JPH0622234B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, it relates to an improvement in a method for forming a multilayer metal wiring.

(2) Background of the technology and problems of the conventional technology With the increase in the integration degree of semiconductor devices, metal, especially aluminum wiring is often formed in multiple layers.
Since the high temperature process of about 400 to 450 ° C. such as the CVD method is often used in the process of forming the interlayer insulating film, the following problems are unavoidable.

(B) During the preheating process of about 400 to 450 ° C. which is performed prior to the execution of the CVD method or the like for the purpose of forming an interlayer insulating layer such as a silicon dioxide layer or a PSG layer, protrusions are formed on the aluminum layer constituting the lower layer (So-called hilllock) occurs, and this protrusion causes unevenness in the thickness of the interlayer insulating film, which causes an interlayer short circuit.

(B) Since the interlayer insulating film is formed on the lower aluminum layer which has expanded considerably at a temperature of about 400 to 450 ° C, if the aluminum layer shrinks when the temperature returns to room temperature, stress will occur in the interlayer insulating film. May occur and cause cracks in the interlayer insulating layer.

(C) For the same reason as above, the aluminum wiring may be damaged or broken.

This drawback is that when protecting a semiconductor device with a glass package, for example, when it is necessary to apply a high temperature process of about 480 ° C. after forming the semiconductor device,
It becomes extremely conspicuous and becomes a serious drawback that is hard to overlook.

(3) Object of the Invention The object of the present invention is to eliminate this drawback, and there is little possibility that an interlayer short circuit or a lower layer metal wiring will be broken.
It is an object of the present invention to provide a method of manufacturing a semiconductor device in which there is little possibility that an interlayer short circuit or a lower layer metal wiring will be broken even when subjected to a high temperature process after forming a multilayer wiring.

(4) Structure of the Invention The present application includes two independent inventions, and the structure of the first invention is planned in a subsequent step of forming a metal wiring in a method of manufacturing a semiconductor device having a multilayer wiring. A method of manufacturing a semiconductor device is characterized in that at least one set of steps of forming an insulating layer is carried out at a temperature obtained by adding about 10 ° C. to about ½ of the maximum temperature.

The above-mentioned drawbacks are that the temperature at which the semiconductor device is placed is (a) the temperature at which the interlayer insulating film is formed (A), and (b) the maximum temperature (B) that the semiconductor device receives after the formation of the multilayer wiring. (C) Room temperature (C), and since the interlayer insulating film is formed at temperature (A), it is generated between the metal wiring and the interlayer insulating film due to thermal expansion. The stress to be applied and its direction are as follows:
When the optimum growth temperature of the ordinary CVD method is 400 to 450 ° C., the metal wiring is damaged due to the reason that the temperature becomes large in the negative direction at the temperature (C) and becomes small in the positive direction at the maximum temperature (B). In order to eliminate this cause, the temperature (A) is about 1/2 of the maximum temperature (B) plus about 10 ° C. which is about 1/2 of room temperature (C). Select around 250 ° C (480 ° / 2 + 20 ° / 2), and set the stress and direction generated between the metal wiring and the interlayer insulating film due to thermal expansion in the negative direction at temperature (C). It is set to a medium level, and is set to a medium level in the positive direction at the maximum temperature (B) to minimize the possibility of damaging the metal wiring and the interlayer insulating film. By the way, if the temperature (A) is made extremely low, for example, about 100 ° C., the stress generated between the metal wiring and the interlayer insulating film and its direction become small in the negative direction at the temperature (C). At temperature (B), it becomes large in the positive direction and the interlayer insulating film is damaged, which is also a problem.

The interlayer insulating film can be formed at the temperature according to the structure of the present invention by using the plasma CVD method or the sputtering method. Further, a large degree of freedom is allowed for the type of this insulating material, and PSG, SiN, SiO ₂ or the like can be used. Further, when the sputtering method is used, TiN or the like may be used.

However, since it cannot be said that the silicon dioxide film formed by the plasma CVD method or the like has an excellent film quality, it is most desirable from the viewpoint of stress by using these low temperature growth methods. After forming an insulating layer having characteristics, an ordinary CVD method is used to form an insulating film having an excellent film quality, and if this double layer is used as an interlayer insulating film, the film quality can be improved in terms of stress. Therefore, it is possible to manufacture a multilayer wiring which is less likely to cause an interlayer short circuit or a lower layer metal wiring disconnection.

According to a second aspect of the invention included in the present application, in the method for manufacturing a semiconductor device having multilayer wiring, metal wiring is formed,
Approximate maximum temperature planned for the subsequent process
At least a set of steps of forming a first insulating layer at a temperature of about 1/2, performing a heat treatment, removing the first insulating layer, and forming a second insulating layer at another temperature 1
A method for manufacturing a semiconductor device is characterized in that a set is executed.

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, since the interlayer insulating film is formed at a relatively low temperature, the plasma CVD method or the sputtering method has to be used, so the problem of stress is solved. However, there remains a drawback that the film quality of the interlayer insulating film is not always satisfactory. The second invention solves this drawback, and similarly to the first invention, the interlayer insulating film is once formed at a temperature at which it is most desirable in terms of stress due to thermal expansion. For the purpose of maintaining this desirable stress state, heat treatment is performed in the state where the above-mentioned interlayer insulating film is formed to alloy the metal forming the metal wiring and rearrange the metal grains to fix the stress state. After that, the interlayer insulating film (insulating layer whose film quality is not necessarily good) is removed, the temperature at which the best film quality is obtained is freely selected, and the interlayer insulating film is formed again. This is to realize the multilayer wiring in the most desirable state in terms of stress and film quality.

As the interlayer insulating film which is initially formed but is removed in a later step, PSG formed by plasma CVD, SiN, SiO ₂ or the like or PSG formed by sputtering, as in the case of the first invention, SiN, SiO ₂ ,
TiN or the like can be used. An interlayer insulating film formed in a later step is PSG formed by using a normal CVD method,
SiN, SiO _{2 and the} like are preferable. The heat treatment temperature for alloying metal electrodes / wirings depends on the type of metal, but in the case of aluminum it is about 400 to 500 ° C, and the heat treatment time is 15
It is desirable that it be about a minute or slightly longer.

(5) Embodiments of the Invention Hereinafter, referring to the drawings, first and second embodiments included in the present application
The step of forming an interlayer insulating film in the method for manufacturing a semiconductor device according to the embodiment of the invention will be further described.

Embodiment of the first invention See FIG. 1 In the figure, 1 is a silicon single crystal layer in which an element is formed, 2 is a field insulating film made of silicon dioxide, and 3 is an aluminum electrode / wiring. After depositing aluminum to a thickness of about 5,000Å,
It is formed by patterning using a photolithography method.

At a temperature of about 250 ° C, a plasma CVD method is used in which a mixed gas of phosphine, monosilane, and nitric oxide is used, the substrate side is grounded, a positive bias voltage is applied to the counter electrode side, and a radio frequency is applied. The PSG film 4 to 500
Å It is formed to a thickness of about.

Then, in the temperature range of 400 to 450 ° C., another PSG film 5 is formed to a thickness of about 9,500 Å by the plasma CVD method using a mixed gas of phosphine, silane and oxygen.

If desired, the aluminum electrode / wiring 3, PSG film 4,
A set with another PSG film 5 is formed in an overlapping manner.

In the multilayer wiring manufactured using the above steps, (a) the stress state between the aluminum electrode / wiring 3 and the PSG film 3 is maintained in the most desirable state, that is, the aluminum electrode / wiring 3 and The stress state between the PSG film 3 and the PSG film 3 is maintained so as to be moderate in the negative direction at room temperature and moderate in the positive direction at the maximum temperature. (B) The film quality of the PSG film 3 is not necessarily excellent. Although it cannot be said that this problem of film quality is sufficiently covered by another PSG film 4 having good film quality, it is an interlayer insulating film which satisfies the object of the present invention.

Although two PSG films are used in the above embodiment, only one PSG film is used, that is, the PSG film 3 is used.
As a matter of course, it does not matter if the thickness is increased to about 1 μm. As stated again, PSG formed by plasma CVD at a low temperature of about 250 ° C
Since the film quality of the film 3 is slightly inferior, it is inevitable that the film 3 is somewhat inferior in terms of reliability.

Embodiment of Second Invention See FIG. 2. In the figure, 1 is a silicon single crystal layer in which elements are formed, 2 is a field insulating film made of silicon dioxide, and 3 is an aluminum electrode / wiring. After depositing aluminum to a thickness of about 5,000Å,
It is formed by patterning using a photolithography method.

At a temperature of about 250 ° C, a plasma CVD method is used in which a mixed gas of phosphine, monosilane, and nitric oxide is used, the substrate side is grounded, a positive bias voltage is applied to the counter electrode side, and a radio frequency is applied. The PSG film 4 to 500
Å It is formed to a thickness of about.

The heat treatment is performed at a temperature of 400 to 500 ° C for about 15 minutes or slightly longer. Since the surface is PSG,
Any gas can be selected. Even oxidizing gas can be used.

In this step, the aluminum electrode / wiring 3 is alloyed to rearrange the atoms, and the desired stress state is fixed and converted into the aluminum electrode / wiring 3 '.

See FIG. 3. The PSG film 4 is removed. This step can be easily performed by using a plasma etching method using a mixed gas of tetrafluoromethane and oxygen as a reaction gas.

Then, in the temperature range of 400 to 450 ° C., the second PSG film 6 is formed to a thickness of about 1 μm by the plasma CVD method using a mixed gas of phosphine, silane and oxygen.

If desired, the above steps are repeated a plurality of times to form a desired number of sets of aluminum electrodes / wirings 3'and second PSG films 6.

In the multi-layer wiring manufactured using the above steps, (a) aluminum electrode / wiring 3'and second PSG film 6
Is maintained at the most desirable state, that is, the stress state between the aluminum electrode / wiring 3'and the second PSG film 6 is moderate in the negative direction at room temperature, and at the maximum temperature. Is held so as to be moderate in the positive direction, and (b) the second PSG film 6 having a good film quality is an interlayer insulating film which surely holds the insulation and satisfies the object of the present invention.

(7) Effects of the Invention As described above, according to the present invention, there is little possibility of interlayer short-circuiting or lower layer metal wiring disconnection. It is possible to provide a method for manufacturing a semiconductor device that is less likely to occur.

[Brief description of drawings]

1 and 2 are sectional views of a substrate for explaining an embodiment of the first invention, and FIG. 3 is a sectional view of a substrate for explaining an embodiment of the second invention. 1 ... Silicon single crystal layer, 2 ... Field insulating film, 3
...... Aluminum electrode / wiring, 3 '... Alloyed aluminum electrode / wiring, 4 ... Insulator layer (PSG film),
5 ... Other insulator layer (other PSG film), 6 ... Second insulator layer (second PSG film).

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device having multi-layered wiring, wherein metal wiring is formed, and an insulating layer is formed at a temperature of about half of the maximum temperature expected in the subsequent steps plus about 10 ° C. A method of manufacturing a semiconductor device, comprising performing at least one set of forming steps. 2. A step of forming an insulating layer at a temperature obtained by adding 10 ° C. to 1/2 of the maximum temperature, and then forming another insulating layer at another temperature. A method of manufacturing a semiconductor device according to claim 1. 3. A method of manufacturing a semiconductor device having multi-layered wiring, wherein metal wiring is formed, and a first insulator layer is formed at a temperature of about ½ of a maximum temperature expected in the subsequent steps. A method of manufacturing a semiconductor device, comprising performing at least one step of performing a heat treatment, removing the first insulating layer, and forming the second insulating layer at another temperature.