JPH0619389B2 - Power supply voltage fluctuation detection circuit - Google Patents

Description

The present invention relates to a circuit provided in a monolithic integrated circuit for detecting fluctuations in a voltage in a device using a DC power supply in a predetermined voltage range.

Many electric and electronic devices require a power supply for their operation, and in particular, a DC power supply within a predetermined voltage range for stable operation, which is obtained by being rectified and stabilized from a commercial AC power supply, does not cause normal operation. Guaranteed to work. This DC power supply is out of the specified voltage range in the following three cases. That is, (a) the power switch is turned on to start the operation of the electric / electronic device, the supplied DC voltage starts rising from the ground potential, and reaches a predetermined voltage range. When the DC voltage is temporarily outside the specified range due to external electrostatic noise or inductive noise, AC power failure, momentary interruption, surge voltage noise caused by lightning / thunder, (c) When the operation of the electric / electronic device is terminated. A transient state in which the power switch is turned off and the DC voltage deviates from the specified range and reaches near the ground potential. In order to protect the device from malfunctions in the case of (a), according to the conventional technology, a time constant circuit consisting essentially of a resistor and a capacitor is provided, and the capacitor is connected via this resistor by the power supply voltage. To charge. The time constant until the voltage across the capacitor reaches a predetermined threshold voltage is made longer than the transient time until the DC power supply voltage actually reaches the predetermined voltage range. If the device is held in the initial state by this time constant signal, the occurrence of malfunction can be suppressed. The product of these values must be increased to lengthen the time constant. However, increasing the product in the monolithic integrated circuit has a limitation on the size of the integrated circuit board. Due to this restriction, the voltage rise time conventionally required for a DC power supply is about 3 times for a P-channel MOS IC.
The time was less than ms, and about 100 μs or less in the complementary MOS IC.

On the other hand, shortening the rise time of the DC power supply requires increasing the weight, volume, and cost of the power supply device.

Therefore, an object of the present invention is to provide a power supply voltage fluctuation detection circuit that stably operates a circuit for giving a signal indicating that it is in the above transient state, without being restricted by this time constant, within the operating temperature range. Is.

FIG. 1 is a conventional initialization signal generation circuit diagram which generates an initialization signal 1 when a power supply voltage rises by using a conventional resistance capacitor time constant circuit. The time constant circuit is a capacitor 2 and two P channel MOS transistors. It is composed of source-drain resistances (ON resistance) 3 and 4. Due to the presence of the diode 5, the voltage applied to the drains of the transistors 3 and 4 is slower than the power supply voltage V _DD and acts to increase the rising time constant. But this effect is small. During the time until the charging voltage exceeds the threshold voltage of the input terminal 16 of the NOR circuit 7, the initialization signal is output from the output 17 of the NOR circuit. Since this initialization signal indicates a transient state until reaching the predetermined voltage range as described above, it is a signal that suppresses the operation start of the device, a timing signal for securing initial conditions in various circuits at the start of operation, or a transient state. It can be used as a signal to notify the operator that there is. Since the conventional circuit shown in FIG. 1 uses a resistor-capacitor time constant circuit, it has a possibility of causing the above-mentioned malfunction and restrictions on the integrated circuit board.

7 and 8 are conventional circuit diagrams for connecting a constant voltage Zener diode 62 and a current limiting resistor 61 to obtain a constant voltage. The circuit of FIG. 8 is a voltage divider circuit composed of 64 and 65. Have. FIG. 10 is a conventional circuit diagram for connecting a current limiting resistor 67 and a diode 66 in series to obtain a constant voltage by utilizing the forward voltage of the diode. Figure 7,
The reference voltage output shown in FIG. 8 and FIG.
It is output from 3. Even if an attempt is made to replace the circuit shown in FIG. 10 with the reference voltage generating circuit of the present invention in the C-MOS, the N-type substrate, the P-well of the anode part and the N ⁺ region of the cathode part of the diode form a transistor. N,
Since it operates as the P and N regions and an excessive current flows, a correct operation cannot be obtained.

FIG. 2 is a circuit diagram of a power supply voltage fluctuation detection circuit according to the present invention.

All circuit elements in Fig. 2 are made on a monolithic semiconductor substrate using insulated gate FET, especially C / MOS technology.
The resistors 21 to 23 are formed by an ion implantation method on a single crystal silicon substrate. This ion implantation can be performed simultaneously with the formation of other circuit elements (the source / drain offset regions of the MOSFET) on the same semiconductor substrate, so that the number of steps is not increased.

In FIG. 2, the N-channel MOS of the reference voltage generating circuit
The source 26 of the transistor 27 is grounded, and the gate 24
And the drain 25 are short-circuited and connected to the + 5V power source (V _DD ) through the resistor 21. Resistors 22 and 23 are
The same 5 volt power supply voltage (V _DD ) is divided into resistors, and the detected voltage that changes in proportion to the change in the power supply voltage is detected by the voltage comparator 2.
8 to non-inverting input 30. The drain 25 of the MOS transistor 27 is connected to the inverting input 29 of the voltage comparator 28 to receive the reference voltage. At the output 31 of the known voltage comparator 28, a positive output voltage appears when the voltage applied to the non-inverting input 30 is larger than the voltage applied to the inverting input 29 thereof, and a zero voltage appears in the opposite case. . The output 31 of the comparator 28 is connected to the waveform shaping circuit 32 and the inverter 33.

FIG. 3 is a diagram for explaining the details of the voltage comparator 28 in FIG. 2, and resistors 21 to 23 and a MOS transistor 27 are also shown at the same time. If the power supply voltage (V _DD ) is resistance-divided by the resistors 22 and 23 and the voltage applied to the gate input 30 of the N-channel MOS transistor 45 (this is the same as the non-inverting input in FIG. 2) decreases, this transistor 45 moves in the direction of cutoff. That is, the current flowing between the source and the drain decreases. The N-channel MOS transistor 41 makes the sum of the currents flowing through the two transistors 29 and 30 a constant current. Therefore, when the current of the transistor 45 decreases, the current flowing through the transistor 46 increases and the output 31 of the comparator 28 decreases. Two transistors 47, 48 and 4 of P and N channels shown in FIG.
9 and 50 are combined to equal one resistor each. However, the area of a pair of transistors of C-MOS structure can be smaller than the resistance by the ion implantation method.

Here, two pairs of transistors 47, 48, and 4 are C / MOS.
By using 9 and 50, the output amplitude of the comparator 28 can be increased. In the conventional load MOS element, when the gate potential is V _DD , the drain side potential is V _DD −
It only rises to V _TH (V _TH is the threshold voltage of the load MOS). On the other hand, if the C-MOS structure of FIG. 3 is used, N
The presence of the channel MOS 47 can cancel the characteristic variation of the other N channel MOSs 45 and 41 due to the variation of the manufacturing parameter. The output of the comparator 28 can be greatly varied from 0 to the V _DD voltage by increasing the channel resistance of the P-MOSs 48 and 49 to increase the ON resistance. on the other hand
ON resistance of N-MOS 47 and 50 shortens the channel length and becomes P
・ Lower than ON resistance of MOS48 and 49.

For example, the channel length of P.MOS 48 and 49 can be about four times the channel length of N.MOS 47 and 50.

Further, the transistor 42 is a temperature compensating circuit inserted in order to correct the characteristic shift due to the temperature of the transistor 41.

That is, this circuit is important for the normal operation of the logic circuit and the like in all the power supply voltage regions of power supply rise, momentary interruption, and fall.

In the embodiment of the present invention, first, the transistor 41 (field effect type MOSFET) is required to operate stably with respect to temperature fluctuations. 43 and transistor 4
By configuring the temperature compensating circuit of No. 4 on the same semiconductor substrate, when the temperature of the transistor 41 rises, the V _TH (threshold value) of the transistor 41 decreases and the V _{TH of} the transistor 42 also decreases. The drain-gate potential of 42 drops. With these configurations, the potential applied to the gate of the transistor 41 is lower than that before the temperature change.

Here, when the temperature drops, the phenomenon opposite to the above occurs, so even if the temperature varies due to the configuration of these temperature compensation circuits, an appropriate voltage for the gate of the transistor 41 according to the temperature can be obtained. Properly compensate for fluctuations in the power supply voltage over the entire temperature range (for example, the range of 0 to 70 degrees Celsius).

Next, since the load transistor 47 and the transistor 50 are the same N-type MOS transistors as the constant current source transistor 41, the load transistor 47 and the transistor 50 have a proportional relationship with respect to a temperature change and can be mutually compensated operationally. A diffusion resistance element may be used instead of the transistor.

However, the compensating load transistor 4 provided in parallel
8, 49 are P-type M different from the constant current source transistor 41
Since it is an OS transistor, the operating parameters are basically different.

Therefore, by the control signal from the temperature compensation circuit including the transistor 42, the resistance element 43, and the transistor 44 described above, it is possible to compensate for these temperature changes to appropriate values.

FIG. 4 shows a sectional view of the MOS transistor 27 and the resistor 21 in the semiconductor substrate. A P well 50 is formed in the low concentration N type semiconductor substrate 49, and the source of the transistor 27 is formed in the P well 50.
The high-concentration N-type regions 51 and 52 to be drains are formed by diffusion. High-concentration P-type guard rings 53 and 54 are P-well 50
Is formed so as to surround the periphery of, and at the same time, high-concentration P-type resistance contact regions 55 and 56 are also formed. A resistor 57 is formed by ion implantation. The ground (V _SS ) line 59 is connected to the P through the through hole of the insulating layer 58 of silicon dioxide.
It is connected to the mold guard ring 53 and the source 51, and the power source (V
_DD ) line 60 is connected to resistor contact area 56 and substrate 49. The mutual wiring 69 connects the drain 52 of the transistor 27 and the resistance contact region 55. 70 is a protective film.

FIG. 5 is a diagram showing how the voltage input to the gates of the transistors 45 and 46 of FIG. 3 changes with respect to the applied power supply voltage. A straight line 74 in FIG. 5 represents the detected voltage (hereinafter, appropriately referred to as “divided voltage”) output from the point where the resistors 22 and 23 in FIG. 3 are connected, and the curve 7
Reference _{numeral 5} denotes a voltage which is output from the point where the resistor 21 and the transistor 27 are connected and which gives a reference potential (V _REF ).

Due to the structure of the MOS transistor 27 described above with reference to FIG. 4, the reference voltage curve 75 in FIG. 5 changes in a convex shape, and as the power supply voltage rises, the divided voltage straight line 74 and the point 7 appear.
After crossing at 6, the reference voltage curve 75 falls below the divided voltage line 74. At this time, the voltage of the inverting input 29 of the comparator 28 becomes smaller than the voltage of the non-inverting input 30, and the comparator 2
The output 31 of 8 goes from zero to a positive voltage. 77, 7
8, 79 will be described later. This output has its waveform adjusted by the waveform shaping circuit 32 by the shift circuit of FIG. 2 and is combined with the timing signal φ _{Y of the} CPU via the inverter 33. This signal then reaches a program counter and an input / output port (both not shown) contained within the same integrated circuit to set them to the desired state. Further, this PD signal is supplied to an external circuit through an output pin of the integrated circuit as needed, and is used to initialize a necessary circuit.

FIG. 6 is a diagram showing how the output COMPD of the comparator 28 and the output PD of the inverter 33 change in response to fluctuations in the power supply voltage. First, when the power is turned on (TA), the power supply voltage rises from zero to + V _DD as indicated by the solid line 81. Second
The input 30 from the voltage _dividing resistors 22 and 23 to the graph comparator 28 rises as shown by the straight line 74 in FIG. 5, while the reference voltage V _REF increases.
The input 29, which rises to, rises as shown by the curve 75. Passing the intersection 76 near V _DD , COMP shown by dotted line 82 in FIG.
D (output of comparator 28) becomes high and output P after waveform shaping
D suddenly approaches zero as shown by the alternate long and short dash line 83, and this PD enables the input / output port and the program counter of the microcomputer formed in the same semiconductor chip.

Next, consider a case where the power supply voltage, which should be + V _DD , temporarily drops by a minute voltage Δv for some reason during normal operation (TB) of the microcomputer and goes out of the allowable range 78 shown in FIG. . In this case, the input to the comparator 28 moves to the area on the left side of the intersection 76 in FIG. 5, and the divided voltage line 74 becomes lower than the reference voltage curve 75. That is, the inverting input 29 of the comparator 28 is greater than the non-inverting input 30, and the output COMPD of the comparator 28 goes from positive to zero.
In response to this, through the waveform shaping circuit 32, the inverter 33
The PD output from the device suddenly rises as shown by the alternate long and short dash line 83 in FIG.

When the power supply voltage returns to + V _DD , the output COMPD of the comparator 28 goes high following the course opposite to the above, and the inverter 3
The output PD of 3 becomes zero again.

When the power is turned off (TC) at the end, when the power is turned on (T
Follow the reverse course of A).

As described above, the comparator 28 responds to the fluctuations at the time of turning on the power supply voltage, the temporary fluctuations during the normal operation and the powering off, and outputs the output COMPD, and the waveform shaping circuit 32 makes the COM.
The rise and fall of PD is suddenly changed to a gradual output signal PD, and this is used to control other circuits of the micro computer.

FIG. 11 shows a configuration in which the reference voltage generating circuit shown in FIG. 7 or 8 can be selectively externally attached to the comparator 28. Also in this example, the transistor 27 and the resistor 2
The circuit itself such as 1 is exactly the same as in FIG. By changing the photo mask for wiring at the stage of patterning metal wiring, which is a process near the end of the IC manufacturing process,
The inverting input 29 of the comparator 28 is connected to the external terminal 91 and is not connected to the transistor 27. The inverting input 29 of the comparator 28 is thus selectively connectable during the manufacturing process and this input is connected to the transistor 27.
Alternatively, it is noted in the switching unit 92 that it can be obtained from any of the external circuits shown in FIGS. 7 and 8.

Up to now, only fluctuations lower than the optimum value of the power supply voltage + V _DD have been considered, but the allowable range of the power supply voltage given to a normal integrated circuit element and circuit device is to specify both the high side and the low side with respect to + V _DD. There is. For example, if an abnormality occurs in the rectifier circuit of the power supply, the allowable range on the high side with respect to + V _DD may be exceeded. FIG. 9 shows a voltage comparator 73 similar to the voltage comparator 28 and resistors 71 and 72 for applying a second reference voltage to its inverting input in the power supply voltage fluctuation detection circuit of FIG.
3 is a circuit diagram in which a resistance division circuit according to FIG. The resistance ratio R ₇₁ / R ₇₂ of the second divided circuit is set to a value different from the resistance ratio R ₂₂ / R _{23 of} the first divided circuit. The second voltage dividing line 53 shown in FIG. 4 is selected so as to intersect with the reference voltage curve 49 at the point 55 at the voltage at the upper end of the power supply voltage allowable range. In this case, the ratio R ₇₁ / R ₇₂ is the ratio R ₂₂ / R ₂₃
Takes a value smaller than. Therefore, the output of the comparator 28 in FIG. 9 is inverted at the point 51, and the output of the comparator 73 is inverted at the point 55.
Flip at. These reversal points 51 and 55 change due to changes in the temperature used or slight differences in the conditions of the semiconductor manufacturing process, but it is easy to suppress them to the extent that there is no practical problem.

Although the power supply voltage V _DD has been described as a positive voltage throughout the specification, the present invention can be applied to a monolithic MOS integrated circuit that operates by applying a negative power supply voltage.

Although the resistors 21 to 23 in FIG. 3 are formed on the integrated circuit substrate by the ion implantation method on the single crystal silicon substrate, they can be replaced by polysilicon resistors.

[Brief description of drawings]

FIG. 1 is a conventional initialization signal generation circuit diagram, FIG. 2 is a power supply voltage fluctuation detection circuit diagram according to the present invention, FIG. 3 is a more detailed diagram of the power supply voltage fluctuation detection circuit of FIG. 2, and FIG. FIG. 5 is a comparison diagram of the reference voltage and the resistance division voltage, FIG. 5 is a sectional view in which the power supply voltage fluctuation detection circuit of the present invention is formed on a semiconductor substrate, and FIG. 6 is a voltage waveform diagram output from the circuit shown in FIG. 7 and 8 are reference voltage generation circuit diagrams, FIGS. 9 and 11 are diagrams showing another embodiment of the power supply voltage fluctuation detection circuit according to the present invention, and FIG. 10 is a reference voltage generation circuit diagram. Is. (Explanation of symbols) 21 to 23 ... Resistor, 27 ... MOS transistor, 2
8, 73 ... Voltage comparator, 32 ... Waveform shaping circuit, 49
...... Reference voltage curve, 52, 53 …… Divided voltage straight line, 54
...... Allowable voltage range.

Claims (1)

[Claims] 1. A circuit for detecting fluctuations in power supply voltage, comprising:
(A) an input terminal that is integrally formed on a semiconductor substrate and that receives a detected voltage; (b) a reference voltage generation circuit that is connected between a power supply voltage source and a ground voltage source and outputs a reference voltage signal; c) a temperature compensation circuit that is connected between a power supply voltage source and a ground voltage source and outputs first and second control signals; and (d) one of the source or drain is connected to the power supply voltage source and the gate is A first FET controlled by a first control signal; and (e) one of a source and a drain is connected to a power supply voltage source, the other of the source and the drain is connected to an output terminal, and the gate is the first control. A second FET controlled by a signal, and (f) one of the source and the drain is the first FET
A third FET connected to the other of the sources or drains of, and the other of the sources or drains to a common node, and the gate of which is connected to the input terminal; and (g) one of the sources or drains of the output A fourth FET connected to the terminal and having the other one of the source and the drain connected to the common node and having the gate controlled by the reference voltage signal; and (h) one of the source and the drain connected to the ground voltage source. And a fifth FET connected to the other of the source and the drain to the common node and having a gate controlled by the second control signal.