JPH061938B2 - Transmission line failure detection relay - Google Patents
Transmission line failure detection relayInfo
- Publication number
- JPH061938B2 JPH061938B2 JP61030985A JP3098586A JPH061938B2 JP H061938 B2 JPH061938 B2 JP H061938B2 JP 61030985 A JP61030985 A JP 61030985A JP 3098586 A JP3098586 A JP 3098586A JP H061938 B2 JPH061938 B2 JP H061938B2
- Authority
- JP
- Japan
- Prior art keywords
- failure
- transmission line
- current
- circuit
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 230000005540 biological transmission Effects 0.000 title claims description 15
- 238000001514 detection method Methods 0.000 title claims description 12
- 230000010354 integration Effects 0.000 claims 3
- 238000006243 chemical reaction Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 238000005070 sampling Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000018199 S phase Effects 0.000 description 4
- 238000001914 filtration Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 101100100125 Mus musculus Traip gene Proteins 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 208000025274 Lightning injury Diseases 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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Description
【発明の詳細な説明】 〔発明の目的〕 (発明の利用分野) 本発明は雷撃などにより送電線に発生した故障を高速か
つ確実に検出しうるリレーに関するものある。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Use of the Invention) The present invention relates to a relay capable of quickly and reliably detecting a failure that has occurred in a power transmission line due to a lightning stroke or the like.
(従来技術とその問題点) 送電線に発生する事故の殆どは地絡故障であり、その主
因は雷撃による送電線と大地間に発生したアークによる
ものが殆どである。このような地絡故障はフラッシュオ
ーバーにもとづくアークの発生初期において、地絡の発
生した送電線路を両端において遮断して無電圧とするこ
とにより消滅する場合が殆どである。従って例えば再閉
路方式のように故障発生の検出後の短い時間、即ち送受
両端間の電圧位相差角が大きく開かないうちに遮断器を
動作させて送電線を無電圧としたのち、アーク消滅に必
要とされる時間後再び遮断器を再投入する再閉路方式が
過渡安定度の向上に有効であり、このためには遮断器の
動作の高速化と故障検出リレーによる故障の高速度かつ
確実な検出が要求される。(Prior art and its problems) Most of the accidents that occur in power transmission lines are ground faults, and the main cause is the arc generated between the power transmission line and the ground due to lightning. In most cases, such a ground fault is extinguished at the initial stage of arc generation due to flashover by cutting off the power transmission line having a ground fault at both ends to leave no voltage. Therefore, as in the reclosing method, for example, after a short time after the occurrence of a failure is detected, that is, before the voltage phase difference angle between the transmitting and receiving ends does not open greatly, the circuit breaker is operated to make the transmission line voltageless, and then the arc is extinguished. The reclosing method, in which the circuit breaker is reclosed after the required time, is effective in improving transient stability.To this end, the circuit breaker operates at high speed and the failure detection relay ensures high speed and reliable operation. Detection is required.
しかし従来において主として超高圧系統に用いられてい
るFM電流差動リレー或いはPCM電流差動リレーは、
現在以上の高速化を望むことは難しい。即ちこの電流差
動リレーRY1,RY2は第1図のように自端Sと、相
手端Rを流れる電流isとiRを用いて ξ(t)=is(t)+iR(t) ………………(1) により故障の検出を行うもの、例えば第1図に示すよう
に送電線L1に発生した故障F1により図中実線矢印方
向の電流is,iRが流れたとき、ξ(t)≠0から内部故障
(保護範囲)、また送電線L2の故障F2により図中点
線矢印方向の電流is,iRが流れたときξ(t)≒0から外
部故障(保護範囲外)と判定するものである。However, the FM current differential relay or the PCM current differential relay, which has been mainly used in the super high voltage system in the past,
It is difficult to hope for higher speeds than at present. That is, as shown in FIG. 1 , the current differential relays RY 1 and RY 2 use the currents s and i R flowing through the self-end S and the opposite end R to obtain ξ (t) = i s (t) + i R (t) …………………… (1) is used to detect a failure, for example, as shown in FIG. 1 , due to a failure F 1 that has occurred in the transmission line L 1 , currents s , i in the direction of the solid line arrow in the figure. When R flows, when ξ (t) ≠ 0, an internal fault (protection range), and when a fault F 2 of the transmission line L 2 causes currents s and i R in the directions of dotted arrows in the figure to flow, ξ (t) From 0, it is judged as an external failure (outside the protection range).
しかし周知のようにこの在来リレーでは故障時流れる電
流からフィルタリングにより押出した基本波成分により
動作させるため、故障時発生する電流中の過渡高調波を
除去する必要がある。このためフィルタリングによる動
作遅延を招く。従って従来リレーによる故障検出では原
理的に現在以上の故障検出速度の向上を望むことは無理
であり、現在以上の過渡安定度の向上を望み得ない。However, as is well known, since this conventional relay is operated by the fundamental wave component extruded from the current flowing at the time of failure by filtering, it is necessary to remove the transient harmonics in the current generated at the time of failure. Therefore, an operation delay is caused by filtering. Therefore, it is impossible in principle to expect the fault detection speed by the conventional relay to be higher than the present fault detection speed, and it is impossible to expect the transient stability higher than the present time.
そこで従来から故障検出速度の向上について研究が行わ
れ、例えば周知の波動方程式 ここで e:電圧、i:電流、x:距離、 t:時間、L:単位長当たりのインダクタン
ス、 C:単位長当たりのキャパシタンス より導かれる周知のベルジュラン(Bergeron)の関係式を
利用した方法が提案されている。Therefore, research has been conducted in the past to improve the fault detection speed. For example, the well-known wave equation Here, e: voltage, i: current, x: distance, t: time, L: inductance per unit length, C: capacitance per unit length, which is derived from the well-known Bergeron relational expression. Is proposed.
即ちこの波動方程式の解はダランベールの解として知ら
れ次式で与えられる。That is, the solution of this wave equation is known as the solution of D'Alembert and is given by the following equation.
ここで f,g:環境条件により決定される任意関数(3)式からgを
消去すると i(t)+1/Ze(t)=2f(t-X/V)…………(4) この式において自端(X=0)をS、相手端(X=d)
をRとして進行波がSからRへ伝わると考えると、各端
における(4)式は ここでis:自端電流、iR:相手端電流、 es:自端電圧、eR:相手端電圧、 となる。そこでこの(4)式のS端の式のtの代わりにt
−d/Vを代入してS端の式からR端の式を引くことに
より、(6)式に示すベルジュランの関係式を得(R端の
−符号は母線から線路方向へ向かう電流を正としたため
である。) ここで τ=d/V(サージ伝播時間) これに(7)式に示す故障検出の条件 を導入した判別関数を示す(8)式 をリレーの動作基本式とするものである。この方法は基
本波成分の外にサージのような高調波成分を含む歪形波
によって内、外部故障を判定しようとするものであっ
て、在来リレーのようにフィルタリングによる基本波成
分の抽出の必要をなくして、抽出にもとづく電流の検出
の遅れをなくし、高速度の故障検出を行おうとするもの
である。 here f, g: If g is deleted from the arbitrary function (3), which is determined by the environmental conditions, i (t) + 1 / Ze (t) = 2f (tX / V) ………… (4) The end (X = 0) is S, the other end (X = d)
Assuming that R is the traveling wave from S to R, equation (4) at each end is Here i s: local end current, i R: remote end current, e s: local end voltage, e R: mating end voltage, and becomes. Therefore, instead of t in the equation at the S end of equation (4), t
By substituting −d / V and subtracting the R-end equation from the S-end equation, we obtain the Bergeran relational expression shown in Eq. (6) (the − sign at the R-end represents the current flowing from the bus to the line direction). This is because it was positive.) Where τ = d / V (surge propagation time) The condition for failure detection shown in Eq. (7) Equation (8) showing the discriminant function with Is the basic operation of the relay. This method is intended to determine an internal or external fault by using a distorted wave that contains a harmonic component such as a surge in addition to the fundamental wave component, and extracts the fundamental wave component by filtering like a conventional relay. The purpose of this is to eliminate the need, eliminate the delay in the detection of the current based on the extraction, and perform the fault detection at high speed.
しかしこの基本式によるリレーは基本的に電圧電流の大
きさから定まるξ(t)の大きさを利用するため、内部と
外部故障の判定が確実ではない。即ち(8)式におけるサ
ージの伝播時間τやサージインピーダンスZには色々な
モードがあり、故障時の電圧電流のように種々の周波数
成分が含まれている場合にはτやZを一義的に定めるこ
とは困難である。これに加えて(8)式は前進波即ちS端
からR端に向う波に注目したものであり、しかも故障点
や測定点即ちリレー設置点等における反射波の影響によ
りサージ成分波に関する差動原理が完全に成立しなくな
るほか、変換器等のハード誤差やノイズの影響により、
外部故障時においてξ(t)≒0にならなくなり、故障判定
精度の点で保護リレーへの適用に問題があった。However, since the relay based on this basic formula basically uses the magnitude of ξ (t) determined by the magnitude of voltage and current, it is not certain to judge internal and external failures. That is, there are various modes in the surge propagation time τ and the surge impedance Z in the equation (8), and when various frequency components such as voltage and current at the time of failure are included, τ and Z are uniquely defined. It is difficult to determine. In addition to this, Eq. (8) focuses on the forward wave, that is, the wave that goes from the S end to the R end, and furthermore, due to the influence of the reflected wave at the failure point or measurement point, that is, the relay installation point, the differential of the surge component wave In addition to the complete failure of the principle, due to the effects of hardware errors and noise from converters,
When an external failure occurs, ξ (t) ≈0 does not hold and there is a problem in application to a protection relay in terms of failure determination accuracy.
本発明は内部、外部故障の識別を高速度で確実に行いう
るリレーを提供して、過渡安定度の一層の向上を図り得
るようにしたものである。次に図面を用いてその詳細を
説明する。The present invention provides a relay capable of reliably identifying internal and external faults at a high speed so that transient stability can be further improved. Next, the details will be described with reference to the drawings.
(問題点を解決するための手段) 本発明は内部故障時前(8)式におけるξ(t)の積分値が故
障種類、故障地点、故障発生位相、線路長、故障点抵抗
の如何を問わず、健全相においては故障発生後変化増減
するが或るレベル以下におさまるのに対し、故障相にお
いては故障発生後ある時間まで単調に増加して大きな値
となり、ξ(t)の積分値は故障前と故障発生後とは顕著
な差異を示す。従って故障発生前と故障後におけるξ
(t)の積分値の大小関係から、内部故障(保護範囲)で
あることを検出できることを着想してなされたものであ
って、本発明の特徴とするところは次の点にある。(Means for Solving Problems) In the present invention, the integral value of ξ (t) in the equation (8) before internal failure does not matter whether the type of failure, the failure point, the failure occurrence phase, the line length, or the resistance of the failure point. On the other hand, in the sound phase, the change increases and decreases after the occurrence of the failure, but stays below a certain level, whereas in the failure phase, it increases monotonically until a certain time after the occurrence of the failure and becomes a large value, and the integral value of ξ (t) is There is a marked difference between before failure and after failure. Therefore, ξ before and after the failure
The present invention has been made in view of the fact that an internal failure (protection range) can be detected based on the magnitude relationship of the integrated value of (t), and the features of the present invention are as follows.
即ち送電系統から検出された自端Sの電流電圧is,es
と、相手端Rの電流電圧iR,eRとに基づき前記(8)式
から得られるξ(t)を、例えば、第2図に示すように所
定の検出対象時間m(例えば前記電流電圧is,esの1/
4サイクル)の間の各サンプリング値を積分することに
よって得られた値に相当する値 S1=▲∫t t−m▼ξ(t)dt…………(9) と、その所定周期n(例えば図中A点から1サイクル)
前の検出時における検出対象時間mの間の各サンプリン
グ値の積分値に相当する値 S2=▲∫t−n t−n−m▼ξ(t)dt…………(10) とを比較し、所定周期n前の積分値S2に対する現時点
の積分値S1の大小関係、例えば両者の比 η(t)=S2(t)/S1(t1)…………(11) または差 η(t)=S2(t)/S1(t)…………(12) を求め、故障発生後のη(t)が或る定められた閾値を越
えたとき内部故障と判定して、動作遅延を招くフィルタ
リングを行うことなく故障の検出を行うようにするもの
である。That current voltage i s the local end S detected from the grid, e s
And ξ (t) obtained from the equation (8) based on the current voltages i R and e R of the other end R, for example, as shown in FIG. i s, of e s 1 /
The value corresponds to a value obtained by integrating the respective sampling values between 4 cycles) S 1 = ▲ ∫ t t -m ▼ ξ (t) dt ............ (9), the predetermined period n (For example, 1 cycle from point A in the figure)
The value corresponding to the integrated value of each sampling value during the detection target time m in the previous detection S 2 = ▲ ∫ t-n t-n-m ▼ ξ (t) dt ………… (10) and By comparison, the magnitude relationship of the integrated value S 1 at the present time with respect to the integrated value S 2 before the predetermined period n, for example, the ratio of the two, η (t) = S 2 (t) / S 1 (t 1 ) ... (11 ) Or the difference η (t) = S 2 (t) / S 1 (t) ………… (12), and when η (t) after the failure exceeds a certain threshold, internal failure Therefore, the failure is detected without performing the filtering that causes the operation delay.
(作用の効果) 第3図(a)(b)は第5図に示す2回線モデル系統におい
て、2線地絡故障が、A−B変電所間の#1L送電線の
F2点(内部故障)のRS相において、故障点抵抗0
Ω、故障発生位相0°で発生した場合の保護区間内であ
るA変電所における面積S2(t)とS1(t)の比η(t)の
変化を、故障回線#1Lと健全回線#2Lについてそれ
ぞれRST相について求めたものである。また第4図
(a)(b)は上記故障時における保護区間外であるB変電所
におけるη(t)の変化を、故障回線#1Lと健全回線#
2LとについてそれぞれRST相について求めたもので
ある。第3図、第4図においてη(t)のプロット間隔は1
0μsec毎である。In view (effect of the action) the 3 (a) (b) is 2 lines model system shown in FIG. 5, 2 line ground fault, # 1L transmission line F 2 points between A-B substation (internal In the RS phase of (fault), the fault point resistance is 0
Ω, the change in the ratio η (t) of the area S 2 (t) to S 1 (t) at the A substation in the protection section when the failure occurs at phase 0 ° # 2L is obtained for each RST phase. Fig. 4
(a) and (b) show the changes in η (t) at the B substation outside the protection section at the time of the above failure, with the failure line # 1L and the healthy line #
2L and 2L, respectively. In Fig. 3 and Fig. 4, the plot interval of η (t) is 1
Every 0 μsec.
これから明らかなように内部故障時には第3図(a)のよ
うに#1Lの健全相Tで故障発生後増加したり減少した
りするが、故障発生前のη(t)=1に近いレベルに収ま
るのに対し、故障相であるR,S相のそれは故障発生後
或る時間まで単調に増加する傾向を示して大きな値とな
る。また健全回線である#2LのR,S,T相のη(t)
も故障発生前のη(t)=1に近い或るレベル以下にな
る。As is clear from this, at the time of an internal failure, it increases or decreases after the failure occurs in the sound phase T of # 1L as shown in FIG. 3 (a), but it is close to the level before η (t) = 1. On the other hand, the values of the R and S phases, which are the failure phases, show a tendency to increase monotonically until a certain time after the occurrence of the failure, and have large values. Also, η (t) of R, S, and T phases of # 2L, which is a healthy line
Also falls below a certain level close to η (t) = 1 before the failure.
従って例えば第3図中に点線によって示すように判定値
を10とした場合、R,S相のη(t)がこれを越えること
によって内部故障と判定でき、また故障発生より5msec
程度で故障の検出が可能であることが判る。Therefore, for example, if the judgment value is set to 10 as shown by the dotted line in FIG. 3, it can be judged as an internal failure if η (t) of the R and S phases exceeds this, and 5 msec after the failure occurs.
It can be seen that the failure can be detected with a certain degree.
また上記の故障に対し、区間外であるB−C間の#1
L,#2Lに設定したリレーでは第4図(a)(b)のように
#1L,#2Lの各相のη(t)は判定値10以下のレベル
以下に収まる。従ってこれから区間B−Cの#1L,#
2Lに設定したリレーは動作せず外部故障と判定する。
以上は故障地点が第5図の1号線のF1〜F6、故障の
種類が#1L回線のR相1線地絡、#1LのR,S相2
線地絡、#1LのR相と#2LのS相にまたがる2相地
絡また故障発生位相が0〜90゜の場合にも同様な結果が
得られ、故障点抵抗を50Ω,100Ωとした場合にも変わら
なかった。For the above failure, # 1 between B and C outside the section
In the relays set to L and # 2L, η (t) of each phase of # 1L and # 2L falls within the level below the judgment value 10 as shown in FIGS. 4 (a) and (b). Therefore, from now on, sections # 1L and #B of section B-C
The relay set to 2L does not work and is judged to be an external failure.
In the above, the failure point is F 1 to F 6 of Line 1 in FIG. 5, the type of failure is the R phase 1 wire ground fault of the # 1L line, and the R and S phase 2 of the # 1L.
Similar results are obtained when a line ground fault, a two-phase ground fault that spans the R phase of # 1L and an S phase of # 2L, or a fault occurrence phase is 0 to 90 °, and the fault point resistance is set to 50Ω and 100Ω. It didn't change even if.
(実施回路例) 第6図においてLは送電線、DV1,DI1およびDV
2,DI2は両端、S,R端の各相電圧各相電流es,
isおよびeR,iRの検出器、RY1,RY2は本発明
リレーであって、次の各部から構成される。IR1,I
R2は入力変換器で、各相電圧電流をリレーの動作演算
に適したレベルに変換する。SH1,SH2はサンプリ
ングホールド回路であって、サンプリング同期信号発生
回路SSからの信号によって検出器DV1,DV2,D
I1,DI2による各相電圧電流を例えばA/D変換で
10μsec毎にサンプリングするために、各データをホー
ルドする回路である。A/D1,A/D2はアナログ・
ディジタル変換器、PU1,PU2は演算処理部であっ
て、これは中央演算処理素と、本発明のリレー論理、ト
リップシーケンス、自動監視機能等のプログラムが格納
されているROMと、リレー演算の途中結果等が一時的
に記憶されるRAMから構成される。P/S1,P/S
2はパラレル・シリアル変換回路、PI1,PI2は光
インタフェイス回路、S/P1,S/P2はシリアル・
パラレル変換回路であって、アナログ・ディジタル変化
器A/D1,A/D2はサンプリングされた電圧電流の
アナログ信号をディジタル信号に変換して演算処理部P
U1,PU2に加えると共に、パラレル・シリアル変換
回路P/S1,P/S2と光インタフェイス回路、PI
1,PI2、光伝送回路PLを介してそれぞれ相手リレ
ーRY1,RY2に伝送する。そして受信された各相の
es,isまたはeR,iRなどのシリーズ信号をシリアル
・パラレル変換回路S/P1,S/P2によりパラレル
信号に変換して、演算処理部PU1,PU2に加えて、
前記ξ(t)の積分と、その途中結果の記憶、η(t)の演算
を行わせる。IO1,IO2は入出力インタフェイス回
路であって、リレー演算結果、その結果にもとづく遮断
器のトリップ指令、開閉路指令等の入出力処理を行う。(Example of Implementation Circuit) In FIG. 6, L is a transmission line, DV 1 , DI 1 and DV.
2 , DI 2 are both phase voltages at both ends, S and R ends, phase currents es ,
The detectors i s and e R , i R , and RY 1 and RY 2 are the relays of the present invention, and are composed of the following parts. IR 1 , I
R 2 is an input converter that converts each phase voltage / current into a level suitable for operation calculation of the relay. SH 1 and SH 2 are sampling and holding circuits, and detectors DV 1 , DV 2 and D are detected by a signal from the sampling synchronization signal generating circuit SS.
For example, A / D conversion of each phase voltage / current by I 1 and DI 2
This circuit holds each data in order to sample every 10 μsec. A / D 1 and A / D 2 are analog
The digital converters PU 1 and PU 2 are arithmetic processing units, which include a central arithmetic processing unit, a ROM storing programs such as the relay logic, trip sequence, and automatic monitoring function of the present invention, and relay arithmetic processing. It is composed of a RAM for temporarily storing the intermediate results and the like. P / S 1 , P / S
2 is a parallel / serial conversion circuit, PI 1 and PI 2 are optical interface circuits, and S / P 1 and S / P 2 are serial
In the parallel conversion circuit, the analog / digital converters A / D 1 and A / D 2 convert an analog signal of the sampled voltage and current into a digital signal to operate the processing unit P.
In addition to U 1 and PU 2 , parallel / serial conversion circuits P / S 1 and P / S 2 and an optical interface circuit, PI
1 and PI 2 and the optical transmission circuit PL to the respective relays RY 1 and RY 2 respectively. Then, the received series signals such as e s , i s or e R , i R of each phase are converted into parallel signals by the serial / parallel conversion circuits S / P 1 and S / P 2 , and the arithmetic processing unit PU 1 , In addition to PU 2 ,
The integral of ξ (t), the storage of the intermediate result, and the calculation of η (t) are performed. IO 1 and IO 2 are input / output interface circuits, which perform input / output processing such as relay calculation results, and circuit breaker trip commands and switching circuit commands based on the results.
第1図は従来リレーの説明図、第2図は本発明の原理説
明のための波形図、第3図,第4図はモデル系統による
本発明の判定動作の説明図、第5図はモデル系統図、第
6図は本発明のリレーの一実施例回路例図である。 S…自端、R…相手端、es,eR…電圧、is,iR…電
流、L1、L2…送電線、#1L,#2L…1号および
2号線、DV1,DV2…電圧検出器、DI1,DI2
…電流検出器、RY1,RY2…リレー、IR1,IR
2…入入力変換器、SH1,SH2…サンプリングホー
ルド回路、A/D1,A/D2…アナログ・ディジタル
変換器、SS…サンプリング同期信号発生回路、P
U1,PU2…演算処理部、P/S1,P/S2…パラ
レル・シリアル変換回路、PI1,PI2…光インタフ
ェイス回路、S/P1,S/P2…シリアル・パラレル
変換回路、IO1,IO2…入出力インタフェイス回
路。FIG. 1 is an explanatory diagram of a conventional relay, FIG. 2 is a waveform diagram for explaining the principle of the present invention, FIGS. 3 and 4 are explanatory diagrams of the determination operation of the present invention by a model system, and FIG. 5 is a model. A system diagram, FIG. 6 is an example circuit diagram of an embodiment of the relay of the present invention. S ... local end, R ... remote end, e s, e R ... voltage, i s, i R ... current, L 1, L 2 ... transmission line, # 1L, # 2L ... 1 No. and Line 2, DV 1, DV 2 ... Voltage detector, DI 1 , DI 2
... Current detectors, RY 1 , RY 2 ... Relays, IR 1 , IR
2 ... Input-input converter, SH 1 , SH 2 ... Sampling / holding circuit, A / D 1 , A / D 2 ... Analog / digital converter, SS ... Sampling synchronization signal generating circuit, P
U 1 , PU 2 ... Arithmetic processing unit, P / S 1 , P / S 2 ... Parallel / serial conversion circuit, PI 1 , PI 2 ... Optical interface circuit, S / P 1 , S / P 2 ... Serial / parallel Conversion circuit, IO 1 , IO 2, ... Input / output interface circuit.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大槻 博司 大阪府大阪市北区中之島3−3−22 関西 電力株式会社内 (72)発明者 小川 正 大阪府大阪市北区中之島3−3−22 関西 電力株式会社内 (56)参考文献 特開 昭53−109142(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Otsuki 3-3-22 Nakanoshima, Kita-ku, Osaka City, Osaka Prefecture Kansai Electric Power Co., Inc. (72) Tadashi Ogawa 3-3-22 Nakanoshima, Kita-ku, Osaka City, Osaka Prefecture Kansai Electric Power Co., Inc. (56) Reference JP-A-53-109142 (JP, A)
Claims (1)
esと相手端の電流iR電圧eRを用いて波動方程式によ
り導かれるベルジュランの関係式に基づく判別関数の値 ξ(t)=is(t-τ)+iR(t) +1/Z{es(t-τ)-eR(t)} (ただし、tは時間、τはサージ伝播時間、Zはサージ
インピーダンスとする。) を所定時間mに亘って積分する積分回路と、この積分回
路による現時点の積分値S1と所定整数倍周期n前の積
分値S2とを比較する比較回路と、この比較回路による
比較結果が予め定められた閾値を越えたとき内部送電線
に故障が生じたものと判定する判定回路とを備えた送電
線の故障検出リレー。1. A value of a discriminant function ξ (t based on a Bergerand's relational expression derived from a wave equation using a current i s and a voltage e s at its own end and a current i R voltage e R at the other end in a transmission line. ) = i s (t-τ) + i R (t) + 1 / Z {e s (t-τ) -e R (t)} (where t is time, τ is surge propagation time, and Z is surge impedance ) For a predetermined time m, a comparison circuit for comparing the current integration value S 1 by the integration circuit with the integration value S 2 before the predetermined integer multiple cycle n, and this comparison circuit A failure detection relay for a power transmission line, comprising: a determination circuit that determines that a failure has occurred in the internal power transmission line when the comparison result of 1 exceeds a predetermined threshold value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61030985A JPH061938B2 (en) | 1986-02-17 | 1986-02-17 | Transmission line failure detection relay |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61030985A JPH061938B2 (en) | 1986-02-17 | 1986-02-17 | Transmission line failure detection relay |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62193509A JPS62193509A (en) | 1987-08-25 |
| JPH061938B2 true JPH061938B2 (en) | 1994-01-05 |
Family
ID=12318920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61030985A Expired - Lifetime JPH061938B2 (en) | 1986-02-17 | 1986-02-17 | Transmission line failure detection relay |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH061938B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5933305A (en) * | 1998-06-02 | 1999-08-03 | Eaton Corporation | Arc fault detector comparing integrated interval to interval filtered load current and circuit breaker incorporating same |
| CN121500087B (en) * | 2026-01-13 | 2026-04-28 | 南京苏铁经济技术发展有限公司 | A method and system for online monitoring of relay status in urban rail transit trains |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53109142A (en) * | 1977-03-04 | 1978-09-22 | Tokyo Electric Power Co Inc:The | Input device protective relay |
-
1986
- 1986-02-17 JP JP61030985A patent/JPH061938B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62193509A (en) | 1987-08-25 |
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