JPH0620049B2 - Method for forming compound semiconductor layer - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for forming a compound semiconductor layer, and more particularly to a method for forming a high quality compound semiconductor layer on a substrate using a silicon substrate. Is.

<Conventional technology and its problems> Compound semiconductors such as GaAs and InP are being utilized for high performance and high performance devices by taking advantage of their excellent features. However, compound semiconductor crystals are generally expensive, and problems such as difficulty in obtaining a large-area high-quality substrate crystal have not been solved. As an attempt to overcome such a problem, an inexpensive, high-quality, lightweight silicon substrate is used to stack a compound semiconductor layer on the silicon substrate, and the above-described device is formed on the stacked compound semiconductor layer. Attempts have been made to manufacture semiconductor devices.

Although several methods of manufacturing a compound semiconductor device using such a silicon substrate have been proposed in the past, the present situation is that they are still inferior to bulk crystals in terms of crystal quality and the like.

For example, as an attempt to form a single crystal GaAs layer on a silicon (Si) substrate, the following method is currently being attempted.

That is, when forming a GaAs layer on a silicon (Si) substrate,
This is a so-called two-step growth method in which a preliminary deposition layer is formed in advance and then GaAs is epitaxially grown under normal growth conditions. As the preliminary deposition layer, a GaAs layer, a Ge layer, or GaAsP and G formed at a temperature lower than the normal growth conditions.
A buffer layer in which aP and GaAs are alternately laminated is used.

As an example, the growth process of the two-step growth method using a GaAs layer as a predeposition layer is described below.

First, an about 100 Å GaAs layer is formed on a silicon (Si) substrate at a temperature of 450 ° C. or lower by MOCVD or MBE, and then the normal GaAs epitaxial growth temperature (600
After the temperature of the substrate is raised to (° C. to 750 ° C.), a GaAs layer is grown.

Figure 5 shows a silicon (Si) substrate 1 obtained by the two-step growth method.
3 is a schematic view showing the structure of the upper GaAs layer 2, and 3 is a pre-deposition layer.

When any of the above-mentioned ones is used as the pre-deposition layer 3, high density mismatch dislocations are generated in the interface region between Si and GaAs due to the difference in lattice constant between Si and GaAs (up to 4%). The part propagates in the growth direction during growth and penetrates the growth layer. In particular, since the stress due to a large difference in expansion coefficient between the silicon (i) substrate 1 and the compound semiconductor layer (GaAs layer) 2 greatly accelerates the propagation of dislocations in the growth direction during the temperature decrease from the growth temperature to the room temperature after the growth, The dislocation reaches the active layer formation region in the vicinity of the surface and most affects the device performance when the device is formed on the GaAs layer 2.

The density of misfit dislocations generated in the interface region between Si and GaAs is about 10 ¹² cm ^-2 , and the density of dislocations reaching the GaAs surface after stacking 3 μm of GaAs is about 10 ⁸ cm ^-2. It is found from observation by a transmission electron microscope (TEM) and measurement result of etch pitch density (EPD) using molten KOH. Since dislocations act as recombination centers of minority carriers, they significantly reduce the minority carrier lifetime in crystals having high density dislocations. Therefore, the performance of a compound semiconductor device using a minority carrier is significantly reduced.

The present invention has been made in view of the above points, and has been improved by solving the problem of deterioration of crystal quality due to the occurrence of high-density dislocations when forming a compound semiconductor layer on a conventional silicon substrate. It is an object to provide a method for forming a compound semiconductor layer.

<Means and Actions for Solving Problems> In order to achieve the above object, the present invention increases the mechanical yield strength of substrate silicon when forming a structure in which a compound semiconductor layer is grown on a silicon substrate. In addition to using a silicon substrate in which the added amount of elements is suppressed below the solid solution hardening concentration, the growth wafer is subjected to a temperature difference from the growth temperature during or after the growth in addition to a temperature decreasing step of returning the growth wafer from the growth temperature to room temperature. It is configured to have a treatment step including at least one or both of a temperature increase step of 100 ° C. or higher and a temperature decrease step.

That is, according to the present invention, in a method of forming a compound semiconductor layer on a silicon (Si) substrate, the propagation of dislocations due to mismatching dislocations existing between the substrate and the compound semiconductor layer and thermal stress is more efficiently compared to the conventional method. By confining it in the vicinity and reducing dislocations in the upper layer compound semiconductor device active layer forming region, it is possible to provide a compound semiconductor device that enables high quality, low cost and weight reduction. The method for improving the crystallinity of the growth layer by absorbing the thermal stress generated in the temperature decreasing process to the room temperature after the growth used in the present invention on the silicon side of the substrate to relax the stress is understood as follows. be able to.

That is, since the generation and propagation of dislocations are promoted by the local stress concentration, the silicon (Si) substrate and GaAs are
When thermal stress based on the difference in thermal expansion coefficient in the layer is applied to the growth layer, dislocations in the vicinity of the pre-deposition layer propagate to the surface of the crystal layer and release some of the thermal stress in the crystal, resulting in stress relaxation. Thermal stress acts on both the GaAs layer near the interface between silicon and GaAs and the silicon substrate. However, the silicon substrates conventionally used for forming compound semiconductor layers are all CZs that contain about 20 ppm of impurity oxygen as a solid solution. Since it was cut out from a crystal called silicon, stress relaxation was extremely unlikely to occur, and stress relaxation was supposed to occur exclusively in the GaAs layer.

Generally, when manufacturing a silicon device, a wafer is
It is necessary to bring it to a high temperature exceeding 00 ° C. and repeat the impurity diffusion step, the insulating film forming step, and the like. Since a high-purity silicon wafer is warped by a large number of these high-temperature heat treatment steps to reduce the yield, impurity oxygen is added in order to prevent plastic deformation even by high-temperature heat treatment.
A silicon wafer with 0 ppm solid solution is used.

Regarding silicon, oxygen is generally known as an impurity element that causes solid solution hardening, but nitrogen also causes solid solution hardening. The concentration of oxygen and nitrogen at which solid solution hardening becomes remarkable (the solid solution hardening concentration) is roughly 1 ppm.
And 0.1 ppm.

However, when a compound semiconductor device is manufactured, the high temperature heat treatment step is not repeated for the purpose of preventing crystal deterioration because the group V element forming the compound semiconductor has a large vapor pressure. Therefore, when forming a compound semiconductor layer on a silicon substrate, it is not necessary to use a solid solution hardening silicon substrate, but rather it is formed by causing stress relaxation near the interface between silicon and the compound semiconductor, especially on the silicon substrate side. Avoid concentration of stress acting on the compound semiconductor layer,
In order to reduce the dislocation density on the surface of the growth layer, it is important to reduce the added amount of the impurity element that causes the solid solution hardening of the substrate silicon.

When the solid solution hardening elements such as oxygen and nitrogen are set to the solid solution hardening concentration or less, the thermal stress acting on the silicon substrate and the compound semiconductor layer when the temperature rises and falls is effectively absorbed not only in the compound semiconductor layer but also in the silicon substrate side. As a result, stress relaxation progresses smoothly, and as a result, it becomes possible to form a compound semiconductor layer of higher quality than ever before on a silicon substrate.

<Examples> Hereinafter, the present invention will be described in detail based on Examples. Although the following examples describe formation of the GaAs semiconductor layer,
The present invention is not limited to this. For example, GaP, I
It goes without saying that the same can be applied to the formation of other III / V group compound semiconductor layers such as nP or GaInAs mixed crystals.

Example 1 FZ containing neither oxygen nor nitrogen in an amount of 0.1 ppm or more
A GaAs layer was formed on a silicon substrate by a known growth method such as the two-step growth MOCVD method. More specifically, for example, a two-step growth by MOCVD method is performed using a high frequency heating / water cooling reaction tube, and a growth temperature (Tgr) = 700 ° C. is applied to a silicon substrate.
A GaAs layer was formed. Further, in the process of forming the GaAs layer, in order to more effectively absorb the thermal stress acting on the silicon substrate and the GaAs layer in the silicon substrate, as shown in FIG.
The growth of the As layer is stopped during the growth, and the temperature of the growth wafer is changed from the growth temperature (Tgr) to 100 ° C. while the growth is restarted.
The treatment step (temperature raising / lowering step) of lowering the temperature to the lower temperature and returning to the original growth temperature was added once or more.

For comparison, a CZ silicon substrate containing about 20 ppm of oxygen was used to form a GaAs layer in the same process as described above.

As a result, in comparison with the dislocation density of 1 × 10 ⁷ cm ⁻³ of the GaAs layer formed on CZ silicon containing about 20 ppm of oxygen, according to the embodiment of the present invention, on FZ silicon not containing oxygen and nitrogen of 0.1 ppm or more. Dislocation density of 1 ×
It was 10 ⁶ cm ⁻³ , and it was found that the reduction of dislocation density was remarkable.

Example 2 In place of the temperature raising / lowering step shown in FIG. 1 in the above Example, the temperature raising / lowering step during growth shown in FIG. 2 or the temperature raising / lowering step after growth shown in FIGS. 3 and 4 was performed. In either case, compared with the dislocation density of 5 × 10 ⁶ cm ⁻³ of the GaAs layer grown using the silicon substrate containing about 20 ppm of oxygen,
It was found that the dislocation density of the GaAs layer using silicon containing no oxygen or nitrogen of 0.1 ppm or more is 1 × 10 ⁶ cm ^-3 or less, and the dislocation density can be efficiently reduced. .

It was also found that the temperature raising / lowering process shown in FIGS. 1 to 4 requires temperature raising / lowering of at least a temperature difference (ΔT) of 100 ° C. or more in order to effectively absorb the thermal stress in the substrate silicon.

1 to 4, T _RT is room temperature, T _gr is growth temperature, and ΔT is a temperature difference of 100 ° C. or more.

As described above, according to the present invention, Ga on a silicon substrate is
The dislocation density of the As layer can be extremely effectively reduced as compared with the conventional one.

By reducing the dislocation density of a compound semiconductor formed on a silicon (Si) substrate by the method of the present invention, it can be used as a semiconductor substrate for various electronic devices and optical devices. In particular, a PN junction is formed on the compound semiconductor. By forming a solar cell, the excellent effect is exhibited. That is, the light-receiving surface side can be formed using a GaAs layer or InP layer with high photoelectric conversion efficiency, and the substrate supporting this compound semiconductor layer can be constructed using a relatively light and strong Si substrate. ， It is possible to obtain a solar cell that is very advantageous in terms of weight.

<Effects of the Invention> As described above, according to the present invention, it becomes possible to form a higher-quality compound semiconductor single crystal layer on a silicon (Si) substrate than ever before, and as a result, a compound semiconductor device It can greatly contribute to the reduction of price and weight.

[Brief description of drawings]

1 to 4 are views showing examples of temperature programming of a dislocation density reduction method according to the method of forming a compound semiconductor layer of the present invention, and FIG. 5 illustrates a method of forming a compound semiconductor layer on a silicon substrate. It is a schematic diagram of a substrate structure for doing. 1 ... Silicon substrate, 2 ... GaAs layer, 3 ... Pre-deposited layer.

Claims (2)

[Claims] 1. When growing a compound semiconductor layer on a silicon substrate, a temperature lowering step of returning the growth wafer from the growth temperature to room temperature, and a temperature difference of 100 ° C. or more from the growth temperature of the growth wafer during or after the growth. And a treatment step including at least one of a warming step and a temperature lowering step at least once or more, wherein an element that increases the mechanical yield strength of the substrate silicon as the silicon substrate is suppressed to a solid solution hardening concentration or less. A method of forming a compound semiconductor layer, which comprises using an added substrate. 2. The method for forming a compound semiconductor layer according to claim 1, wherein the elements to be suppressed below the solid solution hardening concentration are oxygen and / or nitrogen.