JPH0533528B2 - - Google Patents

Description

[Detailed description of the invention]

<Industrial Application Field> The present invention relates to a method for forming a compound semiconductor layer, and particularly to a method for forming a high quality GaAs compound semiconductor layer on a silicon substrate using a silicon substrate. <Conventional technology> Compound semiconductors such as GaAs and InP are being used for high performance and high functionality devices by taking advantage of their excellent characteristics. However, compound semiconductor crystals are generally expensive, and problems such as difficulty in obtaining large-area, high-quality substrate crystals remain unsolved. In an attempt to overcome these problems, we used cheap, high-quality, and lightweight silicon as a substrate, stacked compound semiconductor layers on this silicon substrate, and then constructed the aforementioned devices on the stacked compound semiconductor layers. Attempts have been made to manufacture semiconductor devices. Although several methods for manufacturing compound semiconductor devices using such silicon substrates have been proposed, they are still inferior to bulk crystals in terms of crystal quality and the like. For example, the following methods are currently being attempted to form a single crystal GaAs layer on a silicon (Si) substrate. That is, when forming a GaAs layer on a silicon (Si) substrate, it is a so-called two-step growth method in which a preliminary deposition layer is formed in advance, and then GaAs is epitaxially grown under normal growth conditions. The preliminary deposition layer can be a GaAs layer, a Ge layer, or a GaAsP and GaP layer formed at a lower temperature than normal growth conditions.
A buffer layer in which GaAs and GaAs are alternately laminated is used. As an example, the growth process using a two-step growth method using a GaAs layer as a preliminary deposition layer will be described below. First, a film of about 100 Å was deposited on a silicon (Si) substrate using MOCVD or MBE at a temperature below 450°C.
After forming a GaAs layer, the substrate is heated to a normal GaAs epitaxial growth temperature (600°C to 750°C), and then a GaAs layer is grown. FIG. 4 is a schematic diagram showing the structure of a GaAs layer 2 on a silicon (Si) substrate 1 obtained by a two-step growth method, and 3 is a preliminary deposited layer. No matter which of the above-mentioned materials is used as the predeposition layer 3, in the interface region between Si and GaAs, the Si and GaAs
The difference in the lattice constants of GaAs (~4%) generates a high density of mismatched dislocations, some of which propagate in the growth direction during growth and penetrate the grown layer. In particular, the stress caused by the large difference in expansion coefficient between the silicon (Si) substrate 1 and the GaAs layer 2 during cooling from the growth temperature to room temperature after the completion of growth greatly promotes the propagation of dislocations in the growth direction. When reaching the active layer formation region and manufacturing a device on the GaAs layer 2, it has the greatest effect on device performance. The density of mismatched dislocations generated in the interface region between Si and GaAs is approximately 10 ¹⁰ cm ^-2 , and the density of dislocations that have reached the GaAs surface after stacking 3 μm of GaAs is approximately 10 ⁸ cm
^-2 , based on observation using a transmission electron microscope (TEM) and measurements of etching pitch density (EPD) using molten KOH. Dislocations act as recombination centers for minority carriers, causing a significant decrease in minority carrier lifetime in crystals with high density dislocations. Therefore, the performance of a compound semiconductor device using minority carriers is significantly degraded. As a method to reduce this high density dislocation, Tsaur et al. proposed a combination of growth interruption and thermal cycling (16th, IEEE PVSC,
1982). 5A to 5C are diagrams for explaining one cycle of this method, in which a silicon (Si) substrate 1
The upper part shows a case in which Ce is used as the preliminary deposit layer 3, and FIG. When the growth is interrupted as shown in Figure B, the substrate temperature is lowered from 700°C to room temperature, and dislocation loops are formed by interaction between dislocations, and in the subsequent second growth layer 22 (Figure 5C), dislocations are reduced. are doing. Furthermore, they confirmed the dislocation reduction effect only after repeating the process shown in FIGS. 5A to 5C more than 10 times. <Problems to be Solved by the Invention> However, when the above conventionally proposed processes are actually applied to manufacturing, there is a problem with the process time described below. For example, when using a metal organic chemical vapor deposition (MOCVD) method using a high-frequency heating/water-cooling reaction tube method, which requires relatively short heating and cooling times, GaAs The time required to form a grown layer is approximately 1 hour, whereas if 10 thermal cycles are performed, the time required for the growth process is over 7 hours, which is extremely long. Furthermore, the time required to carry out 20 thermal cycles is over 12 hours, and it is clear that there are major manufacturing obstacles in terms of time and efficiency in improving crystallinity using this method. The present invention was created in view of the above points, and an object of the present invention is to provide a novel and improved method for forming a compound semiconductor layer that solves the problems encountered when growing a compound semiconductor layer on a conventional silicon substrate. It is an object. <Means and effects for solving the problems> In order to achieve the above object, the method for forming a compound semiconductor layer of the present invention involves growing a GaAs compound semiconductor layer on a silicon substrate, similar to the proposal by Zuur et al. By repeating the growth of the compound semiconductor layer, the interruption of the growth, and the temperature drop during the interruption,
In the method for forming a compound semiconductor layer in which a compound semiconductor layer is sequentially grown in layers for each thermal cycle to form a compound semiconductor layer on the silicon substrate by the thermal cycle, the cooling temperature width of the thermal cycle is 250° C. or more, and the lower limit temperature of the thermal cycle.
It is characterized by a temperature of 300℃ or higher. That is, the present invention is a method for forming a compound semiconductor layer on a silicon (Si) substrate, and can reduce the propagation of mismatched dislocations existing between the substrate and the compound semiconductor layer and dislocations caused by thermal stress in a shorter time than in conventional methods. By efficiently confining dislocations near the interface and reducing dislocations in the active layer forming region of the upper compound semiconductor device, it is possible to provide a compound semiconductor device that is high quality, low cost, and lightweight. The method used in the present invention for improving the crystallinity of a grown layer by applying thermal stress during growth can be understood as follows. That is, since the generation and propagation of dislocations are promoted by local stress concentration, thermal stress based on the difference in thermal expansion coefficient between the silicon (Si) substrate and the GaAs layer is applied to the grown layer during cooling after the growth is interrupted. The dislocations near the pre-deposited layer are propagated to the surface of the crystal layer and release part of the thermal stress in the crystal. After raising the temperature again,
When a 2GaAs layer is grown and the temperature is lowered, the dislocations in the first growth layer may form loops with each other, or point defects caused by impurities present in the growth layer may stick on the dislocations, causing dislocation propagation. is prevented (this is called dislocation immobilization). In this way, the dislocation density propagating to the second growth layer is
It is possible to reduce it compared to that in the layer. Therefore, dislocations reach the active layer region near the growth surface by repeatedly forcibly forming dislocation loops by applying thermal stress to the growing layer when the temperature is lowered, and immobilizing the dislocations by reducing the thermal stress when the temperature is rising. This makes it possible to reduce the Based on the above understanding, the present invention aims to significantly shorten the process time by selecting the most effective thermal cycle temperature range for forming dislocation loops and immobilizing dislocations by forcibly introducing light atoms, and as a manufacturing technology. In particular, the present invention enables the adoption of The dislocation rate decreases rapidly with decreasing temperature. The crystal contains point defects caused by impurities, but the temperature at which dislocations become immobilized has not been clarified. In view of this, the cooling temperature range of the thermal cycle was set at 250℃.
The present invention is characterized in that the lower limit temperature of the heat cycle is set to 300°C or higher. <Examples> The present invention will be described in detail below based on Examples. Example 1 A GaAs single crystal was grown to a thickness of 3 μm on a Si (100) substrate at 700°C using a two-step MOCVD method using a high-frequency heating/water-cooled reaction tube, and the dislocation density near the surface of the grown layer was measured by planar TEM or by molten KOH
It was evaluated using the EPD measurement method. As an example of applying the thermal cycle conditions of the present invention, the lower limit temperature T _D of the thermal cycle is used to shorten the growth stop time.
= 300°C, the initial temperature cooling rate was approximately 2°C/sec, and 10 temperature-lowering/heating thermal cycles were performed for each growth layer thickness of 0.1 μm (Figure 1). The dislocation density near the sample surface was measured, and the thermal cycle was performed as shown in Table 1 when compared with the sample (Figure 3a), which was carried out based on the conventional method with the lower limit temperature T _D = 90°C. From the dislocation density of the sample without 1 × 10 ⁸ cm ^-2 , T _D = 90
℃ and T _D = 300℃, the dislocation density was reduced to 2 × 10 ⁷ cm ^-2 for both samples, and it was found that the reduction in dislocation density was the same between T _D = 90 and 300℃. I understand. In other words, it was found that the long temperature-lowering process from below 300°C to near room temperature hardly contributed to the reduction of dislocations. but
When T _D =450°C or higher, the effect of reducing dislocation density decreased. This changes the growth temperature to the same as in the previous example.
Since the temperature was set at 700°C, the range of cooling temperatures that can contribute to dislocation reduction is reduced, and as mentioned above, ``The larger the range of cooling temperatures, the greater the thermal stress in the growth layer that is effective for dislocation movement (loop formation). This is because the effect of ' is slightly reduced. Further, when the growth was interrupted for 10 minutes, each for 7 minutes, without lowering the temperature, no reduction in dislocation density was observed. Example 2 When the temperature increase range was shifted to the high temperature side in order to confirm the effect of the present invention, that is, after the growth was interrupted, the temperature was raised to the upper limit temperature Tv = 850°C according to the temperature program shown in Figure 2, and then the lower limit temperature lowered. Even for samples cooled in the temperature range of 400℃ up to T <sub>D</sub> = 450℃, the dislocation density is 2.
×10 <sup>-7</sup> cm <sup>-2</sup> , and the reduction effect was confirmed. In this case as well, the time required for the growth process was reduced to about 1/3 compared to the case where T <sub>D</sub> ~90°C. In this way, by setting the lower limit temperature to 300° C. or higher instead of room temperature, there is no time for wasted temperature reduction, and the time required for the growth process can be significantly shortened. Moreover, when the cooling temperature range of the thermal cycle is set to, for example, 400°C, that is, when T <sub>D</sub> of Example 1 is set to 300°C (see the third row of Table 1), and when the temperature range of Example 2 is set to 400°C, In both cases, when the temperature is temporarily raised before the growth is interrupted (see the fifth row of Table 1), the dislocation density decreases when the temperature is lowered to the conventional room temperature (see the second row of Table 1). ), 2×10 <sup>7</sup>
It can be reduced to cm <sup>-2</sup> . this is
This shows that a lower limit temperature of 300°C or less contributes little to dislocation reduction. On the other hand, it is necessary to ensure that the cooling temperature range is at least a predetermined range. This is because, as mentioned above, ``The larger the cooling temperature range, the greater the thermal stress in the growth layer that is effective for dislocation movement (loop formation). This is because dislocations can be reduced by repeating forced dislocation loop formation by applying thermal stress to the growth layer when the temperature is lowered, and immobilization of dislocations by reducing the thermal stress when the temperature is rising. This is because the magnitude of thermal stress depends on the cooling temperature range. For this reason, it is desirable that the cooling temperature range is at least 250°C or more. Even if the lower temperature limit temperature is 300°C or 450°C, if the temperature range is 400°C, a reduction effect of 2×10 ⁷ cm ^-2 is obtained as described above. In addition, as in another example of Example 1, the growth temperature is set to 700°C and the lower limit temperature is set.
When T _D = 450℃, the cooling temperature range is 250℃ and the reduction effect is slightly reduced, but the dislocation density is 4×
10 ⁷ cm ^-2 (up to twice the temperature range of 400℃ mentioned above)
can be reduced to However, as shown in the fourth row of Table 1, the time required for the growth process can be further reduced;
It is useful to reduce the temperature range within the above range from the viewpoint of shortening the time.

[Table] As shown above, according to the present invention, the dislocation density of the GaAs layer on a silicon (Si) substrate can be reduced by using the conventional growth interruption and thermal cycle process (Figure 3), which takes a long time. Dislocation density can be reduced efficiently in a short time using the process shown in Figures 1 and 2, in which the cooling temperature range of the thermal cycle is set to 250°C or higher, and the lower limit temperature of the thermal cycle is set to 300°C or higher. It becomes possible to measure. By reducing the dislocation density of a compound semiconductor formed on a silicon (Si) substrate by the method of the present invention,
It can be used as a semiconductor substrate for various electronic devices and optical devices, especially for the above compound semiconductors.
Excellent effects are shown by forming a PN junction to construct a solar cell. <Effects of the Invention> As described above, according to the present invention, silicon (Si)
Compared to conventional methods, it is now possible to form a high-quality compound semiconductor single crystal layer on a substrate more efficiently, and as a result, it can greatly contribute to lowering the cost and weight of compound semiconductor devices. .

[Brief explanation of the drawing]

Figures 1 and 2 are diagrams showing an example of a temperature program for reducing dislocation density using the compound semiconductor layer forming method of the present invention, respectively, and Figure 3 is a diagram showing a conventional method for reducing dislocation density by interrupting growth and thermal cycling. Figure 4 is a schematic diagram of the substrate structure to explain the method of forming a compound semiconductor layer on a silicon substrate, and Figures 5A to C are diagrams showing conventional growth interruption and thermal cycling to reduce dislocation density. FIG. 2 is a schematic diagram for explaining. 1...Silicon substrate, 2...GaAs layer, 3...preliminary deposit layer.

Claims (1)

[Claims] 1. When growing a GaAs compound semiconductor layer on a silicon substrate, by repeating the growth of the compound semiconductor layer, the interruption of the growth, and the temperature drop during the interruption,
In the method for forming a compound semiconductor layer in which a compound semiconductor layer is sequentially grown in layers for each thermal cycle to form a compound semiconductor layer on the silicon substrate by the thermal cycle, the cooling temperature range of the thermal cycle is 250° C. or more, A method for forming a compound semiconductor layer, characterized in that the lower limit temperature of temperature drop in a thermal cycle is set to 300°C or higher. 2. The method of forming a compound semiconductor layer according to claim 1, wherein the temperature is temporarily raised before the growth of the thermal cycle is interrupted.