JPH0623955B2 - Processing selection method - Google Patents

Description

The present invention relates to a process selection method of a data processing device, and when some kind of interrupt process can be realized by a combination of several common process subroutines, The present invention relates to a processing selection method of displaying selection information for combining common processing subroutines as a series of bit information of a register, detecting the bit information in time series, and performing subroutine processing.

The data processing device controlled by the program is
The control process is divided into a plurality of processing systems. For example, the processing procedure is determined for each interrupt cause, and the processing procedure, that is, the processing system, differs depending on the processing content. Each processing system is composed of a plurality of subroutines.

For example, in the case of data reception processing in the communication control device, it becomes necessary to perform processing for each character received. For example, each time one byte of data is received, the character code is classified and C
Whether to perform RC operation or parity check, whether to activate a timer that monitors the message length or synchronization character, and whether to send the received character to the main unit (central processing unit) connected to the communication control device It is necessary to judge whether or not to process.

These processes are usually made into subroutines and commonly used in each character code process.

Therefore, when the data processing device executes a process, how to select the sub-routine is an important issue in order to improve the processing speed.

[Conventional technology]

Conventionally, when a data processing device executes a process by using a subroutine, for example, when an interrupt occurs while executing another process, the process for this interrupt is performed by calling a plurality of subroutines. Since the processing differs depending on the interrupt cause and the program status, there is a method of creating a plurality of subroutine call instructions for each interrupt cause and the program status.

However, in this method, when it is necessary to add the status of a new program, it is necessary to add an instruction to call multiple subroutines, and when a large addition is made, the correction amount of the program increases, The problem arises that it is not easy to fix.

In order to deal with this, a register or memory for storing bit information corresponding to each subroutine is provided, and bit information of each processing system is stored in the register or memory.
When processing the corresponding processing subroutine, a method of sequentially referring to this register or memory by a program in a time series and executing it is adopted.

That is, this is a method of judging bits by a program and judging which subroutine is to be processed.

However, this method has a problem that the number of processing steps of the processing device increases and the processing efficiency is poor because the register is referred to each time in time series.

[Problems to be solved by the invention]

The present invention has an object of providing a processing selection method capable of efficiently performing processing of a subroutine from the conventional situation as described above, and the program can be easily modified.

[Means for solving problems]

Such a problem is that in an information processing system having a memory for storing a program and control information and a processor for executing the program, the interrupt processing is configured by a time-series combination processing of a plurality of subroutines, and is common to the plurality of interrupt processing. A plurality of the subroutines used in the memory are stored in the memory, the storage addresses of the respective subroutines in the memory are stored with addresses in the time series order, and the interrupt is provided at the final address of the address. A table in which a processing end processing instruction is stored, and a shift register for displaying a combination of the plurality of subroutines used for one interrupt processing, each bit position of the shift register corresponding to an address of the table, According to the bit information of the bit position, the subroutine used is A shift register for displaying, a counter that counts up in synchronization with digit shift of the shift register, and a pointer register for setting a predetermined address of the table are provided, and when performing the interrupt processing, the shift register is sequentially digitized. The bit information is detected by shifting, the number of shifted digits is counted by the counter, and the address of the table is indicated by the operation value of the counter value and the pointer register value. In addition to obtaining the accommodation address on the memory of the subroutine corresponding to, the execution processing instruction of the interrupt processing stored in the final address is executed when the operation value indicates the final address of the table. Solved by a process selection method characterized by obtaining a return address It is.

[Action]

According to the present invention, a table is provided in which each address of the memory storing the common subroutine is stored in the order of processing time series, and the required combination of subroutines is displayed by the information of the bit position of the shift register corresponding to the address of this table. The bit information is identified by sequentially shifting digits.

As a result, in the case of the data reception processing in the above-mentioned communication control device, a plurality of subroutine calls by the program for each byte of the received data are no longer necessary, and the bit of the register or the memory is different from other conventional examples. It is possible to achieve a processing selection method having higher processing efficiency than the method of referring to information by a program.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an essential part of an embodiment of the present invention, and FIG. 2 is a schematic diagram for explaining a time series output means of subroutine selection bit information. The shift register 1 of FIG. 2 is composed of 16 bits, and there are processing subroutines "1" to "16" corresponding to each bit, that is, the upper bit information # 15 to the lower bit # 0. For each bit of the shift register 1, the bit corresponding to the selected processing subroutine is set to logic "1".

As shown in FIG. 1, the shift register 1 stores selected bit information. A carry bit 2 is provided in the shift register 1. The shift register 1 stores a bit corresponding to the selected processing subroutine as a logical value "1". The shift register 1 performs a left shift operation. This shift register 2 is provided with a carry bit 2, and when "1" is stored in the carry bit 2, the left shift operation of the shift register 1 is stopped.

The counter 3 advances in synchronization with the left shift operation of the shift register 1. This step is performed only for the upper 4 bits of the counter 3. The counter 3 is also provided with a carry bit 4, and when the carry bit also becomes "1", the counter operation is stopped.

The jump instruction and the return instruction to which the present invention is applied are JSX instruction and RTX instruction, respectively. As shown in the table, the table 5 stores addresses on the memory (not shown) of the processing subroutines "1" to "16". Here, it is assumed that the address of each processing subroutine is 2 bytes. If the JSX instruction is executed at the address 1000 (hexadecimal), the address 1002 (hexadecimal) of the processing subroutine '1' next to the JSX instruction is stored in the pointer register 6.

When the JSX instruction is generated, the upper 4 bits of counter 3
All are set to "1". That is, the initial value of the counter 3 is
It is "1,11110". After that, the shift register 1 starts the shift operation. When the shift is performed twice, the carry bit 2 of the first 2 bits of the shift register 1 is set to "1", the counter 3 becomes "0,00010", and "0,00010" is added. It becomes one input of the container 7. The other input of the adder 7 is the value of the pointer register 6, that is, 1002
(Hexadecimal) is entered.

The adder 7 adds "0,00010", that is, 2 and 1002 (hexadecimal), stores the result 1004 (hexadecimal) in the register 8,
The address of the start address of the processing subroutine "2" at address 1004 (hexadecimal) in Table 5 is put into the program counter 9 and the processing of the processing subroutine "2" is performed.

This is address 10 of table 5 stored in register 8.
The address 04 (hexadecimal) is given to the memory load processing unit 11 via the multiplexer circuit 10, and the memory load processing unit 11 stores the memory of the processing subroutine 2 stored at the address 1004 (hexadecimal) of the table 5 (see FIG. The top address above (not shown) is obtained and placed in the program counter 9.

As a result, the start address of the subroutine 2 on the memory (not shown) is designated and the processing is executed.

When the processing of the processing subroutine 2 is completed, the shift register 1 is shifted to the left again by the RTX instruction, the shift register 1 is shifted three times, and the counter 3 changes from "0,00010" to "0,01000". The adder 7 is "0,01000", that is, 8
Adds 1002 (hexadecimal) and outputs 100A (hexadecimal).

The start address of the processing subroutine 5 of 100 A (hexadecimal) is output to the program counter 9, and the processing subroutine 5 is executed. Similarly, the processing subroutine '11' and the processing subroutine '15' are executed.

Shift register 1 with RTX instruction of processing subroutine '15'
2 bit shift causes carry bit 4 to "1"
However, since the counter 3 is output as "1,00000", the value 20 (hexadecimal) including the carry bit is added to the value 1002 (hexadecimal) of the register 6 by the adder 7 and the result is obtained. of
Address 1022 (hexadecimal) is stored in register 8, but in this case, all the subroutines have been completed, so register 8
Address 1022 (hexadecimal) from the multiplexer circuit
It is switched by 10 and directly put into the program counter 9 without going through the memory load processing unit 11.

As a result, the address on the memory (not shown) designated by the program counter 9 is the address 1022 of the table 5.
It becomes the address itself, and the end processing instruction stored in this address is executed to obtain the interrupt processing end and the return address after that.

The multiplexer circuit 10 selects whether to directly input from the register 8 to the program counter 9 or to store the start address of the subroutine stored in the address of the table 5 by the memory load processing unit 11 from the contents of the register 8 into the program counter 9. Do. That is, when the carry bit 4 is "1", the data is directly stored, and when the carry bit 4 is "0", the multiplexer circuit 10 switches so that the memory load processing unit 11 operates. Needless to say, the memory is loaded by the memory load processing unit 11.

It should be noted that a termination processing program is stored in the above address 1022 and thereafter.

In addition, in this embodiment, the pointer register 6 has a table 5
It is conceivable that the start address of the is stored fixedly during execution of a series of processing subroutines, but when jumping to one subroutine, the start of the next subroutine is updated to the stored address and processing is performed. In that case, the counter 3 is initialized every RTX. According to this method, the counter 3 contains the displacements of the currently executing subroutine and the subroutine to be executed next.

Further, although the storage order of the table 5 is the time series order of the processing,
If the processing order needs to be partially reversed, the reversed subroutine selection may be executed again according to the present invention.

〔The invention's effect〕

As will be understood from the above description, in short, the present invention is
The processing can be selected by the bit information and the table, which is efficient without increasing the number of steps in the program. When the processing system is changed, the program can be modified by changing the bit information in time series, and the load of the program can be changed. It is very effective in reducing the amount.

[Brief description of drawings]

FIG. 1 is a block diagram showing an essential part of an embodiment of the present invention, and FIG. 2 is a schematic diagram for explaining a time series output means of bit information. In the figure, 1 is a shift register, 3 is a counter, 6 is a pointer register, 7 is an adder, and 9 is a program counter.

Front page continuation (72) Shinji Shibara, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor, Koichi 1015 Kamedanaka, Nakahara-ku, Kawasaki, Kanagawa References JP-A-50-93357 (JP, A) JP-A-58-97737 (JP, A) JIII Journal of Technical Disclosure 83-7158

Claims (1)

[Claims] 1. An information processing system having a memory for storing a program and control information and a processor for executing the program, wherein interrupt processing is constituted by time-series combination processing of a plurality of subroutines, and is common to the plurality of interrupt processing. A plurality of the subroutines used in the memory are stored in the memory, the storage addresses of the respective subroutines in the memory are stored with addresses in the time series order, and the interrupt is provided at the final address of the address. A table in which a processing end processing instruction is stored, and a shift register for displaying a combination of the plurality of subroutines used for one interrupt processing, each bit position of the shift register corresponding to an address of the table, Display the used subroutine according to the bit information of the bit position Shift register, a counter that counts up in synchronization with the digit shift of the shift register, and a pointer register that sets a predetermined address of the table. When performing the interrupt processing, the shift register is sequentially shifted by a digit. The bit information is detected by doing so, and the number of shifted digits is counted by the counter, and the address of the table is indicated by the operation value of the counter value and the pointer register value. The accommodating address on the memory of the corresponding subroutine is obtained, and when the calculated value indicates the final address of the table, the end processing instruction of the interrupt processing stored in the final address is executed and the return is performed. A process selection method characterized by obtaining an address.