JPH0623976B2 - Vector register controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector processor, and more particularly to a vector register allocation mechanism.

[Background of the Invention]

Generally, in a vector processor, the number of data transfers to and from the main memory is reduced by storing vector data of an operation target and an operation result in a vector register. However, when the calculation becomes complicated, the number of vector registers required increases, and often exceeds the number of physically installed vector registers. The vector compiler attempts to optimally allocate vector data to vector registers based on the static analysis of statements, but cannot grasp even the dynamic conditions that change as the operation progresses. You cannot expect an efficient allocation for the.

For example, assume the following sequence of instructions.

1) VR1 ← A (*) 2) VR2 ← B (*) 3) VR4 ← VR3 * VR1 4) VR6 ← VR5 + VR2 5) VR? ← C (*) The first instruction is an instruction to load the vector A (*) into the vector register (hereinafter abbreviated as VR) 1, and the second instruction is an instruction to load the vector B (*) into VR2. Third
The instruction is an instruction for multiplying the contents of VR3 and the contents of VR1 and storing the result in VR4, and the fourth instruction is an instruction for adding the contents of VR5 and the contents of VR2 and storing the result in VR6. Here, there are only 6 VRs, and
If VR3 to VR6 are planned to be used in the subsequent instructions, the destination (V
R? ), There are two candidates, VR1 and VR2, but which one is released first and can be reused is executed when a plurality of arithmetic units perform parallel processing like a recent vector processor. It cannot be judged unless it is time. If VR1 is randomly assigned to this, even if VR2 is actually released first, the execution of the fifth instruction will be VR1.
It will be a waste of time because you will have to wait until the release of.

[Object of the Invention]

An object of the present invention is to prevent VR from being wasted as described above by automatically allocating VRs according to a dynamic situation, and it is necessary for a program to consider the number of VRs and their allocation. Is to exclude.

[Outline of Invention]

According to the present invention, the vector register is not considered to be a problem on the program instruction, and the vector register is allocated by hardware. Therefore, the allocation status of each vector register is registered in the vector register directory. This is searched to check whether or not there is a vector register assigned to the vector data specified by the instruction. If it exists, the vector register number is used to access the vector register group. The replacement circuit configures the vector register control device so as to newly allocate the vector register and register the result in the vector register directory.

As an embodiment, an instruction specifies a vector instruction register (DR in the embodiment) holding vector data instruction information to indirectly specify vector data, and also in the vector register directory, each vector register The assigned vector data can be indirectly specified by specifying the vector instruction register.

Example of Invention

In the embodiment described below, one vector calculator and 16
For a vector processor with 3 VRs. FIG. 2 shows the format of instructions in this embodiment. The first byte of the instruction 10 is an OP code that specifies the type of operation. The second to fourth bytes specify the numbers R _{1 to} R ₃ of the vector instruction register (Description Register, hereinafter abbreviated as DR) for the _{first to third} operands, and these DRs are the respective operands. Holds information indicating the position of the main storage device.
The first operand position is the storage destination of the operation result, and the second and third operand positions are the acquisition destination of the data to be operated.

It is assumed that 256 DRs are provided. As shown in FIG. 3, the content of DR11 consists of four parts. “Data type” indicates the length of the element of the vector and the type of data (integer, floating point display, etc.). The "start address" indicates the address of the first element of the vector in the main memory. The “increment value” indicates an address increment value of the main memory device between elements of the vector. The “vector length” indicates the number of elements forming the vector. The contents of each DR11 are set by the appropriate instruction group prior to the start of calculation.

FIG. 1 shows the overall construction of the vector processor. From the instruction register 21 in the vector instruction control unit 20, the DR number designating the first to third operands is
It is sent to the DR-VR conversion circuit 30 via the data lines 22 to 24. The DR-VR conversion circuit 30 searches for the VR numbers corresponding to these DR numbers, and outputs the VR number for the first operand via the data line 55 to the first operand VR.
Similarly, the VR numbers for the second operand and the third operand are given to the write control circuit 50 and, via the data lines 56 and 57, the second operand VR read control circuit 51 and the third operand VR read control circuit 52. Give to.

The second and third operands are synchronously read from the designated VR in the VR group 43 element by element under the control of the corresponding VR read control circuits 51 and 52, and are operated via the data lines 58 and 59. Input to the container 44. The operation result is returned to the VR group 43 via the data line 60, and under the control of the first operand VR write control circuit 50, a predetermined V
Written to R.

For example, the operation when the second operand does not exist in the VR group 43 is as follows. First, the DR-VR conversion circuit 30 supplies the content of DR indicating the second operand to the address generation circuit 41 via the data line 31. The address generation circuit 41 sequentially generates the address of each element of the vector based on the content of the received DR and requests the main memory device 42 to read the data. The main memory device 42 passes the read data line 61. Transfer to the VR group 43. Meanwhile, the DR-VR conversion circuit 30 newly allocates one VVR to the read second operand,
The VR number is applied to the VR read / write control circuit 53 via the data line 54 to write the vector data of the second operand read from the main storage device 42 into the VR.
At the same time, this VR number is also given to the second operand VR read control circuit 51, and the written second operand is supplied to the arithmetic unit 44 as it is.

Even when the third operand does not exist in the VR group 43, similarly, the vector data read from the main storage device 42 is supplied to the arithmetic unit 44 via the VR group 43.

If the VR assigned to the first operand does not exist, the DR-VR conversion circuit 30 assigns the VR to it and assigns the VR number to the first operand VR write control circuit 50 via the data line 55. It is supplied and the calculation result is written in the VR. However, when the allocatable VR decreases, not only the VR but also the main memory 42
Also, the writing of the first operand is performed. At this time,
The DR-VR conversion circuit 30 outputs the content of DR indicating the first operand via the data line 31 to the address generation circuit 41.
The address generation circuit 41 sequentially generates the addresses of the elements of the vector of the first operand and requests the main storage device 42 to write. At the same time, the DR-VR conversion circuit 30 also supplies the VR number given to the first operand VR write control circuit 50 to the VR read / write control circuit 53 via the data line 54 to write it in VR. The operation result is read as it is, and the main memory 42 is passed through the data line 62.
Transfer to.

The vector instruction unit 20, the address generation circuit 41, the main memory 42, the VR group 43, the arithmetic unit 44, and the control circuits 50 to 53 for reading / writing the VR may be conventional ones. Japanese Patent Laid-Open No. 58-114274 shows an example thereof.

The structure of the DR-VR conversion circuit 30 is shown in FIG. The DR group 70 is a register group including 256 DR11, and outputs 22 to 24 of the second to fourth bytes of the instruction word register 21, that is, DR of the first to third operands.
The content of DR11 designated by the number is the data line 91
To 93, respectively. The VR directory (hereinafter abbreviated as VRD) 73 has a one-to-one correspondence with each VR 16
It is composed of VRD registers 94. Each VRD register 9
4, as shown in FIG. 5, in addition to the contents (data type, data address, increment value, vector length) of DR11 that specifies the vector data stored in the corresponding VR,
The DR number, the validity flag, and the reusable flag are held. Of these, the validity flag is "0" when the corresponding VR is unused, and is "1" when some valid data is stored. The reusable flag is "1" if the corresponding VR can be reused (assigned).
Then, if it is not possible, it becomes “0”.

FIG. 4 shows that the comparison circuits 77 to 79 determine whether or not there is a VR assigned to the vector data designated by the instruction via DR (in the case of the second and third operands, the VR holding the vector data is held). Is present or not). These comparator circuits each include 16 comparators, and simultaneously receive the DR number and the validity flag in the 16 VRD registers 94 from the VRD 73 via the data line 74, and these 16 numbers are The instruction is compared in parallel with the DR numbers (data lines 22 to 24) designated for the first to third operands, and if there is a match, the corresponding VR is based on the position of the comparator in which the match occurred. Generate a number. Then, further on the condition that the validity flag in the VRD register is "1", the VR number and a signal indicating the coincidence establishment are sent to the data lines 95-9.
Send to 7. This coincidence establishment signal is output to the selection circuits 81 to 8
3 to control the corresponding VR number via the data lines 55 to 57 and the operand VR write / read control circuit 50 to 50 in FIG.
52 to the appropriate one. In addition, when the presence of the VR assigned to the first operand is detected, the reusable flag in the VRD register 94 corresponding to the VR is set to "0" by the data line 95, and the data is written therein. The VR is prevented from being reused before the operation result is read. Further, when it is detected that the second and third operands exist on the VR, the reusable flag in the VRD register 94 corresponding to the VR is set to "1" by the data lines 96 and 97, and the VR is set. Indicates that it can be assigned to other vector data.

The replacement circuit (hereinafter abbreviated as RPL) 76 determines the VR to be assigned to any of the first to third operands when the assignment of VR has not been performed. For this purpose, the RPL 76 examines the validity flag and reusable flag in each VRD register 94 via the data line 75, first looking for the VRD register whose validity flag is "0", If there is one, select that one. If there is no validity flag "0", one is selected from the reusable flags "1".

For example, the new assignment of VR to the second operand is
This is done as follows. The data line 9 from the comparison circuit 78 indicates that the DR number that matches the DR number specified by the instruction for the second operand cannot be found in the VRD 73.
6, the RPL 76 outputs the VR number corresponding to the VRD register selected by the above-mentioned procedure via the data line 54 to the VR read / write control circuit 53 of FIG.
And to the second operand VR read control circuit 51 from the selection circuit 82 via the data line 56,
Prepare to accept the vector data read from the main memory 42. At the same time, the RPL 76 controls the selection circuit 84 to change the DR designated by the instruction for the second operand.
The contents of FIG. 11 (FIG. 3) are supplied from the data line 92 through the same 31 to the address generation circuit 41 of FIG. 1 to read the main memory device 42. The RPL 76 further adds the DR to the VRD register 94 selected as described above.
(Data line 31) and its DR number are written, and its validity flag and reusable flag are set to "1".

The new assignment of VR to the third operand is similar to the above, but the determined VR number is the data line 56.
Instead, it is output to the same 57 and supplied to the third operand VR read control circuit 52.

When a VR is newly assigned to the first operand, the assigned VR number is supplied from the selection circuit 81 to the first operand VR write control circuit 50 via the data line 55. At the same time, the VR corresponding to this VR
DR11 indicating the first operand to the D register 94
Is written via the data line 91 through 31.
At the same time, the validity flag in that VRD register 94 is set to "1".

When the VR whose original value of the validity flag is “0” is assigned to the first operand, the RPL 76 sets the reusable flag of the corresponding VRD register 94 to “0” and sets the V
Prevent R from being assigned to other vector data.
In this case, the address generation circuit 41 and VR shown in FIG.
The read / write control circuit 53 is not activated. This is because it can be considered that there are enough VRs that can be allocated. However, since there is no VR with the validity flag remaining "0", when the VR with the validity flag "1" but the reusable flag "1" is assigned to the first operand, the corresponding The reusable flag of the VRD register is left at "1", the VR number is sent to the VR read / write control circuit 53 via the data line 54, and the operation result written in the VR is immediately read. At the same time as instructing to output, the content of the corresponding DR is sent to the address generation circuit 41 via the data line 31, and the operation result (data line 62) read from the VR is written to the main storage device 42. This measure eliminates monopolization of the VR by the first operand and enables allocation to other vector data as a countermeasure against the decrease in the number of VRs that can be allocated, and prepares for such reallocation. , For storing the calculation result also in the main storage device.

In this embodiment, although there are actually only 16 VRs, the program is as if 256.
It can be regarded as if there are VRs (the number of DRs).

In the present invention, the number of arithmetic units is not limited to one, and a plurality of arithmetic units may be provided. Rather, the advantage of the present invention is utilized when a plurality of arithmetic units operate in parallel. Further, in the above-mentioned embodiment, the VR can be reused immediately after being read once, but the reuse may be prohibited until the reading of an arbitrarily specified number of times is completed. For that purpose, for example, a read number designation field is provided in the DR 11, and a read number field is provided in the VRD register 94 instead of the reusable flag. And VR
The read count field of the D register is DR at the beginning of the allocation.
The value of the read number designating field is transcribed, and thereafter, each time reading from the corresponding VR is performed, it is decremented by one, and the value of "0" is changed to the reusable flag in the above embodiment. Is treated as being equivalent to the state of "1".

Further, in the above-mentioned embodiment, the content of DR is premised on being fixed during the execution of the program.
If the contents of R can be updated, vector data more than the number of DRs can be processed. For that purpose, the VRD 73 is searched based on its contents, not on the DR number. For example, in FIG. 4, the comparator circuits 77-79 receive, as one input, the data lines 91-93 which are the contents of the DR indicated by them, instead of the data lines 22-24, and the other input. 7
Even if it is 4, the contents of the fields corresponding to them in the VRD register 94 may be received.

Further, in the above embodiment, the designation of the vector data data in the instruction is performed indirectly via the DR,
Although the group is, so to speak, a form of forming a virtual VR, even if the DR group 70 is abolished and an instruction directly gives vector instruction information such as a start address of vector data, an increment value, and a vector length. Good. In this case, the comparison circuits 77 to 79 in FIG. 4 directly compare the vector instruction information in the instruction with the vector instruction information in the VRD register, and the data lines 91 to 93 are connected to the instruction register 21.
Will be output.

〔The invention's effect〕

According to the present invention, the program creator does not need to consider the number and allocation of VRs as a physical structure, and for example, the program does not have to be changed even if the number of VRs is different. In addition, there is no waste of time, such as waiting for another VR to become available despite the existence of the reusable VR.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a command format diagram, FIG. 3 is a schematic diagram of the contents of DR, and FIG. 4 is a block diagram of the DR-VR conversion circuit in FIG. , FIG. 5 is a schematic diagram of the contents of the VRD register in FIG. 21 ... Instruction register, 30 ... DR-VR conversion circuit, 42
... Main storage device, 43 ... Vector register (VR) group, 5
0-53 ... Write / read control circuit for VR group, 70 ...
Register holding vector data instruction information (DR)
Group, 73 ... Vector register directory, 76 ... Replacement circuit.

Claims (2)

[Claims] 1. A vector processor having a plurality of vector registers, wherein vector data on these vector registers is used as an operand, a vector register directory holding information indicating an allocation status of each vector register to vector data, In response to the decoded vector data designation information in the instruction, the vector register directory is searched to check whether or not there is a vector register assigned to the vector data designated by the instruction. A circuit for outputting information indicating a vector register to a vector register access control circuit, and a replacement circuit for allocating the vector register when it does not exist and registering the result in the vector register directory are provided. Vector Static control device. 2. The vector data designating information in the instruction according to claim 1, includes identification information of a vector designating register in which vector data designating information for specifying vector data is stored, and in the vector register directory. The information indicating the allocation status includes the identification information of the vector instruction register in which the vector data instruction information of the vector data to which each vector register is assigned is stored, and the circuit for outputting the information instructing the vector register is A vector register control device comprising a circuit for comparing the vector instruction register identification information with the vector instruction register identification information in the vector register directory.