JPH0624328B2 - System frequency synchronous transmission system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission system, and more particularly to a signal transmission system suitable for transmitting information using a distribution line of a power system.

[Background of the Invention]

FIG. 1 shows an outline of signal transmission using a distribution line. The MSR in the figure is a master station that is installed in, for example, a substation, and transmits information signals to many slave stations SSR. The slave station SSR has, for example, 6
It will be installed on the pole of 6KV transmission line. A high voltage distribution line is used as a transmission line DH between the MSR and the SSR, and each slave station SSR is coupled to a terminal device (not shown) of each home h via a low voltage distribution line DL. . The terminal device has a meter reading function for gas, water, electricity, etc. in each home, an opening / closing control function for a water heater, etc. that uses night power, and a function for returning these meter readings and control results. According to the system using this distribution line, the centralized device can perform batch meter reading and batch control without installing a new transmission line.

As an example of the specific transmission method in this case, Japanese Patent Application No. 55-
A zero-phase transmission scheme such as that proposed in 102497 can be used. As schematically shown in FIG. 2, one end changes the zero-phase voltage of the three-layer (UVW phase) system, and the other end catches this voltage fluctuation to perform signal transmission. This detailed description will be given later.

Since the data handled in the transmission system using a distribution line is used for the charge settlement, it is particularly required to send and receive the information correctly. For this reason, in general, a signal structure including a sync signal and an information signal is used, and when the sync signal is detected, an M bit after that is obtained as an information signal by an asynchronous transmission method, or only a clock signal is extracted from a received signal, and this clock signal is extracted. A synchronous transmission method is adopted in which only the information signal is taken out in synchronization. However, in the former case, there is a problem in that when the sync signal changes due to noise or momentary interruption, the subsequent information signal cannot be captured. Noise can be reduced by adopting an asynchronous transmission method that adopts a known method of detecting data error and reproducing original data by devising signal coding.
It can be made less susceptible to momentary interruptions. However, in these cases, the circuit becomes complicated and unavoidably increased in size. Considering the installation environment and area (slave station SSR is installed side by side on the pole transformer, and the terminal is installed outdoors in each home), the circuit is simple and compact.
It needs to be reliable.

[Object of the Invention]

In view of the above, it is an object of the present invention to provide a signal transmission system using a highly reliable transmission and distribution line with a simple circuit while adopting a synchronous transmission system that is resistant to noise and instantaneous interruption.

[Outline of Invention]

In the present invention, since the distribution line is used as the signal transmission line, this distribution line voltage can be used as a synchronization signal source for transmission between the master station, the slave station, or the terminal.

Example of Invention

FIG. 2 shows an embodiment of the present invention. In the figure, UVW represents each phase of the three-phase transmission / distribution line. In the master station MSR, one phase of the UVW phase (U phase in this case) is grounded via the resistor R and the switch SW, and the switch SW is opened and closed by the modulator MS. Switching of the switch SW in the modulator MS is performed as shown in FIG. 4 with the U-phase voltage V _U as a reference phase. The signal STCLK is the SW open / close signal.

The demodulator DEM in the slave station SSR inputs a voltage between arbitrary phases or lines (here, the voltage V _{U of the} U phase from which the signal is extracted by the master station MSR) and the zero phase voltage V ₀ . still,
C _U1 and C _U2 are couplers for taking in the U-phase voltage,
C _0U , C _0V and C _0W are couplers for taking in the zero phase voltage. Here, V ₀ is a switch SR in the master station MSR
Is an information signal corresponding to the open / closed state, and V _U means a synchronization signal.

FIG. 3 shows a specific configuration of the demodulator DEM. The full-wave rectification circuit 93 full-wave rectifies a zero-phase voltage as shown in V ₀ of FIG. 4 to obtain a rectified value RECA. The rectangular circuit 94 rectangularizes RECA with an appropriate value TH to obtain a rectangular signal RECS.

On the other hand, the U-phase voltage V _U is rectangular, which is the clock signal C.
It is called LKS. CLKS is input to a known clock control circuit 60, an example of which is shown in FIG. 5, and this output SCLK is used as a synchronizing signal. Reference numeral 60 is composed of a phase oscillation circuit PLL, a counter COU and a decoder DEC, and the PLL is a clock signal CLKS and a counter CO.
A pulse signal having a frequency corresponding to the phase difference from the U output is given. When both are in the same phase, the output frequency _{L of the} PLL
Is M times the frequency of the clock signal CLKS,
The counter COU provides the output divided by 1 / M as the input of the PLL. The decoder DEC is a (M-N) bit counter that obtains a pulse output at the 1 / N frequency-divided position of the counter COU, and outputs the synchronizing signal SCLK when the value formed by the (M-N) bit is a predetermined value. . Therefore, the synchronization signal SCLK can be a signal having the same frequency as the clock signal CLKS and a predetermined phase difference. In the example of FIG. 4, SCLK is 1 (of system electricity quantity) rather than CLKS.
/ 2 cycles is recommended. Reference numeral 95 is a sampling means, which samples the output of the rectangular circuit 94 when the synchronizing signal SCLK is applied, and outputs RECDATA.
To get RECDATA is equivalent to the opening / closing signal STCLK of the switch SW, and thus the original signal can be reproduced from the received signal.

〔The invention's effect〕

As described above, according to the present invention, the synchronous transmission can be realized by a simple device by using the frequency of the system electricity quantity as the clock signal in the signal transmission using the power transmission and distribution line.

[Brief description of drawings]

FIG. 1 is a diagram showing a signal transmission system using a transmission and distribution line, FIGS. 2 and 3 are diagrams of one embodiment of the present invention, FIG. 4 is a signal waveform diagram of each part thereof, and FIG. 5 is a clock. It is a figure which shows a control circuit. DEM ... Demodulator, 93 ... Full-wave rectification circuit, 94 ... Rectangular circuit, 95 ... Sampling means, 60 ... Clock control circuit.

Claims (1)

[Claims] 1. In a system frequency synchronous transmission system comprising a master station connected to a three-phase distribution line and a plurality of slave stations, and performing signal transmission between them, the master station is one line of the three-phase distribution line and the ground. A series circuit consisting of an impedance and a switch is connected between them, and the switch is opened and closed by using one cycle of the voltage of any one line of the three-phase distribution line as a reference unit for signal transmission. A rectifier circuit that inputs a phase voltage and the voltage of the arbitrary one line and rectifies a zero-phase voltage; a rectangular circuit that compares the magnitude of the output of the rectifier circuit with a predetermined level to obtain a rectangular signal; A system frequency synchronous transmission system comprising a clock control circuit for providing an output in each cycle in synchronization with the zero point of the voltage of the first line, and sampling means for reading the output of the rectangular circuit at the output timing of the clock control circuit. .