JPH0624358B2 - Data writing device - Google Patents

Description

TECHNICAL FIELD The present invention relates to an apparatus for writing a personal identification number (ID) to an IC card or the like, or a receiving terminal of a pay broadcasting system using a broadcasting satellite, etc. The present invention relates to a device for writing a master key.

Conventional technology and its problems Widely used in information processing systems in various industrial fields.
IC card is used. IC cards generally make a semiconductor IC containing logic circuits have some functions such as instruction understanding, logical selection, and temporary or permanent storage of data, so that this IC is convenient for carrying and handling. Many of them are packaged in plastic cards. The stored contents of the IC card may be read out or used for internal information processing or judgment. Also, IC
Some of the storage circuits built in the card can change the written data and some cannot. For example, in order to make the data written in the memory area of the memory circuit unmodifiable, the write circuit may be destroyed, or the data itself may be selectively destroyed. In an information processing system using such an IC card, writing of data such as an ID, that is, a personal identification number or an individual master key, to the IC card is generally centralized at a central management center provided in one place of the using system. It is customary to do this,
On the contrary, it has not been possible to write a large amount of data in a distributed and simultaneous manner at each of a plurality of distributed stations that respectively manage a plurality of areas in the system. The main reasons are as follows.

(B) When data is distributed and written at several locations, it is relatively difficult to manage the data to be written, and further consideration must be given especially to guarantee the confidentiality of the data.

(B) Further, when data is distributed and written, the same data as the data representing the ID of one user is stored in another nonvolatile memory (N
-M) or volatile memory (VM).

(C) If the outline of the writing device is publicly disclosed, it is generally impossible to keep the secret. Therefore, there has been no structure having a structure that can keep the secret even if it is disclosed as in the present invention.

By the way, as part of the sophistication and diversification of communication media accompanying the development of advanced information technology in society in recent years, full-scale satellite broadcasting is about to enter the implementation stage in Japan. One of the things aimed at diversifying the public's information needs and enhancing broadcasting services is the pay system for television broadcasting by broadcasting satellites. Therefore, it is necessary to develop effective solutions to predicted technical problems. In the paid broadcasting satellite television system, in order to maintain confidentiality and guarantee the swiftness / accuracy of distribution of related information,
Since it is expected that each terminal will be equipped with a memory in which data such as the subscriber's personal identification number and master key is written, how efficiently, reliably and economically the data can be written in this memory. Whether to do it is one of the important issues. Because of the peculiarity of the broadcasting satellite television pay system, whether it is the above-mentioned intensive or decentralized,
This is because the conventional writing method cannot be applied as it is.

SUMMARY OF THE INVENTION Problems to be Solved by the Invention and Characteristics of Solving Means Thus, the object of the present invention is directed to solving the above-mentioned problems associated with the conventional method of writing data such as an ID to a memory such as an IC card. The present invention is to provide a novel and highly useful data writing device that can be effectively applied to a pay system of broadcasting satellite television.

In order to achieve the above-mentioned object, the writing device of the present invention comprises:
All the data to be written such as personal identification number and master key are centrally managed by one central management center, while the required data is written from each central management center to each writing device in each distributed receiving terminal. It is characterized in that it is delivered and configured so that each writing device can be physically locked, and that all personal master keys used for encryption algorithms are stored in a central management center. By automatically writing data to the volatile memory or the non-volatile memory and writing the written flag in association with each data, the same data is prevented from being written twice.

The specific configuration and operation of the present invention will be clarified by the following description with reference to the drawings.

Embodiment FIG. 1 is a block diagram showing the overall construction of an embodiment of a data writing apparatus according to the present invention, and the operation of this embodiment apparatus is outlined in the flowchart of FIG.

First, in FIG. 1, 1K is a physical key, and 1B is a box or a housing that can be locked by the key, and a relatively large capacity nonvolatile memory (NM) 2 is contained in the housing 1B. It is stored. On the other hand, 10 is a non-volatile memory (N
-M) or volatile memory (VM). In this embodiment, all the main constituent parts 1 to 13 other than the small-capacity memory 10 are housed in one housing. That is, the perspective view of FIG. 3 shows the external appearance of the apparatus, and in the figure, 24 is an IC socket for mounting the small-capacity memory 10.

Therefore, the operation of the embodiment apparatus shown in FIG. 1 will be clarified with reference to FIGS. 2 and 3. Here, consider a case where the ID number is written in a large number of nonvolatile memories (NM) 10. First, when the memory 10 is attached to the socket 24, and then the write instruction switch 3 is turned on, a control pulse signal is output from the main control circuit 4, and the increment counter 5 which was initially set to 0 counts this control. The signal pulse is counted and the increment becomes +1. The contents of the increment counter 5 are transmitted to the read address counter 6, which is further transmitted to the large-capacity nonvolatile memory 2 in the box 1B as a read address under the control of the control pulse. The content of the increment counter 5 may be used as it is as the read address of the large-capacity memory 2, but in the case of designating the column and row addresses, it is better to convert the output of 5 by the read address counter 6. Assuming that the ID is 32 bits in total, one column of the address corresponding to the output of the increment counter 5, for example, a value of a _{0 to} a ₁₁ , which is 1 in this case.
32 bits for one column (this address is assumed to be b _{0 to} b ₄ ) are transmitted to the large-capacity memory 2 (assuming the storage capacity is 2 ¹² × 32≉128 Kbit). Such an action can be easily obtained by appropriately designing the counter in the main control circuit 4.
An address signal of 32 bits (00000 to 11111) is sequentially transmitted from the main control circuit 4 to the large-capacity memory 2 through the read address counter 6, and 32 bits of data in 32 memory cells are read out to the buffer memory 7. Tell. The writing method to the buffer memory 7 is the same as the writing method to the memory 10. When the generation of the read address is completed, the main control circuit 4 sends a control signal to the write control circuit 8 to put the memory 10 in the write mode, while the main control circuit 4 sends the control signal to the read control circuit 14. Then, the buffer memory 7 is set to the read mode. Memory 7 and memory 10
Has the same storage capacity and the same configuration, but 7 is a volatile memory (VM) and 10 is a non-volatile memory (NM).

Data of the read / write address is transmitted from the main control circuit 4 to the write control circuit 8, the write address of the memory 10 is transmitted from the write control circuit 8 to the memory 10 via the write address counter 9, and the read address of the buffer memory 7 is read. It is given from 8 to 7 through the control circuit 14. In this way, the contents of the buffer memory 7 are read and written to the memory 10. In the addresses of the buffer memory 7 and the memory 10, for example, the rows b _{0 to} b ₄ are read from 00000 to 111 as described above.
It's easy to change up to 11. Temporarily, 7 and 10
Even if is a large-capacity memory, the column addresses a _{0 to} a _n (n is an integer) may be fixed. When the writing of 32-bit data from 7 to 10 is completed, the contents are read from 10. This is controlled by the read control circuit 14 and the write control circuit 8. That is, the write control circuit 8 detects the end of writing and releases the memory 10 from the write mode. As a result, 10 is also in the read mode. In this way, the same address is given to 7 and 10, 32 bits are compared one by one in the comparison circuit 11, and if the output of 7 and the output of 10 are the same, the OK symbol is displayed on the display unit 12. On the contrary, if even one bit is different, the NG symbol is displayed at 12. When the determination by the comparison circuit 11 is OK, the main control circuit 4 gives a control signal to the printer 13 to print out the contents written in the memory 10. In this case, 32
Control of whether or not to print all bits is performed through 4 to 11. It is quite possible to read the contents of 10 by controlling 11 according to the speed of printer 13 and reading the contents of 10. After printing, the main control circuit 4 supplies an increment pulse to the increment counter 5. Therefore, the addresses of the large-capacity memory 2 are a _{0 to} a _{11 where the} next 32 bits exist.

By repeating the above operation, a total of 2 ¹² = 4096 pieces of data are sequentially written into the ₄₀₉₆ storage areas M _{1 to} M ₄₀₉₆ of the memory 10. In the above-mentioned example, the case where the 32-bit ID is written has been described. However, considering a large-scale pay-broadcast receiving terminal or individual identification with an IC card, a larger amount of data (ID) can be written, or one terminal (1
It is necessary to write a different key (code) for each memory, but in the above method, 64 bits (000000-1111)
Changing the address of the 11), is an easy to issue write read one a ₀ ~a ₁₁ addresses per 64 bits of data. In this case, the storage capacity of the large-capacity memory 2 is twice as large as that described above, that is, 256 Kbits. 32 bits is about
Since it is equivalent to 4 billion, it is possible that, for example, all Japanese citizens carry IC cards and each has an individual key (code).

Next, an example of systematic operation of the data writing device of the present invention will be described with reference to FIG. In FIG. 4, 16
Is a central management center, which manages, for example, ID 32 bits and key code 32 bits. That is, if the ID number is known, the code number of the key is also known. Here, 4096 different IDs and key codes are written in the large-capacity memories 2A _i , 2B _i , and 2C _i , respectively, to ensure the safety, so that factory A (17A), factory B (17B), factory C
(17C), write device 15A, 15B, 15C of each factory
Insert it in the box 15 (same as 15 in Fig. 3) and lock the key 1K. This can be done by the operator of the central management center, and each factory will have a large memory 2A _i , 2B unless the writing device is destroyed.
_I cannot know the contents of _i or 2C _i . Therefore, confidentiality is guaranteed. As the large capacity memory 2, a floppy disk or an IC card can be considered.

By the way, one of the data write devices 15 in the system
In this case, since some or all of the contents of the large-capacity memory 2 must be read twice and duplicated writing must be performed, refer to FIGS. 5 and 6 for measures to prevent this. Explain. In the explanation so far,
Although the data (ID) is 32 bits and the key code is 32 bits, the data is 31 bits here in consideration of simplification of description. In this case, the total number of IDs is about 2 billion, but there is no problem in practical use.

In FIG. 5, 6A is an address counter controlled by the main control circuit 4 (connection line is omitted in the figure), and is incremented by an increment counter (not shown) in between to address a _{0 to} a _11. Change. 6B is b _{0 to} b ₅ 64
An address counter for designating the bit address.
Now, temporarily, data is written in the large-capacity memory 2 in the order of key code 32 bits, ID 31 bits, and flag 1 bit.
When the memory 2 is transferred from the central management center 16 of FIG. 4 to the factory, the flag is set to 0. The first address (a ₀ ~a ₁₁ all 0) reading of data 63 bits of the main control circuit but has Setsutoparusu the flip flop 6F from 4 begins connexion by be supplied, the output of the monostable multivibrator 6M ₁ is Since it is at the L level, the memory 2 is in the read mode (there is also a memory in which the mode is reversed), and the first one bit appears in the data line at the output of the memory 2. When the flip-flop 6F is set and its Q output becomes H level, the pulse oscillator 6S oscillates. The oscillation frequency of the pulse oscillator 6S is selected to be a repetition frequency longer than the minimum time of the data write / read cycle of the memory 2, but if it is too high, it may be divided and then sent to the address counter 6B. If the 6S oscillation frequency is 100 KHz, the address counter 6B output
b _{0 to} b ₅ change every 10 μsec. Therefore, memory 2 to 3
The time to read one bit is 310 μsec. And b ₀ ~ b ₅
When all become 1, the output of the NAND gate 6G becomes L level and the flip-flop 6F is reset, so that its Q output becomes L level and stops the oscillation of 6S. On the other hand, the monostable multi 6M ₁ outputs a Q output of H level with a width of 100 μsec to put the memory 2 in the write mode, and writes + B, that is, a signal of 1 to the last address 111111 of b _{0 to} b _5. . Further, the monostable multi 6M ₂ is driven at the trailing edge of the Q output of the monostable multi 6M ₁ to generate a Q output having a width of, for example, 10 μsec, and the Q output clears the address counter 6B. Therefore, when the next address of a _{0 to} a ₁₁ is reached, b ₀
~ B ₅ are all 0. Hereinafter, the above operation is repeated. By doing this, the total of the ID and key code will be stored in the large capacity memory 2.
Paired with 63 bits, only the 1-bit flag is written. By doing so, even if the entire contents of the large-capacity memory 2 are not read and written in the memory 10, they can be sequentially exchanged with the succeeding large-capacity memory 2, so that the unused ID and key code can be discriminated. You can do it.

Next, we will describe the countermeasures for reading the flagged ID and key code twice and preventing duplication. FIG. 6 is a modified version of FIG.
(See Fig. 1)
It includes a check circuit configured to check the flag of 111111 in b _{0 to} b ₅ , and operates as follows. Operate the main control circuit 4 to output a negative pulse,
Drives monostable multivibrator 4M. The width of this 4M output pulse is set to 10 msec, for example, and during the H level,
It is assumed that the inputs c _{0 to} c ₅ appear at the output of the selector 6C. Since inputs c ₀ -c ₅ are all 1, it specifies a flagged address. At this time, address counter 6A
Is a _value of a _{0 to} a ₁₁ , for example, n, the output of the large capacity memory 2 is 0 or 1. If it is 0, no output appears in the NAND gate 62.
The operation is similar to that shown in the figure. That is, Q of monostable multi 4M
When the output becomes L level, the flip-flop 6F is excisional selector 6C outputs b ₀ ~b _5, because the AND gate 61 is turned on. On the other hand, the output of the large capacity memory 2 is 1
In the case of, the output of the NAND gate 62 becomes negative and the output of the OR gate 63 also becomes negative, and the address counter 6A is incremented +
Do 1 That, a ₀ ~a ₁₁ 6A address of (n + 1)
Becomes On the other hand, considering the output of the NAND gate 6G, c ₀
All the signals 1 of ~ c ₅ are sent to 6G and the output of 6G becomes a negative level, but while the output of monostable multi 4M is H level, A
Since the ND gate 61 is cut off and 6M ₁ is not driven, the W / R terminal of the memory 2 holds the L level, that is, the read mode. Although the flip-flop 6F is reset, its Q output can be reset any number of times until it is set at the trailing edge of the output of the monostable multi 4M. The addresses a _{0 to} a ₁₁ of the address counter 6A are (n + 1)
In even filed, if the flag is 1, the flow advances further (n + 2) address 6A so on a ₀ ~a ₁₁ from 1 decimal terms 4095, by returning to zero again, to address the total 4096 . That is, 4096 addresses are changed during 10 msec when the output of the monostable multi 4M is H level. Since this is about 0.5 μsec per address,
It can be said that the time is sufficient for reading. If it is too short for reading, set the output width of the monostable multi 4M to 100mse.
May be c.

Check all the contents of memory 10 as above,
You can check for the presence of flags. At this time, it is not necessary to read the contents of the memory address which has already been flagged again. In the above example, the flag address is 111111, but needless to say, this may be 000000.

EFFECTS OF THE INVENTION As is apparent from the above description, the present invention achieves its objects sufficiently and exhibits the following unique effects.

(a) It is possible to sequentially write in the memory to be attached to each terminal by using each data writing device without duplicating the ID and the key.

(b) Since the flag is set at the address of the memory where the ID and key data have been used once, the used ID and key can be immediately discriminated from the unused one.

(c) Since the data writing device can be physically locked, the factory in the system does not need to be directly involved in the writing to the memory, and therefore the security of data confidentiality is high.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of a data writing device according to the present invention, FIG. 2 is a flow chart for explaining the operation thereof, and FIG. 3 is a perspective view showing the appearance thereof, and FIG. FIG. 1 is a schematic diagram of a system to which a data writing device according to the present invention is applied. 5 is a block diagram of another embodiment of the data writing device according to the present invention, in particular, a block diagram of a device having a means for reading the stored contents of the memory twice and a duplicate write preventing means, and FIG. 6 is shown in FIG. It is a block diagram of the modification of an Example.

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-63-103533 (JP, A) JP-A-61-240385 (JP, A) Actually-opened Sho-61-14554 (JP, U)

Claims (1)

[Claims] 1. A device for writing data in a small-capacity memory mounted on a receiving terminal capable of storing a different address and master key for each terminal in a signal transmission / reception system, the device being relative to a physically lockable housing. A large-capacity memory is provided, and a non-volatile, or volatile, relatively small-capacity memory backed up by a battery or the like is connected to a terminal provided on the housing from the outside to provide the large-capacity memory. Is configured to read a part of the stored contents of the memory and sequentially write to the small-capacity memory, and the small-capacity memory attached to each one of the receiving terminals stores different data for each terminal. In order to prevent the same data from being written to a small-capacity memory when writing data to another receiving terminal, the storage area for storing a write flag corresponding to the data is written. Large content Providing a portion of the memory, the data writing apparatus according to claim.