JPH0625790B2 - Phase meter that corrects count error - Google Patents

Description

Description: (a) Technical Field of the Invention The present invention relates to a phase meter for measuring a phase difference between two signals, and more specifically, for correcting a count error in a count type phase meter. It is related to the phase meter.

(b) Prior art and problems First, FIG. 2 shows a block diagram of a phase meter according to the prior art.

In FIG. 2, 1 is a phase detector, 2 is a gate, 3 is a counter,
4 to 6 are input terminals, and 7 is an output terminal.

Next, the operation of FIG. 2 will be described with reference to the waveform chart of FIG.

FIG. 3A is a waveform diagram of an input signal applied to the input terminal 4, and FIG. 3A is a waveform diagram of an input signal applied to the input terminal 5.

The phase meter of FIG. 2 measures the phase difference between FIGS. 3A and 3A.

The phase detector 1 is composed of, for example, a flip-flop, and becomes “1” at the rising edge of FIG. 3A and becomes “0” at the rising edge of FIG.

FIG. 3C is an output waveform diagram of the phase detector 1, which is a square diagram.

FIG. 3D shows a clock applied to the input terminal 6. The square wave of FIG. 3C and the clock of FIG. 3D enter the gate 2, and the clock of FIG.

The clock of FIG. 3e is counted by the counter 3, and the phase difference between the signal of FIG. 3a and the signal of FIG. 3a is measured from the count value of the counter 3.

However, since the count value of the counter 3 is a pulse counting method, an error of ± 1 clock may occur with respect to the square wave of FIG.

In order to reduce such an error, the clock repetition frequency in FIG. 3D may be increased.

For example, in order to measure a signal of 500 KHz with an accuracy of ± 0.1 °, 500 KHz × 3600 = 1800 MHz
Although a clock having a repetition frequency of is required, there is a problem in that a high frequency device is required to do so.

(c) Objects of the Invention The present invention is a phase counter of clock counting system, and a delay circuit and a detection circuit are provided for extracting the difference between the rising and falling edges of the square wave of FIG. 3C and the clock of FIG. It is an object of the present invention to provide a phase meter capable of correcting the count error of the counting method without using a clock having a high repetition frequency.

(d) Embodiment of the Invention First, FIG. 1 shows a block diagram of an embodiment according to the present invention.

In FIG. 1, 11 is an inverter, 12 is a flip-flop,
Reference numeral 13 is a delay circuit, 14 and 15 are detection circuits, and 16 is an inverter.

1 to 7 of FIG. 1 are the same as those of FIG. 2, and FIG. 1 is obtained by adding 11 to 16 to FIG.

Next, the operation of FIG. 1 will be described with reference to the waveform chart of FIG.

FIGS. 4C and 4C show waveforms corresponding to FIGS. 3A and 3A, respectively, which are waveforms of signals applied to the input terminal 4 and the input terminal 5.

Fig. 4 (c) corresponds to Fig. 3 (c).
It is an output waveform of the phase detector 1 which detected the phase difference of FIG.

FIG. 4 (c) shows the fourth part in order to make the following explanation easier to understand.
This is an enlarged view from the front edge portion to the rear edge portion of the drawing.

In the embodiment of FIG. 4, the leading edge is the rising edge and the trailing edge is the falling edge.

FIG. 4C corresponds to FIG. 3D and is an enlarged view of the clock applied to the input terminal 6.

The waveform of FIG. 4C is inverted by the inverter 11 and becomes the edge input of the flip-flop 12.

The flip-flop 12 is a D-type flip-flop,
Since the state of the square wave shown in Fig. 4 is output at the falling edge of the inverted waveform in Fig. 4, the output of "1" is output when both are "1" and both are "0". At this time, an output of "0" is output.

FIG. 4 shows the output waveform of the flip-flop 12.

Looking at the rising portion of Fig. 4, it is delayed by Θ1 with respect to the square wave of Fig. 4. Further, when the trailing edge of FIG. 4 is seen, it is delayed by Θ2 with respect to the square wave of FIG.

FIG. 4 is an enlarged waveform diagram of the rising portion of FIG. 4, and FIG. 4C is an enlarged waveform diagram of the rising portion of FIG.

The difference between Fig. 4 and Fig. 4 becomes Θ1.

Since the gate 2 of FIG. 1 is opened and closed by the square wave of FIG. 4 and passes the clock signal of FIG. 4C, the output of the gate 2 becomes the clock of FIG.

According to the square wave shown in Fig. 4, about 3.
Five of them will pass through the gate 2, but according to the square wave of FIG. 4C, four of the clocks of FIG. 4C will pass through the gate 2.

Since the counter 3 in FIG. 1 counts the clocks in FIG. 4, the count value “4” comes out to the output terminal 7.

Next, the delay circuit 13, the detection circuit 14, and the detection circuit 15
FIG. 5 shows a configuration diagram of the embodiment.

The delay circuit 13 delays the clock of FIG. 4C by T / m with respect to the clock of FIG. 4C applied to the delay circuit 13 if one cycle of the clock of FIG. It is composed of connected m / 2 delay circuits. Fifth
The figure shows an embodiment in the case of m = 10, and the delay circuit 13 is 1
3A to 13E, the detection circuit 14 and the detection circuit 15 correspond to the delay circuit 13 and 14A to 14E and 15A, respectively.
5E each of 15E.

The detection circuit 14 receives the output of the delay circuit 13 and the output of the phase detector 1, and the detection circuit 15 receives the output of the delay circuit 13 and the inverted output of the phase detector 1.

The delay circuit 13 and the detection circuit 14 detect the difference Θ1 between the rising portion of the square wave of FIG. 4 and the rising portion of the square wave of FIG. 4, and the delay circuit 13 and the detection circuit 15 of FIG. The difference .THETA.2 between the falling edge of the square wave and the falling edge of FIG.

Next, the delay circuit 13, the detection circuit 14, and the detection circuit 15
The operation will be described with reference to FIG.

FIG. 4 is a waveform diagram showing an enlarged one cycle of the clock shown in FIG.

4A shows the output of 13E of the delay circuit 13, and FIGS. 4C to 4C show the delayed outputs of 13A to 13D of the delay circuit 13 in order.

The waveform levels shown in FIG. 4 are indicated by “1” and “0”, and the vertical column “9” in FIGS. 4 to 4 shows “01111” and the column “8”. Looking at it, it is "00111".

FIG. 6 summarizes these relationships.

The digital value of FIG. 6 is read by the decoder in the detection circuit 14, and if the decoder value and the value of Θ1 of FIG. 4 are made to correspond to each other, Θ1 of FIG. 4 can be read with the accuracy of the delay time of the delay circuit 13. You can

At the start of Fig. 4, the vertical column from Fig.
1100 ", and according to FIG. 6, Θ1 = 0.2.

Similarly, it is detected which part of the digital value in FIG. 6 the falling part in FIG. 4 corresponds to.

This digital value is read by the decoder in the detection circuit 15, and if the decoder value and the value of Θ2 in FIG. 4 are made to correspond to each other, Θ2 in FIG. 4 can be read with the accuracy of the delay time of the delay circuit 13.

It is assumed that the phase difference can be read with an accuracy of 1 from the output of the counter 3. If m / 2 delay circuits are used in the delay circuit 13 so as to delay each cycle T of the clock shown in FIG. 4 by T / m, then Θ1 and Θ2 in FIG. m)
It can be measured with an accuracy of °.

Since the decimal system is generally used, the clock 1
If a delay circuit that divides the period T into 10 equal parts is adopted,
The values of Θ1 and Θ2 can be obtained with an accuracy of 1/0 °.

The value of Θ1 obtained by the detection circuit 14 in FIG.
If the value of Θ2 obtained in step 5 is added to the output of the counter 3, the value that could not be corrected within 1 count of the counter 3 can be measured with the accuracy of the delay circuit 13.

That is, if the output of the output terminal 7 is N1, the output of the output terminal 8 of the detection circuit 14 is N2, and the output of the output terminal 9 of the detection circuit 15 is N3, the measured value of the phase meter in FIG. 1 is N1 +
It is calculated by (N2-N3).

For example, if N1 = 4, N2 = 0.7, N3 = -0.2,
The phase difference is 4 + 0.7-0.2 = 4.5 °.

(e) Effect of the Invention According to the present invention, the phase difference between two signals is replaced with a square wave,
In a phase meter that counts clocks only during this square wave, one cycle T of the clock is divided into m equal parts, and (T /
Since m / 2 delay circuits that delay the square wave by m) and a detection circuit that corrects the error of less than 1 clock of the counter from the delay circuit output and the square wave are adopted, the clock repetition frequency is The phase difference can be accurately measured without increasing it.

[Brief description of drawings]

1 is a block diagram of an embodiment according to the present invention, FIG. 2 is a block diagram of a phase meter according to the prior art, FIG. 3 is a waveform diagram of each part of FIG. 2, FIG. 4 is a waveform diagram of each part of FIG. FIG. 5 shows a delay circuit 13, a detection circuit 14 and a detection circuit 1.
6 is a digital diagram showing the relationship between the output of the delay circuit 13 and .THETA.1 and .THETA.2. 1 ... Phase detector, 2 ... Gate, 3 ... Counter, 4
~ 6 ... input terminal, 7 ~ 9 ... output terminal, 11 ... inverter, 12 ... flip-flop, 13
...... Delay circuit, 14 ・ 15 …… Detection circuit, 16 …… Inverter.

Claims (1)

[Claims] 1. A phase detector replaces a phase difference between a first signal and a second signal with a square wave, and the square wave opens and closes a gate.
A phase in which a clock having a repetition period shorter than that of the square wave is applied to the gate, the clock passing through the gate is counted by a counter, and the phase difference between the first signal and the second signal is measured from the output N1 of the counter. In the total, one cycle T of the clock is divided into m equal parts, and m / 2 delay circuits connected in series for delaying the clock by T / m, operating with the rising edge of the square wave and the clock, A flip-flop whose output opens and closes the gate; a first detection circuit which detects a difference Θ1 between a leading edge of the flip-flop output and a leading edge of the output of the phase detector from the delay circuit output; A second detection circuit for detecting a difference .THETA.2 between the trailing edge of the flip-flop output and the trailing edge of the output of the phase detector from the output of the delay circuit; of The output of the detection circuit N3
At the time, the phase difference is set to N1 + (N2-N3), and the one-phase error of the counter is corrected.