JPH0626254B2 - Method for manufacturing semiconductor pressure sensor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor pressure sensor.

More specifically, the present invention relates to a method for manufacturing a semiconductor pressure sensor in which a diaphragm and a support substrate are integrally formed by utilizing an etching method.

(Prior Art) FIG. 4 is an explanatory diagram of a configuration of a conventional example which is generally used in the past.

In the figure, 1 is a substrate made of a semiconductor. A diaphragm 2 is attached to the substrate 1 and receives the measurement pressure P. Reference numeral 21 is a concave portion that forms the diaphragm main body portion 22 in the diaphragm 2. Reference numeral 3 is a piezo resistance gauge provided on the diaphragm main body 22.

In the above structure, when the measurement pressure P is applied to the diaphragm main body 22, distortion occurs, and the output corresponding to the measurement pressure P is obtained from the piezo resistance gauge 3.

(Problems to be Solved by the Invention) In such a conventional device, the recess 21 is formed in the substrate 1.
The diaphragm 2 provided with is attached and assembled.

In this case, a joining technique for attaching the diaphragm 2 to the substrate 1 is required, and the joining strength, the difference in temperature expansion coefficient, and the like become problems, which greatly affects the characteristics of the device.

The present invention solves these problems.

An object of the present invention is to provide a semiconductor pressure sensor that has good pressure resistance characteristics and temperature characteristics, is suitable for mass production, and is inexpensive.

(Means for Solving the Problems) In order to achieve this object, the present invention is a semiconductor pressure sensor having a diaphragm, which comprises the following steps.

(1) A step of forming a P-type conductivity type portion by doping impurities into an n-type conductivity type silicon substrate portion corresponding to a recessed portion forming a diaphragm.

(2) A step of stacking an epitaxial layer of the n-type conductivity type on the silicon substrate.

(3) A step of applying a mask for preventing etching to a required portion on the other surface side of the n-type substrate.

(4) A step of performing etching from the other surface side of the n-type substrate until reaching a P-type conductivity type portion due to the impurity doping.

(5) A semiconductor bias sensor is manufactured by applying a reverse bias voltage between the impurity-doped portion and the silicon substrate portion and between the doped portion and the epitaxial layer to remove the concave portion by anisotropic etching. The process of configuring.

Is adopted.

(Operation) In the above configuration, when a measurement pressure is applied to the diaphragm, a strain is generated, and an output corresponding to the measurement pressure is obtained from the piezoresistive gauge.

In this case, the semiconductor pressure sensor integrated with the substrate and the diaphragm is formed by doping an impurity into a portion corresponding to the concave portion to form a P-type conductivity type portion and removing the n-type conductivity type portion by etching. Obtainable.

Hereinafter, detailed description will be given based on examples.

(Embodiment) FIG. 1 is a manufacturing process chart of an embodiment of the present invention.

In the figure, the same symbols as in FIG. 4 indicate the same functions.

Only the parts different from FIG. 4 will be described below.

(1) A portion A corresponding to the recess 21 of the n-type substrate 1 is doped with P-type impurities as shown in FIG. 1 (a). In this case, boron is doped.

In addition to the portion corresponding to the concave portion 21, the band-shaped portion 23 extends from the concave portion 21 as shown in FIG. 1 (b), which corresponds to each concave portion 21 when boron doping is performed on a wafer-by-wafer basis. This is so that the portion A can be electrically conducted by the strip portion 23.

(2) As shown in FIG. 1 (c), an n epitaxial layer is formed on one side of the n-type substrate. (3) As shown in FIG. 1 (d), silicon nitride (n) is formed on the other side of the n-type substrate. SiN) film mask is applied. The silicon nitride film (SiN) has an etching rate of 2 A ° / min or less with respect to an alkaline anisotropic etching solution and has a sufficient masking ability.

(4) As shown in FIG. 1 (e), alkali etching is performed from the other surface side of the n-type substrate to a depth reaching the recess 21.

(5) As shown in FIG. 1 (f), the P of the substrate 1 and the diaphragm 2 is
A reverse bias voltage E is applied to the / N junction portion and alkali etching is performed to form the diaphragm 2 and the substrate 1. In the reverse bias state, only the P-type layer is etched.

(6) As shown in FIG. 1 (g), a semiconductor process for forming the piezoresistive gauge 3 lead wire 31 is performed.

Even if anisotropic etching is carried out by alkali etching, as shown in FIG. 2, it is initially quadrangular, but can finally be circularly etched.

As a result, (1) since the substrate 1 and the diaphragm 2 are integrally formed, it is not necessary to join the substrate 1 and the diaphragm 2,
The problem of instability due to joining is eliminated.

(2) Since the substrate 1 and the diaphragm 2 are made of the same silicon, there is no temperature fluctuation of the zero point due to the difference in thermal expansion coefficient.

(3) The position, thickness and shape of the silicon diaphragm 2 can be accurately controlled by anisotropic etching in which a reverse bias voltage is applied.

(4) Since each wafer can be processed, it is suitable for mass production.

(5) The diaphragm can be easily formed by using a normal semiconductor process technology.

(6) Since mechanical processing is not used to process the silicon diaphragm, the fracture strength is high.

(7) Since the main body of the diaphragm 2 is composed of the n-epitaxial layer, it can be made extremely thin and a device for a low pressure range such as a differential pressure gauge can be easily manufactured.

FIG. 3 is an explanatory view of a main part configuration of another embodiment of the present invention.

In this embodiment, the piezo resistance gauge 3 and the lead wire 3
The diaphragm 2 is alkali-etched after the completion of the semiconductor process of formation 1.

In this case, the reverse bias P ⁺ terminal 32 during etching is used.
Need to be provided.

(Effects of the Invention) As described above, the present invention adopts a method for manufacturing a semiconductor pressure sensor having the following steps in a semiconductor pressure sensor having a diaphragm.

(1) A step of forming a P-type conductivity type portion by doping impurities into an n-type conductivity type silicon substrate portion corresponding to a recessed portion forming a diaphragm.

(2) A step of stacking an epitaxial layer of the n-type conductivity type on the silicon substrate.

(3) A step of applying a mask for preventing etching to a required portion on the other surface side of the n-type substrate.

(4) A step of performing etching from the other surface side of the n-type substrate until reaching a P-type conductivity type portion due to the impurity doping.

(5) A semiconductor bias sensor is manufactured by applying a reverse bias voltage between the impurity-doped portion and the silicon substrate portion and between the doped portion and the epitaxial layer to remove the concave portion by anisotropic etching. The process of configuring.

Therefore, a semiconductor pressure sensor in which the substrate and the diaphragm are integrated can be obtained.

As a result, (1) there is no problem of instability due to bonding as in the case where the substrate and the diaphragm are separate bodies. (2) Since the substrate and the diaphragm are made of the same silicon, there is no temperature fluctuation of the zero point due to the difference in thermal expansion coefficient. (3) The position, thickness, and shape of the silicon diaphragm can be accurately controlled by anisotropic etching in which a reverse bias voltage is applied.
(4) Since each wafer can be processed, it is suitable for mass production.

(5) The diaphragm can be easily formed by using a normal semiconductor process technology. (6) Since mechanical processing is not used to process the silicon diaphragm, the fracture strength is high. (7) Since the main body of the diaphragm is composed of the epitaxial layer of the first conductivity type, it can be made extremely thin and a device for a low pressure range such as a differential pressure gauge can be easily manufactured. (8) A circular diaphragm can be manufactured even by anisotropic etching.

Therefore, according to the present invention, it is possible to realize a semiconductor pressure sensor which has good pressure resistance characteristics and temperature characteristics, is suitable for mass production, and is inexpensive.

[Brief description of drawings]

FIG. 1 is an explanatory view of an embodiment of the present invention, FIG. 2 is an operation explanatory view of FIG. 1, FIG. 3 is a structural explanatory view of another embodiment of the present invention, and FIG. It is a block diagram of the conventional example. 1 ... Substrate, 2 ... Diaphragm, 21 ... Recess, 22
...... Diaphragm body part, 3 ... Piezo resistance gauge.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hiroshi Suzuki 2-932 Nakamachi, Musashino City, Tokyo Yokogawa Electric Co., Ltd. (72) Inventor Tetsuya Fujita 2-932 Nakamachi, Musashino City Tokyo (72) Inventor Nobuyuki Yamashita 2-9-32 Nakamachi, Musashino-shi, Tokyo Inside Yokogawa Electric Co., Ltd.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor pressure sensor having a diaphragm, which comprises the following steps. (1) A step of forming a P-type conductivity type portion by doping an impurity into a portion of an n-type conductivity type silicon substrate corresponding to a concave portion forming a diaphragm. (2) A step of stacking an epitaxial layer of the n-type conductivity type on the silicon substrate. (3) A step of applying a mask for preventing etching to a required portion on the other surface side of the n-type substrate. (4) A step of performing etching from the other surface side of the n-type substrate until reaching a P-type conductivity type portion due to the impurity doping. (5) A semiconductor bias sensor is manufactured by applying a reverse bias voltage between the impurity-doped portion and the silicon substrate portion and between the doped portion and the epitaxial layer to remove the concave portion by anisotropic etching. The process of configuring.