JPH0626314B2 - Digital-to-analog converter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital-analog converter, and more particularly to a digital-analog converter suitable for use in converting a digital audio signal into an analog audio signal.

<Prior Art> In a compact disc player (CD player) and a digital tape recording / reproducing apparatus (DAT apparatus), it is necessary to convert a digitally expressed music signal into an analog signal and output the analog signal.

As shown in FIG. 10, a commonly used digital analog converter for reproducing music (referred to as a DA converter) is a digital / current converter for converting digital data DT input in a sampling cycle into a direct current I _o. 1 and the current I _{o is changed} to the voltage S every time the sampling pulse P _S is generated.
_D (see FIG. 11) and holds the current / voltage converter 2, and low-pass filter 3 that outputs the output voltage S _D after shaping it into a continuous smooth analog signal S _A. Has been done. The movable contact of the switch SW in the current / voltage converter 2 is switched by the sampling pulse P _S to form an integrator in the illustrated a contact state to generate a voltage S _D according to the current I _o , and a b contact. In the state, a hold circuit is configured to hold the voltage.

The most serious problems in such a DA converter for reproducing music are the conversion accuracy for converting digital data into a current value, the conversion speed thereof, and the phase distortion due to the low-pass filter.

Among these, the conversion accuracy and the conversion speed are improved by the higher speed of the LSI and the progress of the trimming technique, and there is no problem. However, although the phase distortion due to the low-pass filter can be reduced by adopting a digital filter, it cannot be eliminated because of the structure.

FIG. 12 is an explanatory diagram of phase distortion, and FIG. 12 (a) shows an original audio signal waveform 5a, a 1 KHz component waveform 5b, and 8
The KHz component waveform 5c is shown, and FIG. 12 (b) shows the audio signal waveform 6a output from the low-pass filter 3 (FIG. 10), the 1 KHz component waveform 6b, and the 8 KHz component waveform 6c. As you can see from this waveform diagram, 8KH
The output audio signal 6a is different from the original audio signal 5a due to the presence of the phase delay of the z component, the phase distortion is particularly large at high frequencies, and the presence of the low pass causes a great deterioration in sound quality.

Further, the output of the low-pass filter when the pulsed signal is input becomes slower at the rising portion 7a and vibrates at the envelope portion 7b and the falling portion 7c as shown in FIG. For this reason, when a music signal with a large number of impulse-like changes is input, the sound quality changes greatly, and sometimes the sense of rhythm also changes.

For this reason, the inventors of the present application, the unit pulse response signal generator 1 for generating the unit pulse response signal SP (see FIG. 15) as shown in FIG. 14, and the 16-bit unit pulse response signal generator 1 for every predetermined time ΔT. A digital data generator 2 for generating digital audio data, a multiplier 3 for multiplying a unit pulse response signal generated at a certain time by the predetermined digital data, and unit pulse response signals multiplied by the digital data are synthesized. Has proposed a digital-analog converter having a synthesizer 4 for outputting an analog signal.

In the proposed digital-analog converter, when the unit pulse response signal generator 1 divides the unit pulse response signal waveform SP at a predetermined time ΔT interval (see FIG. 15), each divided partial signal waveform S _K ( K = −4 to 4) as shown in FIG. 16 (only S ₋₁ , S ₀ , and S ₁ are shown) every time ΔT, and the digital data generator 2 generates the latest data every predetermined time ΔT. 16-bit digital audio data is sequentially shifted and stored in the built-in shift register, and each multiplication DA converter of the multiplication unit stores the partial waveform signal S _k.
And a predetermined 16-bit digital audio data V _K stored in the shift register corresponding to the partial waveform signal.
, And the synthesizing unit 4 synthesizes the signals output from the multiplying circuits to synthesize an analog signal S _A (= ΣS _K · V
_K (K = −4 to 4)) is output.

<Problems to be Solved by the Invention> According to the proposed digital-analog converter, there is an advantage that a continuous analog signal without phase distortion can be generated, but a 16-bit multiplication type DA converter is used. Since it is necessary, there is a problem that the cost becomes high.

Further, in this proposed digital-analog converter, the partial signal waveform S _K input to the multiplication DA converter is the 16th
As shown in the figure, the waveform becomes discontinuous every ΔT, and since the multiplying DA converter requires 16 bits, the settling time becomes long. Then, there is a problem that spike-like noise is added to the analog signal S _A output from the combining unit 4 for each ΔT due to the discontinuity of the signal and the relatively long settling time. The waveform of the analog signal S _A when the unit pulse UP is input to the proposed digital-analog converter is shown in FIG. When the unit pulse UP is input, the analog signal S _A must have the waveform shown in FIG.
Due to the settling time of the converter, a spike-like noise is added every ΔT.

From the above, an object of the present invention is to provide a DA converter capable of generating a continuous analog signal without phase distortion.

Another object of the present invention is to reduce the number of bits of the multiplication type DA converter, resulting in low cost, and an accurate analog signal in which spike noise is not added to the analog signal obtained by the DA conversion. Is to provide a DA converter that can obtain

<Means for Solving Problems> FIG. 1 is a schematic explanatory view of the present invention.

Reference numeral 10 is a digital data generator that generates digital data at predetermined time intervals, 11 is a digital data storage unit that stores digital data while sequentially shifting it, 12 is a unit pulse response signal generator, 13 is a digital data storage unit and unit pulses A multiplying unit 14 connected to the response signal generator is a combining unit that combines a plurality of signals output from the multiplying unit and outputs an analog signal S _A.

<Operation> Partial signal generators 12 _-4 , 12 _-3 , ..., 12 ₃ , 12 ₄ of the ROM configuration in the unit pulse response signal generator 12
Thus, the partial signals S _-4 , S _-3 , ..., S ₃ , S ₄ when the unit pulse response signal is divided at predetermined time intervals are repeatedly generated digitally. In addition, the digital data storage unit 11
Of the shift register configuration _11-4 , _11-3 , ...
16-bit digital data generated at predetermined time intervals in 11 ₃ and 11 ₄ are stored while being sequentially shifted.

Each multiplication circuit 13 _K is stored in the storage circuit 11 _K 1
The 6-bit digital data V _K is converted into an analog signal, and the built-in multiplication DA converter multiplies the analog signal by the digital partial signal value output from the predetermined partial signal generator 12 _K, and outputs the signal. The synthesizing unit 14 synthesizes the signals M _K output from the respective multiplication DA converters 13 _K and outputs an analog signal S _A.

Partial digital data output from the signal generator 12 _K can sufficiently represent the partial signal waveform accurately unit pulse response signal if at most 8 bits. Therefore, the multiplication circuit 113
_{Since the} number of bits of the _K multiplication DA converter can be set to 8 bits, the cost can be reduced as compared with the conventional 16-bit multiplication DA converter, and the settling time can be shortened. Spike noise can be eliminated.

<Example> As shown in FIG. 2, the time axis is divided into predetermined time intervals ΔT,
Each time slot T _k (k = ... T _-4 , T _-3 , T _-2 ,
_{T -1, T 0, T 1} , T 2, T 3, T 4, V discrete-time signal values at ...) (digital value) as shown in FIG. 3 _k Tosureba discrete-time signal RTS The continuous-time signal for is obtained by superposing along the time axis the pulse response signals weighted by the digital data V _k that are input moment by moment.

The fourth (a) is a unit pulse signal in the time slot T ₀ , and the fourth (b) is a unit pulse response signal waveform for the unit pulse signal, which is a spline signal waveform as one embodiment. It should be noted that the unit pulse response signal exists over the entire period from −∞ to + ∞ on the time axis, and is abruptly attenuated as the time goes from the time slot T ₀ to −∞ or + ∞. is there.

From the above, the digital data V in the time slots T _-1 , T ₀ , T ₁ of the discrete time signal RTS shown in FIG.
Focusing only on _-1 , V ₀ and V ₁ , each digital data V
_-1 , pulse response signals SP _-1 , S for V ₀ , V ₁
Since P ₀ and SP ₁ are shown by the dotted line, the solid line, and the alternate long and short dash line in FIG. 5, these are represented by the old time slots T _k (k =
-∞, ··· -2, −1,0,1,2, ···), and the continuous time for three digital data V ₋₁ , V ₀ , V ₁ by sequentially synthesizing and outputting each time ΔT. The signal is obtained. In addition, each pulse response signal SP ₋₁ , S in FIG.
P ₀ and SP ₁ are unit pulse response signals SP (fourth
(See FIG. 6B) is multiplied by V _-1 , V ₀ , and V ₁ .

The above is the case of three digital data, but a continuous time signal can be similarly obtained when the digital data in all time slots are considered. Considering that the pulse response signal is rapidly attenuated, it is sufficient that the number of pulse response signals to be combined in each time slot is at most nine. That is, assuming that the time slot at the current time is T _k , if pulse response signals for nine digital data in time slots T _{k-4 to} T _{k + 4} are combined, a sufficiently accurate continuous time signal is generated at T _K. can get.

FIG. 6 is a block diagram of a digital-analog converter according to the present invention, showing one channel (for example, L-channel). In the figure, 10 is a digital data generator, 11 is a digital data memory, 12 is a unit pulse response signal generator, 13 is a multiplier connected to the digital data memory and the unit pulse response signal generator, and 14 is a multiplier. Is a synthesizing unit for synthesizing a plurality of signals output from the above and outputting an analog signal S _A.

The digital data generator 10 uses the bit clock BCLK,
Shift clock BCLK _L , latch clock LCLK,
For example, 16-bit digital data DTL (see FIG. 3) is generated at a predetermined time (sampling time) ΔT interval while generating the sampling clock SHCLK and the like.

The digital data storage unit 11 is composed of n stages (9 stages in FIG. 6) of shift register units 11a and n stages of latch units 11b. The shift register unit 11a is a 16-bit shift register 11a- _{4 to} 11 that shifts data serially to each stage if digital data is 16 bits.
has a _4, the latch portion 11b has a latch circuit 11b _-4 ~11b ₄ of 16 bits in each stage. The digital data generator 10 sequentially outputs digital data (L-channel data) DTL bit serially to the data line I _D at sampling time ΔT intervals, and at the same time, in synchronization with the bit clock signal BCLK, the shift clock BCLK _L. To generate the shift register 11a at each stage
_The digital data stored in _k are sequentially transferred to the shift register 11a _k-1 of the next stage, and after the transfer, the latch clock LCLK is generated to latch the contents of the shift register 11a _k of each stage in the corresponding latch circuit 11b _k . Let still,
Assuming that the current time slot is T ₀ (see FIG. 3), the digital data generator 10 outputs the digital data V ₄ in the time slot T ₄ after four sampling times.

Therefore, assuming that the current time slot is T ₀ , the shift register 11a _-4 and the latch circuit 11b _-4 store the digital data V _-4 , and the shift register 11a _-3 and the latch circuit 11b _-3 store the digital data V _{4. -3} is stored, and _thereafter , similarly, the shift register 11a ₄ and the latch circuit 11b ₄ are stored.
The digital data V ₄ is stored in.

The unit pulse response signal generator 12 is for generating the signal shown in FIG. 4 (b) which is a unit pulse response signal, and divides the unit pulse response signal waveform at ΔT intervals which is a sampling time to obtain n (for example, 9) partial waveform signals S _-4 ,
A partial signal generator 12 _k that repeatedly generates S _-3 , S _-2 , S _-1 , S ₀ , S ₁ , S ₂ , S ₃ , S ₄ (see the fourth (b)) at each sampling time ΔT. (K = -4, -3,
・ ・ 4) The partial signal S _-1 is Figure 16 which is generated from the partial signal generator 12 _-1 (a), the partial signal S is generated from the partial signal generator 12 _{0 0} Fig. 16 (b)
The partial signals _{S 1} generated from the partial signal generator 12 ₁
See FIG. 16 (c). From the above, the unit pulse response signal generator 12 generates the partial signal S _k (k = −4 to 4) at each sampling time ΔT, in other words, 1 in total.
One unit pulse response signal SP is generated and input to the multiplication unit 13. The reason why the nine partial waveforms S _k (k = −4 to 4) are used and the other partial waveforms are not used is that the unit response signal is abruptly attenuated to almost zero in the other portions, which can be ignored. Because.

FIG. 7 is a block diagram of the partial signal generator 12 _K.
2a is a counter, 12b is a ROM, and 12c is a latch circuit. The counter 12a is cleared of the count value by the reset pulse CCLK generated at the sampling cycle ΔT, and counts the bit clock signal BCLK of the frequency a · _S ( _S is the sampling frequency) to detect the R of the next stage.
Generating an address signal _{A S} of OM12b. ROM12
In b, the digital values of the partial signals S _k digitized at intervals of time 1 / (a · _S ) are continuously stored in the order of addresses. Therefore, ROM 12 b is stored in the latch circuit 12c and outputs sequentially reads the digital values from the storage address signal A _S output from the counter 12a is instructed. As a result, the discrete partial waveform S _k is obtained from the latch circuit 12c and input to the multiplication unit 13. Although the more accurate the partial waveform signal S _k is obtained as the number of bits of the digital value and a is increased, in practice, if the number of bits is 8 bits and a is 40 or more, the unit pulse response signal is sufficiently accurate. The partial signal S _K of can be expressed.

The multiplication unit 13 includes n (9 in FIG. 6) multiplication circuits (MD
AC _{-4 to} MDAC ₄ ) 13 _{-4 to} 13 ₄ . Multiplier circuit 13 _-4 outputs an analog signal M _-4 multiplies the partial signal S _-4 to digital data V _-4 stored in the latch circuit 11c _-4 are analog and digital representations that DA conversion, multiplier circuit 13 _-3 outputs an analog signal M _-3 multiplies the partial signal S _-3 to digital data V _-3 stored in the latch circuit 11c _-3 are analog and digital representations that DA conversion, hereinafter similarly each multiplication circuit 13 _k is the digital data _{V k} stored in the latch circuit 11b _k DA
Converted analog signal and digitally represented partial signal S
Multiply _k to output the analog signal M _K. Therefore, assuming that the current time slot is T ₀ , M _k = S _k · V _k (k = −4, −3, ..., 3, 4) from each multiplication circuit 13 _k.
The analog signals indicated by are output respectively.

FIG. 8 is a block diagram of the multiplication circuit 13 _K , and 13 a is a DA converter that DA-converts the 16-bit digital data V _K stored in the latch circuit 12 b _K. As the DA converter 13a, an ordinary ladder resistance type or integral type low cost type can be used. 13b is a sampling hold circuit for sampling and holding the clock signal SHCLK the DA converted analog signal _{A K} by the DA converter 13a. The sampling and holding circuit 13b is a 16-bit DA converter 13a.
It is provided to remove the glitch in consideration of the settling time.

Reference numeral 13c is an 8-bit multiplying DA converter. Digital data V _K converted into an analog signal A _K is input at a speed of a sampling frequency f _{S to} a reference voltage terminal V _REF , and digital representation is made to a digital input terminal. The 8-bit partial signal S _K thus input is input at a speed of a · f _S , and these are multiplied to output an analog signal M _K.

Combining unit 14 has a known configuration of analog adder, the analog signal M _k output from the multiplier circuit 13 _-4 to 13 ₄
(S _k · A _K ) is combined and output.

Therefore, the analog signal (continuous time signal) S _A output from the synthesizing unit 14 in the time slot T ₀ is a signal (the signal obtained by multiplying the digital data V ₀ (analog signal A ₀ ) and the partial signal S ₀ in the time slot ( this signal was multiplied by the corresponding solid line M ₀₎ in the time slot T ₀ of FIG. 5, the digital data V _-1 in time slot T _-1 and (analog signal a _-1) and a partial signal S _-1 Signal (dotted line portion M in time slot T ₀ in FIG. 5)
_-1 ) and the digital data V ₁ (analog signal A ₁ ) in the time slot T ₁ and the partial signal S ₁ (corresponding to the one-dot chain line portion M ₁ in the time slot T ₀ in FIG. 5). To be a composite signal.

FIG. 9 shows a sampling time ΔT (= 1/1 /) of the original analog signal S _OR and the original analog signal S _OR which are continuous time signals.
A discrete time signal RTS digitized for each _S
The analog signal M output from the multiplication circuit 13 _-1 shown in the figure
_-1, analog signals _{M 0} output from the multiplication circuit 13 ₀
And the analog signal M output from the multiplication circuit 13 _1.
2 is a waveform diagram of the combined signal S _A output from the combination unit ₁ and FIG.

<Advantages of the Invention> As described above, according to the present invention, it is possible to provide a DA converter capable of generating a continuous analog signal without phase distortion, and
Since the number of bits of the multiplication DA converter of each multiplication circuit 13 _K can be set to 8 bits, the cost can be reduced as compared with the conventional multiplication DA converter having a 16-bit configuration.
Moreover, since the settling time can be shortened, spike-like noise that has been conventionally generated in the output can be eliminated.

[Brief description of drawings]

FIG. 1 is a schematic explanatory view of the present invention, FIGS. 2 to 5 are explanatory views of the principle of the present invention, and FIG. 2 is an explanatory view of time slots when the time axis is divided by ΔT, and FIG. Is an explanatory diagram of digital data in each time slot, FIG. 4 is a signal waveform diagram as one embodiment which is a unit pulse response, FIG. 5 is a pulse response signal waveform diagram for three consecutive digital signals, and FIG. FIG. 7 is a block diagram of a digital-analog converter according to the present invention, FIG. 7 is a block diagram of a partial signal generator, FIG. 8 is a block diagram of a multiplication circuit, FIG. 9 is a waveform diagram of each part in FIG. 6, and FIG. FIG. 11 is a block diagram of the digital-analog converter of FIG. 11, FIG. 11 is a waveform diagram of each part thereof, FIGS. 12 and 13 are explanatory diagrams of phase distortion and waveform distortion in a conventional digital-analog converter, and FIGS. Being de FIG. 17 is an explanatory diagram for explaining an outline of the digital analog converter, and FIG. 17 is a waveform diagram for explaining a conventional defect. 10 ...... digital data generator, 11 ...... digital data storage unit, 11 _-4 to 11 ₄ ...... storage circuit, 12 ...... unit pulse response signal generator, 12 _-4 to 12 ₄ ...... partial signal generating section, 13 ...... multiplication unit, 13 _-4 to 13 ₄ ...... multiplier circuit, 14 ...... combining unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor, Kazuo Toraichi, 1-1-14 Irumagawa, Sayama City, Saitama Prefecture (56) References JP 55-161296 (JP, A) JP 1-117423 (JP, A) Actual opening 63-55687 (JP, U) Actual opening 55-107740 (JP, U)

Claims (1)

[Claims] 1. A digital data generator that generates one digital data every predetermined time ΔT, and a shift register that stores the latest n digital data generated from the digital data generator while sequentially shifting by a shift clock. When the unit pulse response signal is divided into n partial signals at the predetermined time ΔT interval, each divided partial signal is divided by time Δ.
N partial signal generators having a ROM configuration that are repeatedly generated digitally for each T, n DA converters that convert each digital data stored in the storage unit into analog signals, and each partial signal generator Output from each of the multiplication DA converters, and n multiplication type DA converters for multiplying the digital partial signals output from the digital signals and the analog signals obtained by DA converting the digital data corresponding to the partial signals. A digital-to-analog converter having a synthesizing unit for synthesizing signals to output analog signals.