JPH0626344B2 - Intermittent transmission circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an intermittent transmission circuit, and more particularly to an intermittent transmission circuit that performs a transmission operation at specific time intervals in order to reduce the power consumption of a battery for power supply.

2. Description of the Related Art Conventionally, this type of intermittent transmission circuit has been constructed as shown in FIG. That is, a plurality of flip-flops FF
Min configured by frequency divider is time to generate a specific time signal V _T by dividing the clock signal CLK signal generating section having a
100a, a transmitter 100b including a plurality of frequency dividers each having a plurality of flip-flops, and a controller 20 for receiving a time signal V _T and outputting a switching signal V _C for switching between a standby mode and a transmission mode. , A switching circuit 30 for allocating the clock signal CLK to the time signal generation unit 100a and the transmission unit 100b by the switching signal V _C, and the transmission unit 100b normally transmits the input signal V _{in at} a time interval of several tens of seconds to several minutes. It was configured to operate. To describe the configuration in detail, the transmission unit 100b is composed of a plurality of flip-flops that generate an output V ₁₁ by dividing the clock signal CLK into a division ratio corresponding to the transmission data “1”. a peripheral circuit 11, generates an output V ₁₂ that the frequency division ratio divider associated clock signal CLK to transmit data "0", and a clock input C _L for the latch input of the latch circuit 14, a plurality of flip And a frequency dividing circuit 2b composed of a group. The latch circuit 14 latches the input signal V _i by the clock input C _L and generates the output V ₁₄ . The switching circuit 16 receives the output V 14 of the latch circuit 14 and outputs the output V ₁₄ of the frequency dividing circuit 11.
_{One of 11} and the output V ₁₂ of the frequency dividing circuit 12 is selected and output to the counter 13. The counter 13 counts the output V ₁₆ of the switching circuit 16, and the output of each stage of the counter 13 is input to the decoder 15 and decoded, and the level signal V _L of the transmission waveform is output. The level signal V _L is input to the operational amplifier 7b, and the transmission signal V ₀ is output.

In this transmission signal V ₀ , the frequency ratio of logical values “1” and “0” is 1 to 1.5 with respect to 1 bit of data, and each is 1
Wavelength and 1.5 wavelength signals, ie MSK (Minimum Shift Ke
ying) signal is being used.

FIG. 3 is a waveform diagram of the switching signal V _C output from the control unit 20 shown in FIG. The switching period of the pulse width T ₁ of the signal V _C is the transmission mode, transmission operation is performed in the transmitting unit 100b, the period T ₂ is in the standby mode, the division operation is performed by the time signal generating section 100a, These are alternated.

FIG. 4 is a waveform of a signal of each part in the transmission mode. V _IN is data to be transmitted as an input signal. V ₁₄ is the output of the latch circuit 14, which controls the switching circuit 16 to output V ₁₁ of the frequency dividing circuit 11 (the frequency dividing ratio corresponding to data “0”) and the frequency dividing circuit 12 (data “data“ 0 ”). The output V ₁₂ of the frequency division ratio corresponding to 1 ″ is switched and output as the output V ₁₆ of the switching circuit 6b. The counter 13 counts this V ₁₆ and the decoder 15 decodes it.
When the operational amplifier 17 processes, the transmission signal V ₀ is output.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention The conventional intermittent transmission circuit described above includes a time signal generation unit 100a.
, And even though the transmission unit 100b operates alternately, it has a separate frequency divider circuit, so when one frequency divider circuit is operating, the other frequency divider circuit is stopped. However, there is a drawback that the circuit is redundant, the use efficiency is low, and the high integration ratio is hindered.

Therefore, the present invention is intended to provide an intermittent transmission circuit in which the use efficiency of circuit elements is high and high integration can be realized.

Means for Solving the Problems An intermittent transmission circuit according to the present invention includes a plurality of flip-flops, a first frequency dividing circuit that receives a clock signal and divides the frequency, and a plurality of flip-flops. A second frequency dividing circuit for receiving and dividing the frequency, a third frequency dividing circuit having a plurality of flip-flops, a latch circuit for latching an input signal, and a plurality of flip-flops of the first frequency dividing circuit. A first flip-flop that receives an output of a specific flip-flop of the second frequency divider circuit and an output of a specific flip-flop of the plurality of flip-flops of the second frequency dividing circuit, and switches and outputs according to an output signal of the latch circuit. The switching circuit and the output of a specific flip-flop among the plurality of flip-flops of the third frequency dividing circuit are received, and a switching signal for switching between the standby mode and the transmission mode is output. The switching signal indicates the standby mode in response to the output of the control unit for controlling the input, the output of the specific flip-flop of the plurality of flip-flops of the second frequency dividing circuit, and the output of the first switching circuit. When the switching signal indicates the transmission mode, the output of the second frequency dividing circuit is output as the clock input to the third frequency dividing circuit, and when the switching signal indicates the transmission mode, the output of the second frequency dividing circuit is output to the third frequency dividing circuit. A first switching circuit for supplying a clock signal to the frequency dividing circuit as a clock input and supplying the output of a specific flip-flop among the plurality of flip-flops of the second frequency dividing circuit to the latch circuit as a latch signal; And a decoder circuit which decodes outputs of a plurality of specific flip-flops of the third frequency dividing circuit and outputs a level signal of a transmission waveform.

In the intermittent transmission circuit according to the present invention described above, when the switching signal indicates the standby mode, the second frequency dividing circuit and the third frequency dividing circuit are connected in series to form a time signal generating section. Then, a specific flip-flop among the plurality of flip-flops of the third frequency dividing circuit outputs a time signal to the control unit. On the other hand, when the switching signal indicates the transmission mode, the first frequency dividing circuit, the second frequency dividing circuit, the third frequency dividing circuit, the latch circuit, and the decoder circuit constitute a transmitting unit, and the decoding circuit Outputs a level signal of a transmission waveform.

As described above, the intermittent transmission circuit according to the present invention shares the frequency dividing circuit that constitutes the time signal generation unit and the transmission unit with respect to the above-described conventional intermittent transmission circuit, and realizes high utilization efficiency of circuit elements. ing.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The frequency dividing circuit 1 has a plurality of flip-flops FF and divides the clock signal CLK into a frequency dividing ratio corresponding to the data “1”.

The frequency dividing circuit 2 has a plurality of flip-flops FF, divides the clock signal CLK into a frequency dividing ratio corresponding to data “0”, and further generates a clock input C _L for latch input of the latch circuit 5. To do.

The latch circuit 5 latches the input signal V _i at the timing of the clock input C _L from the frequency dividing circuit 2.

The switching circuit 7 switches between the frequency dividing circuit 1 and the frequency dividing circuit 2 according to the contents of the latch circuit 5.

The output of the switching circuit 7, the clock input C _L from the frequency dividing circuit 2 is input to the switching circuit 4. The switching circuit 4
Selects one of the input signals according to the switching signal V _C from the control unit 6 and outputs it to the frequency dividing circuit 3, and at the same time, the switching circuit 7
If the output of is selected, it outputs the clock input C _L from the divider circuit 2 in the latch circuit 5.

The frequency dividing circuit 3 further divides the output of the frequency dividing circuit 2 in the standby mode to generate the time signal V _T. In the transmission mode, it operates as a counter and counts the output of the switching circuit 2.

The control unit 6 uses the time signal V _T output from the frequency dividing circuit 3 to switch the switching mode between the standby mode and the transmission mode.
_C is output to the switching circuit 4.

Therefore, switching circuit 4, when the switching signal V _C indicates the standby mode, to connect the dividing circuit 3 and the frequency divider circuit 2, when indicating the transmission mode, connects the divider circuit 2 and the latch circuit 5, The switching circuit 7 and the frequency dividing circuit 3 are connected.

The decoder 8 decodes the counter output of the frequency dividing circuit 3, weights the signal, and outputs the level signal V _L of the transmission signal.

Therefore, when the switching signal V _C indicates the standby mode, the frequency dividing circuit 2 and the frequency dividing circuit 3 are connected to operate as one frequency dividing circuit and configure the time signal generating unit 100 that outputs the time signal V _T. To do.

Further, a frequency divider circuit 1 when the switching signal V _C indicates a transmit mode, a frequency dividing circuit 2, a divider circuit 3, a switching circuit 4, the switching circuit 7, a latch circuit 5, Degoda 8 operation Then, the transmission signal generation unit 200 that outputs the level signal V _L of the transmission signal
Make up.

That is, the time signal generation unit 100 and the transmission signal generation unit 200 operate alternately according to the switching signal V _C , and the time signal generation unit 1
00 and the frequency dividing circuit 2 and frequency dividing circuit 3 forming the transmission signal generating section 200 are commonly used.

EFFECTS OF THE INVENTION As described above, according to the present invention, since the frequency dividing circuits forming the time signal generating section and the transmitting section that operate alternately are shared with each other, redundant circuits are eliminated and integrated circuits are integrated. It has the effect of increasing the degree.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of an intermittent transmission circuit according to the present invention, FIG. 2 is a block diagram of an intermittent transmission circuit according to a conventional technique, FIG. 3 is a waveform diagram of a switching signal V _C , and FIG. Is
It is a waveform diagram of each part in the transmission mode. (Main reference numbers) 1, 2, 3, 11, 12 ... Dividing circuit 4, 7, 16, 30 ... Switching circuit 5, 14 ... Latch circuit 6, 20 ... Control unit, 8, 15 ... Decoder 100, 100a Time signal generator 200 Transmit signal generator 200b Transmitter

Claims (1)

[Claims] 1. A first frequency dividing circuit having a plurality of flip-flops for receiving and dividing a clock signal, and a second frequency dividing circuit having a plurality of flip-flops for receiving and dividing the clock signal. A frequency dividing circuit, a third frequency dividing circuit having a plurality of flip-flops, a latch circuit for latching an input signal,
The output of a specific flip-flop of the plurality of flip-flops of the first frequency dividing circuit and the output of a specific flip-flop of the plurality of flip-flops of the second frequency dividing circuit are received, and To switch between the standby mode and the transmission mode by receiving the output of the first switching circuit that switches and outputs according to the output signal of the latch circuit and the output of a specific flip-flop of the plurality of flip-flops of the third frequency dividing circuit. A control unit for outputting a switching signal of
Receiving the output of a specific flip-flop of the plurality of flip-flops of the frequency dividing circuit and the output of the first switching circuit, the second frequency dividing circuit when the switching signal indicates the standby mode. Of the second switching circuit is output as a clock input to the third frequency dividing circuit, and when the switching signal indicates the transmission mode, the output of the second switching circuit is output to the third frequency dividing circuit as a clock input. Along with
A first switching circuit that supplies an output of a specific flip-flop of the plurality of flip-flops of the second frequency dividing circuit to the latch circuit as a latch signal, and a plurality of specific plurality of the third frequency dividing circuits. And a decoder circuit for decoding the output of the flip-flop and outputting the level signal of the transmission waveform. When the switching signal indicates the standby mode, the second frequency dividing circuit and the third frequency dividing circuit are provided. The frequency circuit is connected in series to form a time signal generator, and
When a specific flip-flop of the plurality of flip-flops of the frequency divider circuit outputs a time signal to the control unit, while the switching signal indicates the transmission mode, the first frequency divider circuit and the first frequency divider circuit 2. An intermittent transmission circuit characterized in that the frequency dividing circuit (2), the third frequency dividing circuit, the latch circuit and the decoder circuit constitute a transmitting section, and a level signal of a transmission waveform is outputted from the decoding circuit.