JPH0628044B2 - Data transfer system - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a memory access system of a microcomputer, and in particular, a plurality of instruction words or data words stored in consecutive memory addresses are stored in a microcomputer. The present invention relates to a data transfer system using a microprocessor having a structure for storing as a cache.

[Technical background of the invention]

Conventionally, a microcomputer (hereinafter simply referred to as CPU)
Accesses a memory for an instruction or data word,
It outputs the memory address where the target word is stored, and then writes or reads data. However, as the functions of the CPU have been improved, the address width and the data width have been increased to 16 to 32 bits, respectively, and it is necessary to assign these address bus and data bus to independent pins. This leads to an increase in the number. Therefore, many methods are used in which addresses and data are assigned to the same pin and used in a time-sharing manner (for example, 8086 manufactured by Intel Corporation).

By the way, since the cache memory in the CPU can be accessed at a higher speed than the external memory, there is a tendency to incorporate a large-capacity cache for data or instruction words.

FIG. 5 shows a configuration example for realizing the time division method described above. In the figure, 11 is a CPU, 12 is a memory, 13 is a buffer circuit, 14 is an address latch circuit,
ADB is address / data bus, DB is data bus, A
B is the address bus, R / W is the read / write mode line,
ALE is an address latch enable signal.

In the above configuration, when writing data,
As shown in the timing chart of FIG. 6, the CPU 11
Outputs a high ("H") level address latch enable signal ALE from the address latch circuit 14, and the address signal output from the CPU 11 is latched in the address latch circuit 14 via the address / data bus ADB. Next, when the write mode signal W becomes "H" level, the address signal latched by the address latch circuit 14 is transferred to the memory 1 via the address bus AB.
2, the predetermined address is set, and the CPU 11
The write data output from is written in the memory 12 via the address / data bus ADB, the buffer circuit 13 and the data bus DB.

On the other hand, when reading data, as shown in the timing chart of FIG.
The address latch enable signal ALE of "H" level is output from U11 to the address latch circuit 14, and the CPU
The address signal output from 11 is latched in the address latch circuit 14 via the address / data bus ADB. Next, when the read mode signal R becomes "H" level, the address signal latched by the address latch circuit 14 is supplied to the memory 12 via the address bus AB to set a predetermined address and is output from the memory 12. The read data to be read is read by the CPU 11 via the data bus DB, the buffer circuit 13, and the address / data bus ADB.

Here, as a characteristic of a program, it is known that data and instructions to be accessed are distributed within a relatively limited address space within a short time interval (access locality). , The data or instruction cache often corresponds to a continuous address space.

[Problems of background technology]

By the way, when the continuous address space is sequentially accessed to transfer data between the cache and the memory as described above, in the conventional memory access method that outputs the address for each data, the time for outputting the address is There is a drawback that the ratio of the total data transfer time becomes large. This is an obstacle to realizing high-speed data transfer.

[Object of the Invention]

The present invention has been made in view of the above circumstances,
The purpose is to provide a data transfer system capable of realizing high-speed data transfer.

[Outline of Invention]

That is, according to the present invention, in order to achieve the above object, a cache memory, a cache memory address counter that holds and counts up an address of the cache memory, an address / data multiplexer, and an external memory that is updated every data transfer. A plurality of external memory devices each having a CPU having an address counter, an address / data multiplexer, a memory address counter for holding and counting up a memory address, and a memory body, and an address / data multiplexer of the CPU and each external memory device. An address data bus is provided between the address and data multiplexers, and addresses and data of each external memory device are multiplexed and transferred in a time division manner, and an address is output on this address data bus. An address latch line indicating from the CPU to each external memory device, a read / write mode line indicating a data read or write state in each external memory device, and a data read or write from the CPU to each external memory device. An access request line indicating that a request has been generated, an access acceptance line indicating that the processing for the request has been completed from each of the external memory devices to the CPU, and an address output from each of the external memory devices to the CPU. The address request line for requesting constitutes a microprocessor.

When performing continuous data transfer of memory addresses between the cache memory and each external memory device,
Only the access start address of the memory body is output from the CPU to the external memory device, and the memory address for each data is not output. When accessing an address space that spans multiple external memory devices,
By requesting the output of an address from the external memory device to the CPU via the address request line at an address boundary between the external memory devices, the external memory address counter of the CPU outputs the address again to the next external memory device. , The external memory device is taken over.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 15 is a CPU, and this CPU 1
5 includes a cash memory address counter 16, an address / data multiplexer 17, and a cash memory 18.
Is built in. The cache memory address counter 16 and the cache memory 18 are connected by a cache address bus CAB, and the address / data multiplexer 17 and the cache memory 18 are connected by _a data bus DB _a . The external memory device 19 is composed of a memory address counter 20, an address / data multiplexer 21 and a memory main body 22. The memory main body 22 has an address / data multiplexer 21 by a data bus DB _b and a memory address counter 20 by an address bus AB. And are connected respectively. C above
The PU 15 and the memory device 19 have an address data bus AD
B, address latch line AL, read / write mode line R
/ W, access request line ACY and access acceptance line AC
Connected to each other by J.

The address / data multiplexers 17 and 21 are for transferring an address signal and a data signal in a time division manner. When the address latch line AL is in the "on" state ("H" level), the address data Bus AD
The address signal is output on B, and the data signal is output on the address data bus ADB in the other period. The direction in which these data are transferred is selected by the read / write mode line R / W.

Further, the cache memory address counter 16 holds the address of the cache memory to be accessed and is incremented so as to sequentially indicate the next address in accordance with the data transfer.

On the other hand, the memory address counter 20 has the address data bus A when the address latch line AL is in the "ON" state.
The signal on DB is latched as an address signal, and further incremented to indicate the next address in accordance with the data transfer.

The read / write mode line R / W indicates whether the mode is a write mode to the memory or a read mode from the memory. Here, the write mode is set to the “H” level and the read mode is set to the low level. These are represented by the (“L”) level.

Next, the operation of the above configuration will be described. First, the write operation to the memory is performed as shown in the timing chart of FIG. That is, the CPU 15
Address data bus ADB before writing data
The write address "A" is output to the above, the address latch line AL is set to the "ON" state, and the read address "C" of the cache memory 18 is set to the cache memory address counter 16. Further, the potential of the read / write mode line R / W is set to the “L” level to indicate the write mode. On the other hand, the memory device 19
Since the address latch line AL is in the "on" state,
The write address “A” on the address / data bus ADB is read into the memory address counter 20. CP
U15 turns off ("L" level) the address latch line AL after a lapse of a predetermined time.

Next, the CPU 15 outputs the data of the cache address “C” to the address / data bus ADB and turns on the access request line ACY to indicate that the write data is being output. At this time, the memory device 19
Writes the data on the address / data bus ADB to the memory address “A”, turns on the access acceptance line ACJ to indicate the end of the operation, and sets the memory address counter 20 to indicate the next address. Count up.

As a result, the CPU 15 receives “ON” on the access acceptance line ACJ and “OFF” on the access request line ACY.
Then, the cache memory address counter 16 is counted up. Then, the memory device 19 uses the access request line A
Upon reception of CY "off", the access acceptance line ACJ is turned "off" to complete one data transfer.

Next, it is shown that the CPU 15 outputs the data of the cache address "C + 1" to the address / data bus ADB, turns the access request line ACY "ON", and outputs the write data. Hereinafter, the above-described operation is repeated as many times as necessary to transfer data.

On the other hand, reading from the memory is performed as shown in the timing chart of FIG. First, the CPU 15
Sets the cache memory address counter 16, the memory address counter 20, and the read / write mode line R / W as in the case of writing to the memory. Next, CP
U15 sets the access request line ACY to "ON" in order to read the data from the memory. At this time, the memory device 19 reads the data of the memory address “A ′”,
The data is output on the address / data bus ADB, and the access acceptance line ACJ is turned on to indicate that the data is valid.

Next, the CPU 15 turns on the access acceptance line ACJ.
Is received, the data on the address / data bus ADB is written to the cache memory 18, and the access request line ACY
Is turned off, and the cache memory address counter 16 is counted up to indicate the next address. The memory device 19 receives “OFF” of the access request line ACY, turns “OFF” the access acceptance line ACJ, counts up the memory address counter 20, and ends one data transfer. Hereinafter, the above-described operation is repeated a necessary number of times to transfer data.

As described above, in the memory write operation and memory read operation, the data transfer is performed while the access request line ACY and the access acceptance line perform the handshake.

Therefore, in such a memory access type microprocessor, when data is transferred between the CPU and the memory,
Prior to data transfer, the access start address is transmitted to the memory device only once, and the memory device and the address counter in the CPU are configured to access the continuous address space. Therefore, when moving continuous data, It is not necessary to output the address of each data from the CPU every time. Therefore, only data is output onto the address / data bus, so that high-speed data transfer can be performed.

In addition to the above configuration, the CPU 15 is provided with an external memory address counter and an address request line (not shown). With such a configuration, the memory address to be transferred can be output even during the data transfer, and even if the data transfer is performed to the address space extending over different memory devices, the boundary is not generated. The address is output again and the memory device can be taken over.
That is, as shown in the timing chart of FIG.
Data transfer start address "A" is present in the memory device 19 _1, subsequent part of the address if the "A + 2" subsequent address exists in another memory device 19 _2, the memory device 19 ₁ of the final address "A + 1 "memory device 19 ₁ when it is in the address request line" turned on ". Thus, CPU 15 is "A + 2" to output the contents of the external memory address counter prior to outputting the data to be transferred to the address, its address is taken over by the memory device 19 _2.

Although the read / write mode line and the access request line are separated in the above embodiment, they are divided into the read request line and the write request line, and are configured to perform the handshake with the access acceptance line when reading and writing data, respectively. May be.

Further, the memory address counter 20 is configured to hold and count up all address bits, but in order to effectively use the page mode widely adopted in the dynamic RAM, the high-order bit of the address is set as a row address by the D address. A method may be used in which the RAM is loaded, only the lower address is held and counted up, and the column address is input to the D-RAM every data transfer.

〔The invention's effect〕

As described above, according to the present invention, it is possible to obtain a data transfer system capable of realizing high-speed data transfer.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining a data transfer system according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining a data writing operation to a memory in the data transfer system of FIG. 3, FIG. 3 is a timing chart for explaining a data read operation from a memory in the data transfer system of FIG. 1, and FIG. 4 is a timing chart when a plurality of memory devices are used in the data transfer system of FIG. 5 is a timing chart for explaining the operation of FIG. 5, FIG. 5 is a block diagram for explaining the conventional data transfer system, and FIG. 6 is for explaining the data writing operation to the memory in the data transfer system of FIG. 7 is a timing chart for the above, and FIG. 7 shows reading of data from the memory in the data transfer system shown in FIG. Is a timing chart for explaining the operation. 15 ... CPU, 16 ... Cash memory address counter, 17, 21 ... Address / data multiplexer, 1
8 ... Cash memory, 19 ... Memory device, 20 ... Memory address counter, 22 ... Memory main body, AL ... Address latch line, ADB ... Address / data bus, R / W ... Read / write mode line, ACY ... Access request line, AC
J: Access acceptance line.

Claims (1)

[Claims] 1. A CPU having a cache memory, a cache memory address counter for holding and counting up an address of the cache memory, an address data multiplexer, and an external memory address counter updated every data transfer, and an address data multiplexer. , A plurality of external memory devices each having a memory address counter for holding and counting up a memory address, and a memory main body, and provided between the address / data multiplexer of the CPU and the address / data multiplexer of each external memory device. The address data bus in which the address and data of the external memory device are multiplexed and transferred in a time division manner, and the fact that the address is output on this address data bus is shown from the CPU to each external memory device. A dress latch line, a read / write mode line indicating a data read or write state in each external memory device, and an access request line indicating a data read or write request from the CPU to each external memory device. An access acceptance line indicating that the processing for the request from each of the external memory devices to the CPU is completed, and an address request line for requesting the output of an address from the external memory device to the CPU. When the continuous memory address data transfer is performed between the cache memory and each external memory device, the CP
The access start address of the memory body is output from U to the external memory device, and the memory address for each data is not output.
When accessing an address space across a plurality of external memory devices, when the final address of the external memory device being accessed is reached, the address is output from this external memory device to the CPU via the address request line. Requesting to output the address again from the external memory address counter of the CPU onto the address / data bus, latch this address in the memory address counter of the next external memory device, and take over the external memory device. Characteristic data transfer system.