JPH0628302B2 - Semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor memory device in which a plurality of bit lines and a plurality of power supply lines are arranged in parallel by the same conductive layer.

Prior Art For example, in a MOS static RAM, the first
As shown in the figure, regular memory cells C ₀₀ , C ₀₁ , C ₁₀ ,
In addition to C ₁₁ , ..., 1 to 2 columns of redundant memory cells C _R0 , C _R1 , ... (1 column in the column direction in FIG. 1) are arranged along a row or a column. If a normal memory cell, such as C _00, is a defective cell, the bit line select signal BS
The ₀ selected and the redundant memory cell array redundant bit line select signal BS _R instead of are as repairing defective cells. Redundant memory cells have the same resistance as each memory cell.
It is composed of R ₁ and R ₂ , and transistors Q _{1 to} Q ₄ . Each memory cell C _R0 , C _R1 , C ₀₀ , C ₀₁ , C ₁₀ , C ₁₁ , ... Is 1
One word line WL ₀ , WL ₁ , ..., A pair of bit lines It is connected to two power supply lines V _CC and V _SS . this house,
The bit line and the power supply line V _SS are composed of the same conductive layer. That is, these bit line and power supply line are arranged adjacent to each other and in parallel. And with the high integration, the wiring intervals between them have become very close, and accordingly,
Short circuits between these lines due to defects in the manufacturing process are becoming non-negligible.

The pattern of the conventional semiconductor memory device is shown in FIG.
In FIG. 2, only the memory cell C ₀₀ is shown in detail, and the other memory cells are simply shown by word lines, bit lines,
Only the power lines are shown. Portions indicated by dots indicate impurity diffusion regions formed in the semiconductor substrate. For example, word lines WL ₀ and WL ₁ , power supply line V _CC , transistors Q ₁ and Q ₂
Gate electrode: 1st layer polysilicon, resistors R ₁ and R ₂ ; 2nd layer polysilicon, bit line Power supply line V _SS : Assume that it is composed of an aluminum layer. In FIG. 2,
Short circuit between bit lines, eg Short circuit between the redundant bit lines of the redundant column Can be relieved by using. But,
When the bit line and the power supply line V _SS are short-circuited, the bit line is pulled up to V _CC through the load, so V _CC to V _SS
DC current flows steadily to. This defect is a fatal defect that cannot be avoided even by using a redundant column, and has a great influence on the manufacturing yield. That is, since the bit line and the power supply line V _SS are arranged almost symmetrically with respect to the contact area determined by the design inside the cell, the distance between the bit line and the power supply line V _SS is narrow. And power line
There is a problem that a short circuit with V _SS is likely to occur.

OBJECT OF THE INVENTION The object of the present invention is to solve the above-mentioned problems in the conventional form.
The purpose of this is to prevent the short circuit between the signal line, for example, the bit line and the power supply line, thereby increasing the repair rate of defects due to the redundant circuit.

According to the present invention to achieve the above object, in a semiconductor memory device having a plurality of columns, each of the plurality of columns has a bit line pair to which a memory cell is connected, and the bit line pair. Between the two bit lines forming a line and a power supply line extending substantially parallel to the bit line and forming the same conductive layer as the bit line. The plurality of columns can be replaced with defective columns. A redundant column is provided, each potential of the bit lines is pulled up to a potential higher than the potential of the power supply line, and the distance between the bit line and the power supply line in each bit line pair is There is provided a semiconductor memory device characterized by being arranged so as to be wider than a space between adjacent bit lines.

Embodiment of the Invention An embodiment of the present invention will be described with reference to FIG.

In FIG. 3, the contact region CONT is the same as that in FIG. 2 from the design of the inside of the cell, but a signal line such as a bit line is used. Is separated from the power supply line V _SS and is brought closer to the other bit line BL ₁ by that amount. This allows the bit line Short circuit between bit line BL ₁ and It is possible to prevent a fatal short circuit between the power supply line V _SS and the power line. By arranging the bit line asymmetrically with respect to the contact region CONT in this way, the bit line and the power supply line are separated from each other, thereby preventing a fatal short circuit. That is, when there is a defect due to a short circuit between the signal lines, it is highly possible that the redundant memory cell can relieve the defect, and therefore the yield can be improved.

In this way, the distance B in FIG. 3 is the same as the distance B in FIG. 2 (B ′ = B), and the cell size is the same as the conventional one, and A ′> A. The short circuit between the bit line and the power supply line V _SS is hard to occur. Further, in this case, the chip size can be reduced by setting C '<C'.

The present invention can be applied not only to the MOS static RAM but also to other semiconductor devices.

EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to reduce the probability of occurrence of a fatal short circuit between the signal line and the power supply line.

Therefore, the probability of repairing a defect by the redundant circuit can be increased.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a general MOS static RAM,
FIG. 2 is a layout diagram showing a wiring pattern of a conventional semiconductor device, and FIG. 3 is a layout diagram showing a wiring pattern of a semiconductor device as an embodiment of the present invention. …… Signal line (bit line), V _SS …… Power supply line, C ₀₀ , C ₀₁ …… Memory cell, C _R0 , C
_R1 ... Redundant memory cell.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H01L 27/10 491 8225-4M (56) References JP-A-56-130886 (JP, A) Special features Kai 58-50770 (JP, A) JP 54-122984 (JP, A) JP 54-14690 (JP, A)

Claims (1)

[Claims] 1. A semiconductor memory device having a plurality of columns, wherein each of the plurality of columns has a bit line pair to which a memory cell is connected and between two bit lines forming the bit line pair. Each of the bit lines includes a power supply line that extends substantially parallel to the bit line and is formed of the same conductive layer as the bit line, and the plurality of columns includes a redundant column that can replace a defective column. Is pulled up to a potential higher than the potential of the power supply line, and the distance between the bit line and the power supply line in each bit line pair is wider than the distance between adjacent bit lines. A semiconductor memory device characterized in that the semiconductor memory device is arranged in.