JPH0744227B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a semiconductor memory device in which a plurality of bit line pairs to which normal memory cells are connected and a bit line between two bit line pairs are provided. From a normal memory cell group having a power supply line extending substantially in parallel, and a redundant memory cell replacing the defective normal memory cell when the normal memory cell is defective. And a redundant memory cell group, wherein at least the normal memory cell group is l1 <l2 <l3 l1: distance between two bit lines forming a bit line pair l2: bits Distance between line pairs l3: The relationship between the distance between the bit line and the power supply line is maintained to prevent the occurrence of a short circuit that causes great damage to the semiconductor memory device.

[Industrial application field]

The present invention relates to an improvement in a semiconductor memory device having a plurality of bit line pairs and a plurality of power supply lines formed in parallel using the same conductive layer.

[Conventional technology]

FIG. 2 is a circuit diagram of a main part of a normal semiconductor memory device.

In the figure, C ₀₀ , C ₀₁ , C ₁₀ , C ₁₁ are memory cells, and C _R0 , C _R1
Is a redundant memory cell, BL _R , ▲ ▼ _R , BL ₀ , ▲ ▼ ₀ , BL
₁ , ▲ ▼ ₁ is a bit line, WL ₀ , WL ₁ is a word line, V _CC is a positive power supply level, V _SS is a ground power supply level, DB and ▲
▼ data bus, BS _0, BS ₁ is the bit line selection signals, BS _R is redundant bit line selection signal, Q ₁ and Q ₂ transistor in driver memory cells, Q ₃ and Q ₄ Transfer
Gate transistor, R ₁ and R ₂ are resistors, N1, N2, N3, N4
Indicates a node, and P indicates a short-circuit current.

FIG. 3 is an explanatory plan view of an essential part showing the layout of the semiconductor memory device shown in FIG. 2, and the same symbols as those used in FIG. 2 represent the same parts or have the same meanings. To do.

In the figure, CT indicates an electrode contact portion.

As is apparent from FIGS. 2 and 3, since this semiconductor memory device includes redundant memory cells C _R0 , C _R1 etc., there is no defect in a normal memory cell, for example, memory cell C _00. in some cases, redundant memory associated with the redundancy bit line selection signal BS _R instead of the bit line selection signals BS _0, a memory cell associated with the bit lines BL ₀ and BL ₀ to the bit line BL _R and ▲ ▼ _R The semiconductor memory device can be repaired by replacing the cell.

FIG. 4 is an explanatory plan view of an essential part showing another conventional layout, and the same symbols as those used in FIGS. 2 and 3 represent the same parts or have the same meanings. .

This conventional example differs from the conventional example shown in FIGS. 2 and 3 in that two pairs of bit lines share one power supply line for supplying the ground-side power supply level V _SS . , For example,
Bit line BL ₀ and ▲ ▼ ₀ pair and bit line BL _R and ▲
▼ A power supply line for supplying the ground-side power supply level V _SS is shared between the _R pair.

In any of the above-described embodiments, since the bit line BL _{0 and the} like and the ground-side power supply level V _SS supply power supply line use the same conductive layer, they are formed adjacent to and parallel to each other. .

[Problems to be solved by the invention]

In recent years, the degree of integration of the semiconductor memory device as described above has been further increased, and therefore, the distance between the bit lines and the power supply lines has become extremely narrow, and the bit lines and the power supply lines are caused by the defects generated in the manufacturing process. There are increasing opportunities for shorts with wires.

As described with reference to FIGS. 2 and 3, if the memory cell C ₀₀ becomes a defective memory cell, the reason is that the bit line BL ₀ and the power supply line for supplying the ground side power supply level V _{SS are} supplied. In the case of a short circuit with, a short circuit current as indicated by arrow P in FIG. 2 flows.

In this case, as described above, the defective memory cell and all the other memory cells associated with the bit line to which the defective memory cell is connected are replaced with redundant memory cells that operate normally, so that the semiconductor memory device is replaced. It is possible to relieve,
Even if the provisional decree is taken, the short-circuit current P still continues to flow, so that the semiconductor memory device consumes a large amount of wasted current and in some cases is not practical. Such a problem is not limited to the conventional example shown in FIGS. 2 and 3, but is the same in the conventional example shown in FIG.

The present invention reduces the chances of short-circuiting between the bit line and the power supply line by appropriately selecting the spacing between the bit lines or the spacing between the bit line and the power supply line, thereby reducing the manufacturing yield of the semiconductor memory device. It aims to improve reliability.

[Means for solving problems]

The semiconductor memory device of the present invention comprises a plurality of bit lines to which memory cells are connected, and a power supply line extending substantially parallel to the bit lines between two pairs of bit lines. <L2 <l3 l1: Distance between two bit lines that make up a bit line pair l2: Distance between bit line pairs l3: Distance between bit line and power supply line is maintained.

[Action]

When a short circuit between wirings in a semiconductor memory device is redundantly repaired, when a short circuit occurs between two bit lines forming a bit line pair, one column including the bit line is replaced by a redundant memory It can be relieved by substituting one of the cell columns.

When there is a short circuit between the bit lines of the adjacent columns, it is possible to remedy it by replacing the shorted two columns with the two columns of the redundant memory cell columns. The device needs to have more redundant memory cell columns available.

When there is a short circuit between the bit line and the power supply line, even if the short-circuited bit line string is replaced with the redundant memory cell string, the short-circuit current continues to flow, and it is often impossible to relieve.

Therefore, in the semiconductor memory device, each wiring should be configured such that the short circuit probability decreases in the order between the bit lines forming the bit line pair, between the bit lines in the adjacent column, and between the bit line and the power supply line. Is effective in improving the manufacturing yield and reliability.

According to the means of the present invention, the probability of occurrence of a short circuit is greatest between two bit lines forming a bit line pair, then between the bit line pairs, and between the bit line and the power supply line. Is clearly the least.

〔Example〕

FIG. 1 is an explanatory plan view of an essential part showing a layout in one embodiment of the present invention. The same symbols as those used in FIGS. 2 to 4 represent the same parts or have the same meaning. I shall.

In the figure, l1 is the distance between the two bit lines that make up the bit line pair, l2 is the distance between the bit line pairs, and l3 is the distance between the bit line and the power supply line for supplying the ground side power level V _SS. Shows.

In the case of the present invention, the bit line and the power line are formed so as to maintain the relationship of l1 <l2 <l3, as described above. Incidentally, in this embodiment,
As can be seen, it will be appreciated that the biasing of the bit lines with respect to the electrode contact portion CT helps to obtain the required spacing.

With such a configuration, a short circuit will most often occur between two bit lines forming a bit line pair. In this case, if a memory cell for one column is replaced with a redundant memory cell, a semiconductor memory device is formed. Is relieved, and no unnecessary current consumption as described with reference to FIG. 2 flows. Also, a short circuit between bit line pairs is less than a short circuit between the bit lines, and even if a short circuit occurs, two columns of memory cells can be replaced by redundant memory cells. For example, the semiconductor memory device is relieved, and in this case as well, useless consumption current does not flow as in the above case. In addition, when a short circuit occurs between the bit line and the power supply line, the short circuit shown in FIGS.
The point that the short-circuit power supply P flows as described in the figure is the same as the conventional example, but the distance between the bit line and the power supply line
Since l3 is the widest, the chances are even less than the occurrence of a short circuit between the bit line pair.

〔The invention's effect〕

According to the present invention, in a semiconductor memory device, a plurality of bit line pairs to which regular memory cells are connected, and a power supply line extending substantially parallel to the bit lines between the two pairs of bit lines are provided. And a redundant memory cell group including a redundant memory cell that replaces the defective normal memory cell when the regular memory cell is defective. In a semiconductor device, at least the normal memory cell group has a distance between two bit lines forming a bit line pair as l1, a distance between bit line pairs as l2, and a distance between bit lines and power supply lines as a distance. Is set as l3, and the relationship of l1 <l2 <l3 is maintained.

By adopting such a configuration, it is less likely that the bit line and the power supply line are short-circuited. Therefore, even if the defective memory cell is replaced with the redundant memory cell, useless current consumption flows. After all, it is possible to reduce the occurrence of situations such as discarding the semiconductor memory device, and the number of short circuits between bit line pairs is smaller than that between conventional bit line pairs. It is also possible to reduce the occurrence of the situation in which the memory cells in the above need to be replaced with the redundant memory cells, and as a result, the manufacturing yield and reliability of the semiconductor memory device are improved.

[Brief description of drawings]

FIG. 1 is an explanatory plan view of a main part showing a layout of an embodiment of the present invention, FIG. 2 is a circuit diagram of a main part of a conventional example, and FIG. 3 is a main part plane showing a layout of the conventional example shown in FIG. FIG. 4 and FIG. 4 are main-portion plan views showing layouts of other conventional examples. In the figure, C ₀₀ , C ₀₁ , C ₁₀ , C ₁₁ are memory cells, C _R0 , C _R1
Is a redundant memory cell, BL _R , ▲ ▼ _R , BL ₀ , ▲ ▼ ₀ , BL
₁ , ▲ ▼ ₁ is a bit line, WL ₀ , WL ₁ is a word line, V _SS is a ground side power supply level, V _CC is a positive side power supply level, DB and ▲
▼ is a data bus, CT is an electrode contact portion, l1 is the distance between two bit lines that make up a bit line pair, l2 is the distance between bit line pairs, and l3 is the bit line and ground side power supply level V _SS supply The distances between the power supply lines are shown.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/11

Claims (1)

[Claims] 1. A regular memory cell comprising a plurality of bit line pairs to which regular memory cells are connected, and a power supply line extending substantially parallel to the bit lines between two pairs of bit line pairs. A semiconductor device comprising: a cell group; and a redundant memory cell group including a redundant memory cell that replaces the defective regular memory cell when the regular memory cell has a defect, At least the regular memory cell group has l1 <l2 <l3 l1: distance between two bit lines forming a bit line pair l2: distance between bit line pairs l3: distance between bit line and power line A semiconductor memory device characterized in that the relationship is maintained.