JPH0628341B2 - A-D converter - Google Patents

Description

The present invention relates to an AD converter, and more particularly to a fully parallel AD converter.

[Conventional technology]

The all-parallel A / D converter is usually constructed as a semiconductor integrated circuit. In the integration, if a large number of comparison circuit blocks are arranged in one column, the pattern becomes too long and thin, and therefore an arrangement method of folding back and dividing into a plurality of columns is adopted.

FIG. 3 is an explanatory diagram showing a planar arrangement of main blocks and wiring of an example of the conventional AD converter.

The conventional example shown in FIG. 3 is a 5-bit A / D converter with an input signal range of 0V to -2V, and has comparator circuits CM _{1 to} CM.
₃₂ , resistors R _{1 to} R _32, and an encoder (not shown).

The pad P _{0 to} which 0V is input, the resistors R _{1 to} R _32, and the pad P ₁ to which −2V is input are connected in series and arranged in a U-shape having the resistor R ₁₇ as the base. Two comparison circuit rows (comprising the comparison circuits CM _{1 to} CM ₁₆ or CM _{17 to} CM ₃₂ ) formed by folding back the rows of the comparison circuits CM _{1 to} CM ₃₂ at the central portion are arranged on both outsides of this resistance row. Has been done. The connection point between the resistance R _i (i is an integer of ₁ to 31) and the resistance R _{i + 1} is connected to the quantization level input terminal of the comparison circuit CM _i , and the connection point between the resistance R ₃₂ and the pad P ₁ is compared. Circuit CM ₃₂
It is connected to the quantization level input terminal of. Pad P ₀ ,
Two pads P for inputting the input signal V _{in on} both outsides of P _1.
in is arranged, and two buffer amplifier circuits A and two pads P _CL for inputting the clock signal CL to them are arranged on both outsides thereof. One input signal line L ₁ is laid out from each of the pads P _in so as to overlap one of the comparison circuit rows, and the input signal V _in is branched from these input signal lines L ₁ to generate an input signal V _{in. The} signals are sequentially input from ₁ to the comparison circuit CM ₁₆ and from the comparison circuit CM ₃₂ to the comparison circuit CM ₁₇ . The clock signal lines L ₂ are similarly wired one by one from the respective output ends of the buffer amplifier circuit A, and the clock signal CL is similarly inputted to each comparison circuit.

In the comparison circuits CM _{1 to} CM ₃₂ , 0 V to −2 V are resistors R ₁ to.
One of the 32 quantization levels divided by R ₃₂ and the input signal V _in are compared at the timing of the clock signal CL.
The encoder encodes the comparison result of each comparison circuit and outputs a 5-bit digital signal.

Since the speed at which the input signal V _in propagates through the input signal line L ₁ does not match the speed at which the clock signal CL propagates through the clock signal line L ₂ and the clock signal CL propagates through the clock signal line L ₂ , see FIG. In the conventional example shown, the comparison circuit CM ₁ C
There is almost no comparison timing error in M ₃₂ , and the comparison timing error gradually increases as it goes from the comparison circuit CM ₂ to the comparison circuit CM ₁₆ , and as it goes from the comparison circuit CM ₃₂ to the comparison circuit CM ₁₇ .

FIG. 4 is a graph for explaining the operation of the conventional example shown in FIG.

In Figure 1, an example of the curve represented by the solid line voltage waveform of the input signal V _in the conventional example shown in FIG. 3, a digital signal curve represented by the broken line output in response to the input signal V _in It is a voltage waveform of the signal which carried out D-A conversion.

Generally, the amplitude change of the input signal V _in is the central part of the amplitude (-1
Since the comparison timing error becomes maximum at (around V) and the comparison circuit that determines the digital signal corresponding to this portion (comparison circuits CM ₁₆ and CM ₁₇ whose quantization level is near the center) becomes maximum. The A-D conversion distortion (difference between the solid line and the broken line in FIG. 4) becomes large.

[Problems to be solved by the invention]

As described above, in the conventional AD converter, the input signal and the clock signal are sequentially input from the comparison circuit of the highest and lowest quantization levels to the comparison circuit of the central quantization level. Since the comparison timing error is maximized in the quantization level comparison circuit of, and the digital signal corresponding to the portion in which the amplitude change of the input signal is most abrupt is determined in the central quantization level comparison circuit, There is a drawback that the A-D conversion distortion becomes large.

An object of the present invention is to solve the above-mentioned drawbacks and to provide an AD converter having a small AD conversion distortion.

[Means for solving problems]

The AD converter of the present invention has a first resistance example in which a first electrode to which a first potential is applied is connected to one end, and a second resistance example to one end.
A second electrode connected to the second electrode to which the second electric potential is applied and extending in parallel with the first resistor string, and a second resistor string connected between the other end of each of the first and second resistor strings. A series of 3 resistors,
A first comparison circuit group connected to each connection point of the first resistance string and a second comparison circuit group connected to each connection point of the third resistance string.
An analog-to-digital converter and a clock signal are supplied to the first comparison circuit group from the third resistance string to the first electrode, An analog signal and a clock signal are supplied to the second comparison circuit group from the third resistor string toward the second electrode.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings illustrating an embodiment.

FIG. 1 is an explanatory diagram showing a planar arrangement of main blocks and wiring of an embodiment of an AD converter of the present invention.

The embodiment shown in FIG. 1 is a 5-bit A / D converter with an input signal range of 0V to -2V, and has comparator circuits CM _{1 to} CM.
₃₂ , resistors R _{1 to} R _32, and an encoder (not shown).

The structure and function of the embodiment shown in FIG. 1 are the same as those of the conventional example shown in FIG. 3 except for some differences in arrangement.

Pads P ₀ and P ₁ , resistors R _{1 to} R ₃₂ , and comparison circuits CM _{1 to} C
M ₃₂ and M ₃₂ are arranged and interconnected in the same manner as in the conventional example shown in FIG.

The pads P _in P _CL and the buffer amplification circuit A are adjacent to the end portions on the side of the comparison circuits CM ₁₆ and CM ₁₇ of the two comparison circuit rows, respectively, that is, in the conventional example shown in FIG. It is arranged at a target position for each of the comparison circuit rows.

The input signal line L ₁ and the clock signal line L ₂ are laid from the pad P _in and the buffer amplifier circuit A, and the input signal V _in and the clock signal CL are supplied from these signal lines to the comparison circuits CM _{1 to} CM ₃₂ , respectively. Is the same as in the conventional example shown in FIG. However, since the relationship between the direction of propagation of each signal and the direction of arrangement order of the comparison circuits in each comparison circuit column is opposite to that in the conventional example shown in FIG. 3, in the embodiment shown in FIG. There is almost no comparison timing error in the comparison circuits CM ₁₆ and CM ₁₇ , and the comparison timing error increases in sequence from the comparison circuit CM ₁₅ to the comparison circuit CM ₁ and from the comparison circuit CM ₁₈ to the comparison circuit CM ₃₂ . Become.

FIG. 2 is a graph for explaining the operation of the embodiment shown in FIG.

In Figure 2, an example of the curve represented by the solid line voltage waveform of the input signal V _in of the embodiment shown in FIG. 1, a digital signal curve represented by the broken line output in response to the input signal V _in It is a voltage waveform of the signal which carried out D-A conversion.

In the central part of the amplitude (around -1V) where the amplitude change of the input signal V _in becomes the most abrupt, the comparison circuits CM ₁₆ and CM ₁₇ determine the digital signal, and there is almost no comparison timing error in these comparison circuits, and the comparison timing is small. Since the amplitude of the input signal V _in that determines the digital signal by the comparator circuits CM ₁ and CM ₃₂ that maximize the error has a gentle amplitude change,
The AD conversion distortion of the embodiment shown in FIG. 1 is small.

The embodiment of the present invention has been described above in the case of the 5-bit A / D converter in which the comparison circuit is arranged to form two folded comparison circuit strings. It can be applied regardless of how many comparison circuit rows are folded back to form or arranged in one row, and regardless of the number of bits.

〔The invention's effect〕

As described in detail above, in the AD converter of the present invention, both the input signal and the clock signal are compared from the central quantization level comparison circuit to the higher quantization level comparison circuit and the lower quantization level comparison circuit. By sequentially supplying to, the comparison timing error in the comparison circuit of the central quantization level that determines the digital signal corresponding to the portion where the amplitude change of the input signal becomes the most abrupt,
There is an effect that the A-D conversion distortion is small.

[Brief description of drawings]

FIG. 1 is an explanatory view showing a planar arrangement of main blocks and wiring of one embodiment of an AD converter of the present invention, and FIG. 2 is for explaining the operation of the embodiment shown in FIG. FIG. 3 is an explanatory diagram showing a planar arrangement of main blocks and wiring of an example of a conventional AD converter, and FIG. 4 is a diagram for explaining the operation of the embodiment shown in FIG. Is a graph of. CM _{1 to} CM ₃₂ …… Comparison circuit, L ₁ …… Input signal line, L ₂ …
… Clock signal line.

Claims (1)

[Claims] 1. A first resistor string having a first electrode to which a first potential is applied is connected to one end, and a second electrode to which a second potential is applied is connected to one end. A second resistor string extending parallel to the first resistor string, a third resistor string connected between the other ends of the first and second resistor strings, and connection points of the first resistor string. In the AD converter having a first comparison circuit group connected to each other and a second comparison circuit group connected to each connection point of the second resistance string, On the other hand, an analog signal and a clock signal are supplied from the third resistor string to the first electrode, and the second signal is supplied to the second electrode.
For the comparator circuit group of
An analog-to-digital converter that supplies an analog signal and a clock signal to the electrodes of the.