JPH0628426B2 - Image display device drive circuit - Google Patents

Description

The present invention relates to a drive circuit for an image display device such as a liquid crystal matrix panel.

(B) Prior Art FIG. 3 is a diagram showing a drive circuit of a liquid crystal display device using an active matrix liquid crystal panel used in a liquid crystal TV device. Such a circuit is described in, for example, Japanese Patent Laid-Open No. 57-41078. ing.

In the figure, an active matrix type liquid crystal panel (1) has pixels in n columns in the x direction and m rows in the y direction.
T composed of × n amorphous silicon (a-si)
FT (thin film transistor) (1a) and liquid crystal electrode (1
b) are connected in a matrix as shown, and each row (G ₁ , G ₂ ... Gm) and each column (D ₁ , D ₂ ... Dn) is connected to a row driver (2) and a column driver (3), respectively. Has been done. The row driver is an m-stage shift register (2
a) and an output circuit (2b), and the column driver includes an n-stage shift register (3a), a sample hold circuit (3b), and an output circuit (3c). (4) is a synchronization control circuit, which is a horizontal synchronization signal (H
p) and the vertical synchronization signal (Vp) based on the first and second
A start pulse (ST ₁ ) (ST ₂ ) and first and second clock pulses (CP ₁ ) (CP ₂ ) are created.

FIG. 4 is a diagram showing each waveform of the row driver.
Represents a video signal, on which a vertical synchronizing signal (Vp) and a horizontal synchronizing signal (Hp) are superimposed. In the figure, T ₁ is a vertical synchronizing signal section, T ₂ is a vertical blanking section, and T ₃ is a video signal section.

The shift register (2a) has a first start pulse (ST ₁ ) synchronized with the vertical synchronizing signal shown in FIGS. 4 (b) and 4 (c).
And the first clock pulse (CP
₁ ) and each row G ₁ , G ₂ ... Has (d) (e)
As shown in (f), voltage waveforms shifted by 1H (one horizontal period) are applied. With this voltage waveform, the TFTs (1a) in each row are sequentially turned on in the horizontal blanking interval to apply the liquid crystal drive voltage to each pixel.

On the other hand, the waveform of each part of the column driver (3) is as shown in FIG. The column drive repeats the same operation in each 1H section. FIG. 5A shows a video signal drawn by extending the 1H section at T ₃ . In the figure, T ₄ is a horizontal synchronizing signal section and a horizontal blanking section, and T ₅ is a section containing video information.

The shift register (3a) has a second start pulse (ST ₂ ) synchronized with the horizontal synchronizing signal shown in FIGS.
And a second clock pulse having a frequency of its period τ = T ₅ / n is given, and the output of each stage of the shift register (3a) is sequentially incremented by τ as shown in (d), (e) and (f) of FIG. The staggered pulses are output. Sample and hold circuit (3
Each stage of b) is controlled by the output of the shift register of the corresponding stage, and the voltage value of the video signal is sampled by the fall of the output and held until the next sampling time (for 1 H). The output circuit (3c) receives the output of the sample-hold circuit, buffers and increases the width, and drives the column electrode.

When a failure such as a short circuit or a disconnection occurs in the liquid crystal panel and the drive circuit during the manufacturing process of the above liquid crystal display device, the shift register cannot generate the shift pulse in the line after the failure occurrence panel. The whole becomes inoperable and the yield is remarkably reduced.

(C) Problems to be Solved by the Invention The present invention has been made in view of the above-described points, and normally operates the panel even if a failure occurs in the matrix panel or the drive circuit to improve the yield. With the goal.

(D) Means for Solving the Problems The present invention provides a counter that counts clock pulses and derives a binary count value and its inverted output, and a counter output that is decoded to each row and / or each column. A decoder for generating a pulse that shifts in order in synchronization with the clock pulse, and supplies the counter output from both ends of a code signal line of the decoder.

(E) Operation By the above-mentioned means, even if a failure occurs on the code signal line of the decoder, the decoder operates normally because the counter output is supplied to the code signal line from both ends.

(F) Embodiment One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a drive circuit of a liquid crystal display device in the present embodiment. The same parts as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted.

In the figure, (50) is the first clock pulse (C) generated by the first start pulse (ST ₁ ) from the synchronization control circuit (4).
Start counting D ₁ ) and output binary count (A)
The first counters (51) and (51) that output (B) and the inverted output () () decode the output of the first counter, and output the first clock to the left and right of each row G ₁ , G ₂ ... A first decoder (60) that outputs a pulse that sequentially becomes high for each pulse (CP ₁ ), a (60) is a second start pulse (ST ₂ ) and a second clock pulse (CP ₂ ) from the synchronization control circuit (4). ), A second counter for outputting a binary count output, (61) (61) decodes the second counter output and outputs a second clock pulse (CP ₂ ) above and below each column D ₁ , D ₂ ... It is a second decoder that outputs pulses that sequentially become high every time. In this embodiment, the function corresponding to the conventional shift register is replaced with a binary counter and a decoder. Therefore, the row driver (5) is constituted by the first counter (50), the first decoder (51) and the output circuit (52), and the second count (60), the second decoder (61), the sample hold circuit (62). ) And the output circuit (63) form a column driver (6). Then, the first and second decoders
(51) (61), output circuit (52) (63) and sample hold circuit
(62) is formed of a-SiTFT on the same substrate as the liquid crystal panel (1) and in the same step.

FIG. 2 illustrates the operation of the row driver together with the specific circuit of the first decoder. Binary count outputs (A), (B) and their inverted outputs () () from the first counter (50)
, And the rows G ₁ , G _2, ... Cross each other in a matrix, and each row has two TFTs forming an AND gate.
Are arranged in series. Furthermore, each row has a load TFT
(T ₉ ) to (T ₁₂ ) are connected, and an output circuit (52) is connected to each output for each row.

Now, when the counter output is "00", both (A) and (B) are "0" and both () and () are "1", and the TFT
(T ₁ ) (T ₂ ) (T ₄ ) (T ₅ ) is turned on,
Only row (G ₁ ) is low. Next, when the counter output is "01" (A) and () are both "0" ()
Both (B) become "1" and TFT (T ₂ ) (T ₄ ) (T
₇ ) is turned on, causing row (G ₂ ) to go low. When the counter output is sequentially incremented in this way,
The next row is sequentially selected to be low and selected, and the output circuit in the next stage inverts and increases the width to drive the TFT in the liquid crystal panel of that row.

Then, when the driving of all the rows is completed and the first counter (50) is reset by the next start signal, the scanning of the next frame is started.

Although the decoder (51) and the output circuit (52) are shown only on the left side in FIG. 2, they are actually arranged symmetrically as shown in FIG. 1, and one row is driven by the same signal from the left and right. It

Therefore, even if the scanning line of the liquid crystal panel (1) is broken at one place, the signal is supplied from both sides of the line, so that the signal is supplied to the entire line and the display is completely performed. Further, when the scanning line and the signal line are short-circuited somewhere in the active matrix, the line defect can be changed into a point defect by cutting the portion at two places on the scanning line across the signal line.

Next, the case where a failure occurs on the decoder side will be described.
First, the code signal line from the counter and the AN of the decoder
When short-circuited with the D gate line, AND
If the line wiring of the gate is cut on both sides of the code signal line, the output from the other decoder does not cause a failure. Moreover, wherever the line of the AND gate is broken, the output of the other decoder can be used for compensation as described above.

Furthermore, even if a disconnection occurs on the code signal line of the decoder, the code signal is supplied from above and below the matrix so that the operation is not hindered.

Furthermore, if a disconnection occurs at two points on the code signal line, disconnect the output line of the output circuit corresponding to the AND gate line existing between the two points with a laser or the like to open the failure line and open the other decoder. It can be driven by the signal from.

As described above, the method of applying the code signal from above and below the matrix of the decoder is similar to the decoder (6
It is obvious that it can be applied to 1).

(G) Effect of the Invention As described above, according to the present invention, even if a failure occurs on the code signal line of the decoder during the manufacturing process of the drive circuit, the operation can be performed with almost no trouble and the yield is greatly improved. It becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a drive circuit of a liquid crystal display device according to an embodiment of the present invention, FIG. 2 is a concrete circuit diagram of a first decoder, FIG. 3 is a view showing a conventional drive circuit, and FIG. FIG. 5 is a main part waveform diagram of the row driver, and FIG. 5 is a main part waveform diagram of the column driver. (1) …… Liquid crystal panel, (4) …… Synchronous control circuit,
(2) (5) …… row driver, (3) (6) …… column driver, (51) (61) …… decoder, (52) (63) …… output circuit

Claims (1)

[Claims] 1. A drive circuit for an image display device, comprising: driving each pixel by selecting each row and each column of an active matrix panel in which a plurality of pixels are arranged in a matrix by a clock pulse of a predetermined frequency. , A counter that counts the clock pulse and derives a binary count value and an inverted output thereof, and decodes the counter output to generate a pulse that sequentially shifts in each row and / or each column in synchronization with the clock pulse A drive circuit for an image display device, comprising a decoder for driving the counter, and supplying the counter output from both ends of a code signal line of the decoder.