JPH0766252B2 - Image display device drive circuit - Google Patents

Description

The present invention relates to a drive circuit of an image display device such as a liquid crystal matrix panel.

(B) Prior Art FIG. 6 is a diagram showing a drive circuit of a liquid crystal display device using an active matrix liquid crystal panel used in a liquid crystal TV device. Such a circuit is described in, for example, Japanese Patent Laid-Open No. 57-41078. ing.

In the figure, an active matrix type liquid crystal panel (1) has pixels in n columns in the X direction and m rows in the Y direction.
× n TFT made of amorphous silicon (a-si)
(Thin film transistor) (1a) and liquid crystal electrode (1b) are connected in a matrix as shown in the drawing, and each row (G ₁ , G ₂ , ... G)
m) and each column (D ₁ , D ₂ ... Dn) is respectively a row driver (2)
And column driver (3). The row driver includes an m-stage shift register (2a) and an output circuit (2b), and the column driver includes an n-stage shift register (3a), a sample hold circuit (3b), and an output circuit (3).
c). (4) is a synchronous control circuit,
To create the first based on the horizontal synchronizing signal (Hp) and a vertical synchronizing signal (Vp), a second start pulse (S _T1) (S _T2) and the first and the second clock pulses (C _P1) (C _P2) .

FIG. 7 is a diagram showing each waveform of the row driver.
Represents a video signal, on which a vertical synchronizing signal (Vp) and a horizontal synchronizing signal (Hp) are superimposed. In the figure, T ₁ is a vertical synchronizing signal section, T ₂ is a vertical blanking section, and T ₃ is a video signal section.

The shift register (2a) is given the first start pulse (ST ₁ ) synchronized with the vertical synchronizing signal and the first clock pulse (CP ₁ ) synchronized with the flat synchronizing signal shown in FIGS. 7 (b) and (c). , The voltage waveforms shifted by 1H (one horizontal period) as shown in (d), (e), (f) are applied to the respective rows G ₁ , G _2, .... With this voltage waveform, TF of each row in the horizontal scanning section
The liquid crystal drive voltage is applied to each pixel by sequentially turning on T (1a).

On the other hand, the waveform of each part of the column driver (3) is as shown in FIG. The row drive repeats the same operation in each 1H section. FIG. 8A shows a video signal drawn by extending the 1H section at T ₃ . In the figure, T ₄ is a horizontal synchronizing signal section and a horizontal blanking section, and T ₅ is a section including video information.

The shift register (3a) is supplied with a second start pulse (ST ₂ ) synchronized with the horizontal synchronizing signal shown in FIGS. 8 (b) and (c) and a second clock pulse having a frequency of its period τ = T ₅ / n. , The output of each stage of the shift register (3a) is shown in FIG.
(E) As shown in (f), pulses sequentially shifted by τ are output. Each stage of the sample and hold circuit (3b) is controlled by the output of the shift register of the corresponding stage, and the voltage value of the video signal is sampled at the fall of the output and held until the next sampling time (for 1H). . The output circuit (3c) receives the output of the sample hold circuit, buffers and widens it, and drives the electrode.

The shift register in the above-mentioned drive circuit has the structure shown in FIG. 9, but the figure shows only one stage.
Since each transistor is sequentially switched by the clock (,), the delay time per transistor stage must be within / 4 of the clock cycle to operate. That is, since a transistor having a relatively high switching speed is required for the transistor, a transistor having a low switching speed such as a-Si TFT used in the liquid crystal panel (1) cannot be used.

(C) Problems to be Solved by the Invention The present invention has been made in view of the above points, and an object thereof is to use a transistor having a relatively slow switching speed in a part of a driving circuit.

(D) Means for Solving the Problems The present invention provides a counter that counts clock pulses to derive a binary count value and its inverted output, and decodes this counter output to each row and / or each column of a matrix panel. A drive circuit is configured with a decoder that generates pulses that are sequentially shifted in synchronization with the clock pulse.

(E) Action The above-mentioned means shortens the time required for switching the switching transistor in the drive circuit.

(F) Embodiment One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a drive circuit of a liquid crystal display device in the present embodiment, and the same parts in FIG.

In the figure, (50) is the first signal from the synchronization control circuit (4).
Start pulse (ST ₁ ) causes the first clock pulse (C
Starts counting P ₁ ) and outputs binary count (A)
It is a first counter that outputs (B) and reverse output () (). For example, Tokyo Sanyo IC: LC4520 and L
Composed of C4049B. (51) decodes the output of the first counter and outputs the first clock pulse (CP) to each row G ₁ , G ₂ ...
₁ ) A first decoder that outputs a pulse that goes high for each
(60) is a second counter that outputs a binary count output based on the second start pulse (ST ₂ ) and the second clock pulse (CP ₂ ) from the synchronous control circuit (4), and (61) is this second counter. 2 counter output is decoded and second is given to each column D ₁ , D ₂ ...
It is a second decoder that outputs a pulse that sequentially becomes high for each clock pulse (CP ₂ ). In this embodiment, the function corresponding to the conventional shift register is replaced with a binary counter and a decoder. Therefore, the row driver (5) is constituted by the first counter (50), the first decoder (51) and the output circuit (52), and the second counter (60), the second decoder (61) and the sample hold circuit (62). And output circuit (6
The column driver (6) is composed of 3). Then, the first and second decoders (51) (61) and the output circuit (52)
(63) and the sample and hold circuit (62) are formed on the same substrate as the liquid crystal panel (1) and in the same step by a-Si TFT.

FIG. 2 illustrates the operation of the row driver together with the specific circuit of the first decoder. Binary count outputs (A), (B) and their inverted outputs () from the first counter (50)
Each line in () and each row G ₁ , G ₂ ... Cross in a matrix, and two TFTs forming an AND gate are arranged in series in each row. Furthermore, the load TFT (T ₉ ) to (T
₁₂ ) is connected, and an output circuit (52) as shown in FIG. 3 is connected to each output for each row. Now, when the counter output is "00", both (A) and (B) are "0" ().
() Are "1" tori _{TFT (T 1) (T 2} ) (T 4) (T 5) is to become turned on, only the row (G ₁₎ becomes high. Next, when the counter output is "01", both (A) and () are "0" and both () and (B) are "1". TFT (T ₂ ) (T ₃ ) (T ₄ )
Row (G ₂ ) is high because (T ₇ ) is on. When the counter output is sequentially incremented in this way,
The next row becomes high one by one and is selected, and the TFT in the liquid crystal panel of that row is driven.

Then, when the driving of all the rows is completed and the first counter (50) is reset by the next start signal, the scanning of the next frame is started.

The first decoder (51) in FIG. 2 has TFTs (T ₁ ) to (T _1
Since it is an AND gate in which ₈ ) are arranged in series in each row, there are advantages such as a small number of wires and low power consumption, but there is a drawback that the drive voltage becomes high.

FIG. 4 shows another embodiment of the first decoder. First decoder of the present embodiment (51 ') is TFT (T ₁₎ ~ (T ₈₎ because that is the NAND gate arranged parallel to each row, the power consumption and the number of wires than in Figure 2 is slightly Although there are many, there is an advantage that the driving voltage is low.

Further, FIG. 5 shows another embodiment of the first decoder. The first decoder (51 ″) of this embodiment includes diodes (D ₁ ) to (D ₈ ).
Since the AND gates are arranged in parallel in each row, the power consumption is high, but the drive voltage is low and the number of wirings is small.

It should be noted that, in FIGS. 2, 4, and 5, the first decoder is shown only for four lines for simplification, but actually, the number of lines is about 240, so the number of digits of the counter Also increases. The second counter (60) and the second decoder (61) in the column driver (6) have basically the same configuration and operation as those of the row driver (5), and therefore, the illustration thereof is omitted. .

(G) Effect of the Invention As described above, according to the present invention, a part of the drive circuit can be configured by the switching transistors having the same structure on the same substrate as the switching transistors in the active matrix panel and in the same step, and thus the matrix panel The external circuit can be greatly simplified, and the number of connecting lines between the matrix panel and the external circuit and power consumption can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a drive circuit of an image display device in an embodiment of the present invention, FIG. 2 is a concrete circuit diagram of a first decoder, FIG. 3 is a concrete circuit diagram of an output circuit, and FIG. Is a diagram showing another embodiment of the first decoder, and FIG. 5 is a diagram showing still another embodiment of the first decoder. FIG. 6 is a schematic block diagram of a drive circuit of a conventional image display device, FIG. 7 is a waveform diagram of essential parts of a row driver, FIG. 8 is a waveform diagram of essential parts of a column driver, and FIG. 9 is a conventional shift register. It is a circuit diagram. (1) …… Liquid crystal panel, (4) …… Synchronous control circuit,
(2) (5) ... row driver, ((3) (6) ... column driver, (50) (60) ... first and second counters, (51)
(61) ...... first and second decoders, (52) (63) ... output circuit, (62) ... sample and hold circuit.

Claims (3)

[Claims] 1. A driving circuit for a pixel display device, comprising: driving each pixel by selecting each row and each column of an active matrix panel in which a plurality of pixels are arranged in a matrix form by a clock pulse of a predetermined frequency. , A counter that counts the clock pulse and derives a binary count value and its inverted output, and decodes the counter output to generate a pulse that sequentially shifts in each row and / or each column in synchronization with the clock pulse A driving circuit for an image display device comprising a decoder made of a thin film active element. 2. A drive circuit for an image display device according to claim 1, wherein a switching transistor in a thin film active element forming the decoder is formed as a thin film transistor on the same substrate as the active matrix panel. 3. The drive circuit for an image display device according to claim 2, wherein the switching transistor is formed in the same process as the active matrix panel.