JPH0630072B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a readable and writable semiconductor memory device having an address register built therein, and more particularly to a reaction counter memory device suitable for an arithmetic device for pipeline processing.

[Conventional technology]

Generally, in a readable and writable semiconductor memory device (hereinafter referred to as RAM) having an address register inside, a clock signal is used to update the address register.

FIG. 7 schematically shows the structure of a conventional RAM 1 of this type. 10 is a memory cell matrix, 11 is a column decoder, 12 is a row decoder, 13 is a column selector, 14 is an address register, and 15 is a sense amplifier. 1
6 is a write amplifier, ▲ ▼ is a write enable signal,
Di is write data, Do is a read nata, and CK is a clock signal.

In this way, the clock signal CK for the address register 14
In the RAM 1 which uses, it is convenient to synchronize the read and write operations with this clock signal CK.

FIGS. 8 (a) to 8 (f) show an example of a time chart in that case, in which the address input as shown in FIG. 8 (b) is sequentially applied to the address register 1 at the rising edge of the clock signal CK.
4 and the output of the address register 14 is sequentially switched to the address input in the dictionary in synchronization with the rising edge of the clock signal CK as shown in FIG. 8 (c). In this way, the output of the address register 14 (for example, the data output (read data) Do is output after a fixed time (so-called access time) after the confirmation of AD ₁ and the write enable signal ▲ ▼ is at the high level period). The data of the memory cell at address AD ₁ is read in. The data output is in
A valid period (for example, a high impedance state) is shown. When writing the data, the write enable signal ▲ ▼ is set to the low level after the output of the address register 14 is confirmed, and the write data Di input at that time corresponds to the address AD corresponding to the output of the address register 14. Written to memory cell ₁ .

FIG. 9 shows a case in which the RAM 1 shown in FIG. 7 is used to form an arithmetic system. In the figure, 21 is a register, and the address input AD input to the register 21 is synchronized with the clock signal CK. Then, the registers 21 are sequentially set in the register 21, and the set register output, that is, AD is then input to the arithmetic unit (ALU ₁ ) 22. The computing unit (ALU ₁ ) 22 computes the forehead address input AD, converts it into an address AD ′ corresponding to the memory cell of the RAM 1, and outputs the address AD ′ for accessing the RAM 1.

In this way, the data A at the address AD 'from the RAM 1
Is output, the data A is then transferred to the arithmetic unit (AL
U ₂ ) 3, and in the arithmetic unit (ALU ₂ ) 3,
The data A is transmitted from, for example, another arithmetic unit to the arithmetic unit (ALU
₂ ) The data A input to 3 is calculated and the data A
The calculation result of the data B and the data B is again written as data input to the RAM 1 at the address AD 'of the RAM 1, and the first data A is rewritten with the data of the calculation result. The RAM 1 operates in synchronization with the lock signal CK as described above, and the write enable signal ▲ when writing data.
▼ is set to low level.

FIG. 10 schematically shows a configuration of a RAM 4 having two read systems and one write system, that is, a so-called 2-port read and 1-port write RAM 4 capable of simultaneously reading data from two addresses in a common memory cell. Shows.

_A column decoder _A 41 and a row decoder _A 4 as a first read system, which are 40 and a memory cell matrix in the figure.
2, column selector _A 43, address register _A 44,
_A sense amplifier _A 45 is provided, while a column decoder _B 51, a row decoder _B 52, a column selector _B 53, an address register _B 54, and a sense amplifier _B 55 are provided as a second read system. Then, each read system operates similarly to the case of FIG. 7, and the clock signal CK
The data A and the data B corresponding to the address A and the address B which are sequentially fetched into the address registers 44 and 54 in synchronization with the rising edge of
During the high level period of ∘, the data are simultaneously output from the sense amplifiers 45 and 55, and the data A and the data B are simultaneously read.

Further, when the write enable signal ▲ ▼ is set to the low level after the output of the address register _A 44 is confirmed, the write data Di input to the write amplifier 46 at that time corresponds to the address A fetched in the address register _A 44. Is written to the memory cell.

FIG. 11 shows a case where the RAM 4 shown in FIG. 10 is used to form an arithmetic system. The data A read from the address A and the data B read from the address B are calculated by the arithmetic unit 6. Then, the operation result is written again in the address A, whereby the data at the address A is rewritten from the data A to the operation result data.

By the way, in constructing an arithmetic system using the RAM shown in FIG. 7 or FIG. 10, an intermediate register is provided in the arithmetic unit as means for significantly improving the arithmetic speed, and arithmetic operations of two or more stages are performed through the intermediate register. A so-called pipeline type arithmetic system in which the devices are sequentially connected is often performed.

FIG. 12 shows an example of a case where a pipeline system is constructed using the RAM 4 shown in FIG. 10 and a two-stage arithmetic unit. Data A read from address A and address B of the RAM 4 respectively. And the data B are input to the _first arithmetic unit (ALU ₁ ) 7 and are arithmetically operated. The arithmetic result f (DA, DB) is temporarily set in the register 8 and the data f (DA , D
B) is input to the _second arithmetic unit ALU ₂ ) 9 and a predetermined arithmetic operation is further performed, and the arithmetic result is data f ″ (DA, D
B) is again input to the address A of the RAM 4, and data writing (data rewriting) to the address A is performed.

The reason why the speed of arithmetic processing is improved by using such a pipeline system will be further explained. Generally, for example, when two arithmetic operations of f and f ″ are continued, the data A read from the address A _{1 is} assumed. ₁
If the operations f and f ″ for the data B ₁ read from the address B ₁ are performed in one arithmetic unit, the arithmetic unit completely completes these operations and the data A ₁ and B ₁ Final calculation result f ″ (DA
₁ until DB ₁ ) is output from the one computing unit.
One of it is impossible to enter the following data (for example, an address A data A ₂ is read from the ₂ and the address B ₂ data is read from the B ₂₎ to the computing unit, arithmetic processing is slow in such a way. Therefore, in the above pipeline system, the first and second arithmetic units ALU ₁ and ALU ₁
LU ₂ is provided, and data A is stored in the _first arithmetic unit ALU ₁ .
_{When the first} operation f for ₁ and B ₁ is completed, the first operation unit for the operation f becomes empty. Therefore, when the operation f for the data A ₁ and B ₁ is completed, the operation result f (DA ₁ , DB ₁ ) Is input to the _second arithmetic unit ALU ₂ of the second arithmetic f ″, and at the same time, the following data (for example, data A ₂ and data B ₂ ) is input to the first arithmetic unit ALU ₁ for the first arithmetic f. By doing so, the calculation process as a whole will be speeded up.

In the pipeline system shown in FIG. 12, the RAM 4 (see FIG. 10) of the 2-port read and 1-port write is used, and two data A and data B are read from the common RAM 4 and the first data is read. Although it is configured to be input to the arithmetic unit ALU ₁ , in constructing such a pipeline system, the data A read from the normal RAM 1 as shown in FIG.
For example, the data B read from another RAM can be input to the _first arithmetic unit ALU ₁ shown in FIG.

FIG. 13 is a time chart of the pipeline system shown in FIG. 12, in which the address A ₁ is _first selected from the first address input (that is, the address register A side) in synchronization with the rising edge of the clock signal CK. has been at the same time as the data a ₁ of the address a ₁ is read as DA ₁ as the data output a, the address a second address input (i.e. the address register B side) address B ₁ is selected from the data output B data B ₁ of B ₁ is DB
Read as ₁ . These data DA ₁ and DB ₁
Is input to the _first arithmetic unit ALU ₁ , the first arithmetic operation f is performed in the arithmetic unit ALU ₁ , and the operation result f (DA ₁ ,
It is output as DB ₁ ). The output f (DA ₁ , DB ₁ )
Is once set in the intermediate register, and in the next cycle, the second arithmetic unit ALU ₂ performs the second arithmetic operation f ″ on the basis of the data f (DA ₁ , DB ₁ ). One clock cycle later (at this time, the output of the address register has become the address A ₂ ), and the final operation result f ″ is output from the _second operation unit ALU _2.
(DA ₁ , DB ₁ ) is output, and the data f ″ (DA ₁ ,
DB ₁ ) is written to the RAM 4 again.

However, in this case, the data writing is performed to the address selected by the address register A (that is, the address A ₂ as described above in this case) when the write enable signal ▲ ▼ becomes low level in the clock cycle. It will be done a lot (first
(See the write address shown in FIG. 3K). Therefore, as it is, the data f ″ (DA ₁ , DB ₁ ) is the original address from which the data A ₁ is extracted, as in the pipeline system shown in FIG. It becomes impossible to write to A ₁ (rewrite the data of address A ₁ ).
That the data _{f "(DA 1, DB 1} ) to write to the address A ₁ of said original must be Yara enter the address A ₁ in the address register A side again, so that the next address A _2, The data from B ₂ , namely DA ₂ ,
The reading of the DB ₂ must be delayed one cycle,
There has been a problem that the operation speed of the pipeline system is reduced accordingly.

[Problems to be solved by the invention]

As described above, in the pipeline system shown in FIG. 12, when the conventional example, that is, the RAM shown in FIG. 7 or 10, is used, the calculation result f ″ (DA ₁ , DB ₁ ) is different from the original address from which the data A ₁ is read, that is, the read address A ₁ one cycle before, and the read address A _{2 in the} next cycle.
Will be written in. Therefore, the calculation result f ″ (DA
_1, DB ₁₎ In order to write to the address A ₁ of said original must enter the address A ₁ again, thus must delayed one cycle to read data from the next address A _2, This goes against the purpose of the pipeline system, which is to increase the calculation speed.

The present invention has been made to solve the above problems,
The final calculation result (corresponding to the above f ″ (DA ₁ , DB ₁ )) is rewritten (corresponding to the above address A ₁ ) to the original read address (corresponding to the above address A ₁ ) without reducing the calculation speed as described above. The data at the address A ₁ can be rewritten).

[Means for solving problems]

In order to solve such a problem, according to the present invention, a latch circuit for holding an output of a decoder for selecting a memory cell corresponding to an input address for at least one cycle is provided, and when the data is read, the decoder output is provided. According to the present invention, there is provided a semiconductor memory device, wherein the memory cell is selected, and when the data is written, the memory cell is selected by using the decoder output at the time of reading at least one cycle before held in the latch circuit. It

[Action]

According to the above configuration, the write address is delayed from the read address by the predetermined number of cycles by the means for holding the signal for memory selection corresponding to the input address for the predetermined cycle even after the next input address is input. Therefore, the final calculation result can be rewritten to the first read address to rewrite (update) the data at the address, and the calculation speed is not reduced.

〔Example〕

FIG. 1 shows a semiconductor memory device as one embodiment of the present invention. The difference from the conventional RAM 1 shown in FIG. 7 is that a register 17 is provided between a row decoder 12 and a memory cell matrix 10. This is the point that is inserted. A means for holding a signal for memory selection corresponding to the input address (output signal of the row decoder 12) in the register 17 for a predetermined cycle even after the next input address is input (for example, a latch circuit, D Flip-flop etc.)
Is provided so that data is written to the previously input address by the predetermined cycle.

FIG. 2 shows a specific example of the portion of the register 17 in the device of FIG. 1, and the output from the first decoder 121 in the row decoder 12 is the first of the memory cells 10 via the inverter 175. While being input to the read word line RWL ₁ , the output from the decoder 121 is
It is input to the OR circuit 1761 via the latch circuits 171, 172, and the output of the OR circuit 1761 is further input to the _first write word line WWL ₁ of the memory cell 10 via the inverter 1762. The OR circuit 17
A write enable signal ▲ ▼ is also input to 61.

Similarly, the output from the second decoder 122 in the row decoder 12 is input to the _second read word line RWL ₂ of the memory cell 10 via the inverter 177, and the output from the decoder 122 is also output from the latch circuit 17.
3, 174 to the OR circuit 1781, and the output of the OR circuit 1781 is further passed through the inverter 1782 to the second write word line WW of the memory cell 10.
Input to L ₂ . The write enable signal ▲ ▼ is also input to the OR circuit 1781.

In the same manner, the input circuit for each word line is constructed through the register 17. The clock signal CK
Is supplied to each row decoder and each latch circuit.

FIG. 3 is a time chart of the semiconductor memory device shown in FIGS. 1 and 2, in which the address input as shown in FIG. 1 (a) (b) is generated at the rising edge of the clock signal CK. The signals are sequentially taken into the address register 14, and the output of the address register 14 is sequentially switched to the address input at that time in synchronization with the rising edge of the clock signal CK as shown in (c) of FIG. 3 (a). To be In this way, the data output (read data) D ₁ is output after a fixed time (so-called access time) after the output of the address register 14 (for example, A ₁ ) is determined, and the write enable signal ▲ ▼ is in the high level period. The address A ₁
The data is read from. In the decoder (decoder 121 in this case) whose address has been selected, its output signal becomes low level, and the low level signal is made into a high level signal by the inverter 175 to select the read word line RWL _1. To be done. (See (e) in FIG. 3 (a) and (d) in FIG. 3 (b)) On the other hand, the low-level output signal from the decoder 121 is taken into the latch circuit 171, and the next clock signal CK
Then, the contents of the latch circuit 171 are transferred to the latch circuit 172 and shifted by one cycle. That is, these latch circuits form a shift register. The third
Latch output A in FIG. 6B indicates the output of the latch circuit 171, and latch output B indicates the output of the latch circuit 172. Then, in this cycle, while the latch output B is at the low level, the write enable signal ▲ ▼
Becomes low level, the output of the OR circuit 1761 to which the low-level latch output B and the write enable signal ▲ ▼ are input becomes low level, and then the inverter 1
A high-level signal is output by 762, and the write word line WWL ₁ is selected after shifting by one cycle from the data read. (Fig. 3 (a) (f) and Fig. 3
(See (e) of (b)). Therefore, the write data D' ₁ ^' input at that time is written to the address A ₁ corresponding to the write word line WWL ₁ .

In the above example, the latch circuits 171 and 172 are used as means for shifting the output signal from the row decoder, but they can be replaced with D flip-flops. In the example shown in FIG. 3, after the write word line WWL ₁ is selected, the output from the row decoder specifies the write word line WWL ₂ by the same operation as above in the next cycle.
In this cycle, write enable signal ▲ ▼
Is not set to the low level, the write word line WW
The input to L ₂ is never set to the high level (see (i) in FIG. 3 (b)), and when the write enable signal becomes the low level again in the next cycle, the write word line WWL ₃ is set. when a high-level selection signal against the writing of the inputted data corresponding to the cell ▲ D _^'3 ▼ performed is shown. (See FIG. 3 (a) (h) and FIG. 3 (b) (j)).

Therefore, the semiconductor memory device (RAM) shown in FIGS. 1 and 2 is used, and the pipeline system described above is configured by using the data A read from the RAM and the data B read from another RAM or the like. Then, the final calculation result f ″ (DA, DB) can be rewritten to the original address A from which the data A was read.

FIG. 4 shows another specific example of the register portion 17 in the device shown in FIG. ₁ , which is largely applied to the memory cell 10 in which common word lines WL ₁ , WL ₂ ... Are used for reading and writing. The case is shown.

In the structure shown in the figure, if the decoder 121 is selected, the low-level output from the decoder 121 is transmitted to the transmission gate 1791 (clock signal ▲
▼ is input to the word line WL ₁ as a high level signal through a P-channel transistor and an N-channel transistor to which the clock signal CK is input) and the inverter 1795, and the clock signal CK and the write enable signal ▲ ▼ are input. In the high level period, data is read from the memory cell corresponding to the word line WL ₁ .

On the other hand, the low level output from the decoder 121 is shifted by one cycle through the latch circuits 171 and 172 (which can also be a D flip-flop), the OR gate 1761 (the write enable signal ▲ ▼ is also input to the OR gate 1761), the transmission gate 1792. (Consisting of a P-channel transistor to which the clock signal CK is input and an N-channel transistor to which the clock signal ▲ ▼ is input), and input as a high level signal to the word line WL ₁ through an inverter 1795. While the write enable signal ▲ ▼ is at the low level, the word line WL ₁
Data is written to the memory cell corresponding to.

FIG. 5 shows a semiconductor memory device as another embodiment of the present invention. It is a conventional type shown in FIG. 10, that is, a read system has two systems and a write system has one system RAM (that is, two-port read). Although it belongs to the 1-port write type RAM), the difference from the conventional type shown in FIG. 10 is that a register 47 (a specific configuration thereof is described above) between the row decoder _A 42 and the memory cell matrix 40. 2 or 4) is inserted, so that the first read system (that is, address A) is inserted.
Side) and the second read system (that is, the address B side), the data A and the data B are simultaneously read, and the data D is provided by providing the register 47.
Writing i is delayed by a predetermined cycle (one cycle in the case of the configuration of FIG. 2 or FIG. 4) and the data A is written to the original address A from which it was read.

FIG. 6 is a time chart when the apparatus shown in FIG. 5 is applied to the pipeline system shown in FIG. 12. The time chart shown in FIG. The difference from the time chart when the conventional apparatus shown in FIG. 12 is applied to the pipeline system shown in FIG. 12 is that the apparatus of the present invention shown in FIG. 5 is the same as that shown in FIG. 2 or 4. By including the register 47, the output data f ″ (DA ₁ , DB ₁ ) from the _second arithmetic unit (ALU ₂ ) 9 in FIG.
The data A is inputted (written by) a write address is to become read address A ₁ of the read address A ₁ of the data A ₁ (see FIG. 6 K), in this way
_At the original address A ₁ from which ₁ was read, the output data f ″ (D
A ₁ , DB ₁ ) can be written, and the above-mentioned pipeline system can be directly applied.

In each of the above-described embodiments, the number of latch circuits (or D flip-flops) in the register is set to shift the write address by one cycle so that the so-called arithmetic unit can be adapted to a pipeline system having two stages. However, it is needless to say that the number of the latch circuits (or D flip-flops) is set to three or more according to the number of stages of the arithmetic unit in the pipeline system, whereby the write address can be shifted by a predetermined cycle. Nor.

〔The invention's effect〕

According to the semiconductor memory device of the present invention, data can be written to an address input by a predetermined cycle before that cycle. Therefore, when this is applied to a pipeline system, the operation speed is particularly high. The final operation result can be rewritten to the original read address without lowering the value, and thus an efficient pipeline system can be configured. Moreover, according to the present invention, since the output of the decoder is held for at least one cycle, the memory cell can be selected by the decoder output at least one cycle before even if no address is input at the time of writing data. .

[Brief description of drawings]

1 is a block diagram showing one embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram showing one specific example of a register portion in the device of FIG. 1, and FIG. 3 is FIG. FIG. 4 is a timing diagram for explaining the operation of the device shown in FIG. 2, FIG. 4 is a circuit diagram showing another specific example of the register portion in the device shown in FIG. 1, and FIG. 5 is a semiconductor memory according to the present invention. FIG. 6 is a block diagram showing another embodiment of the apparatus, FIG. 6 is a timing chart for explaining the operation when the apparatus of FIG. 5 is applied to the pipeline system shown in FIG. 12, and FIG. 8 is a block diagram showing an example of a semiconductor memory device in FIG. 8, FIG. 8 is a timing chart for explaining the operation of the device of FIG. 7, and FIG. 9 is an arithmetic system using the conventional device shown in FIG. FIG. 10 is a block diagram showing the configuration of FIG. 11 is a block diagram showing another example of a semiconductor memory device in the art, FIG. 11 is a block diagram showing the configuration of an arithmetic system using the conventional device shown in FIG. 10, and FIG. 12 is a pipeline system. FIG. 13 is a block diagram showing the configuration of the adopted computing system, and FIG. 13 shows the conventional type device shown in FIG.
It is a timing chart explaining operation | movement at the time of applying to the pipeline system shown by a figure. (Description of symbols) 1 ... RAM 10 ... Memory cell matrix 11 ... Column decoder 12 ... Row decoder 14 ... Address register 17 ... Register 171,172,173,174 ... Latch (or D flip-flop) 22, 3 ... Operation unit, 4 ... RAM having two read systems, 40 ... Memory cell matrix 41, 51 ... Column decoder 42, 52 ... Row decoder 44, 54 ... Address register 47 ... Register 6,7,9 ... Calculator

Claims (1)

[Claims] 1. A latch circuit for holding an output of a decoder for selecting a memory cell corresponding to an input address for at least one cycle is provided. When data is read, the memory cell is selected by the decoder output, and when data is written. The semiconductor memory device is characterized in that the memory cell is selected using the decoder output at the time of reading at least one cycle before, which is held in the latch circuit.