JPH0630308B2 - Memory type negative feedback power supply - Google Patents
Memory type negative feedback power supplyInfo
- Publication number
- JPH0630308B2 JPH0630308B2 JP1260088A JP1260088A JPH0630308B2 JP H0630308 B2 JPH0630308 B2 JP H0630308B2 JP 1260088 A JP1260088 A JP 1260088A JP 1260088 A JP1260088 A JP 1260088A JP H0630308 B2 JPH0630308 B2 JP H0630308B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- power supply
- sine wave
- negative feedback
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000015654 memory Effects 0.000 title claims description 13
- 230000003111 delayed effect Effects 0.000 claims description 8
- 238000001514 detection method Methods 0.000 claims description 2
- 238000004804 winding Methods 0.000 description 54
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical group [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 32
- 238000012360 testing method Methods 0.000 description 20
- 230000004907 flux Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 230000010355 oscillation Effects 0.000 description 7
- 230000003321 amplification Effects 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 230000005415 magnetization Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- 229910000976 Electrical steel Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Landscapes
- Control Of Voltage And Current In General (AREA)
- Measuring Magnetic Variables (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、負荷に電流を供給するための記憶方式負帰還
電源装置に関し、たとえば、トロイダル鉄心、カットコ
ア型鉄心等の鉄心の交流磁化特性の試験を行う鉄心試験
装置、整流回路負荷の電源装置、歪電流負荷用電源装置
等に用いられる。Description: TECHNICAL FIELD The present invention relates to a memory type negative feedback power supply device for supplying a current to a load, for example, an alternating current magnetization characteristic of an iron core such as a toroidal core or a cut core type iron core. It is used for an iron core testing device for conducting the test of, a power supply device for a rectifier circuit load, a power supply device for a strain current load, and the like.
大量のトロイダル鉄心等の鉄心の励磁電流、渦電流損お
よびヒステリシス損の鉄損の交流磁化特性の試験を行う
ために、試験を行う毎に鉄心に巻線を施こす必要があ
る。つまり、第7図に示すごとく、鉄心1に1次巻線W
1および2次巻線W2を巻付け、試験が終了するとこれ
らの巻線を巻きほぐす。このような複雑な巻線作業を省
略するために、第7図に示すコネクタ状接点CW1,CW2に
よって巻線W1,W2の脱着を容易とする方法を想定す
ることができる。しかし、実際の変圧器等の設計におい
ては、本来、巻線の太さを可能な限り大きくして巻線直
流抵抗を小さくし且つ巻線数も通常非常に多く巻いてい
るので、電流も少なく、巻線抵抗成分による電圧低下及
び発熱は充分小さいが、第7図の場合、コネクタ状接点
CW1,CW2の配置空間に限度があるので、巻線太さは小さ
く且つ巻線数は少ないものとなってしまう。この結果、
1次巻線に流す試験用励磁電流を大きくしなければなら
ず、しかも、巻線および接点の抵抗の影響を強く受ける
ことになる。なお、第6図において、コネクタ接点CW1,
CW2の上下の接点は、鉄心挿入時は離れ、試験(測定)
時は接触させることにより、鉄心の巻線作業は不要とな
る。In order to test the alternating current magnetization characteristics of the exciting current, eddy current loss and hysteresis loss of a large number of toroidal iron cores, it is necessary to apply windings to the iron core each time the test is performed. That is, as shown in FIG. 7, the primary winding W is attached to the iron core 1.
1 and secondary winding W 2 of the winding, loosen winding these windings when the test is completed. In order to omit such complicated winding work, it is possible to envisage a method of facilitating the attachment / detachment of the windings W 1 , W 2 by means of the connector-shaped contacts CW 1 , CW 2 shown in FIG. 7. However, in the actual design of a transformer, etc., originally, the thickness of the winding is made as large as possible to reduce the DC resistance of the winding and the number of windings is usually very large. , The voltage drop and heat generation due to the winding resistance component are sufficiently small, but in the case of FIG.
Since the arrangement space of CW 1 and CW 2 is limited, the winding thickness is small and the number of windings is small. As a result,
The test exciting current flowing through the primary winding must be increased, and it is strongly affected by the resistance of the winding and the contacts. Incidentally, in FIG. 6, the connector contact CW 1 ,
The upper and lower contacts of CW 2 are separated when the iron core is inserted and tested (measured)
By making them contact with each other, the work of winding the iron core becomes unnecessary.
第7図の試験巻線を有するトロイダル鉄心の試験装置
は、従来、1次巻線W1に入力交流電源および交流電流
計を接続し、2次巻線W2に交流電圧計を接続し、1次
巻線W1と2次巻線W2との間に電力計を接続し、これ
により、鉄心の交流磁化特性試験の1つである飽和磁束
密度付近の1次電流Ipの測定およびそれにもとづく鉄
損の測定を行う。なお、鉄損の測定は電力計で行う。The toroidal iron core test apparatus having the test winding shown in FIG. 7 is conventionally connected to the primary winding W 1 with an input AC power source and an AC ammeter, and to the secondary winding W 2 with an AC voltmeter. A power meter is connected between the primary winding W 1 and the secondary winding W 2 to measure the primary current I p near the saturation magnetic flux density, which is one of the AC magnetization characteristic tests of the iron core. The iron loss is measured based on it. The iron loss is measured with a power meter.
しかしながら、たとえば、1次巻線W1の等価直流抵抗
は励磁電流Ipによる発熱に伴って変動し、コネクタ接
点CW1の接触直流抵抗はコネクタ接点CW1の状態に応じて
変動して不安定であり、1次巻線W1の等価交流抵抗も
鉄心の飽和特性によって変化する。従って、2次巻線W
2に発生する出力電圧Esは大きく変動する。さらに、
鉄心の飽和磁束密度付近では、交流1サイクル中に局部
的に発生する異常電流による瞬間的な1次巻線W1の等
価交流抵抗の低下があり、このため、2次巻線W2に発
生する出力電圧Esの波形は大きく歪む。これらの変動
及び歪みは、鉄心中の磁束が変動し、歪むことであり、
本来は一定した正しい交流磁束であるべき鉄心の試験と
しては極めて不具合である。このため、2次巻線W2の
出力電圧Esを一定にすべく、鉄心毎に交流電源の電圧
を調整して2次巻線W2に発生する電圧Esを修正して
も、磁束波形すなわち出力電圧Esに歪みが残存し、こ
れに伴って、励磁電流Ipのピーク電流部分が抑制さ
れ、正しい測定が不可能であった。However, for example, the equivalent DC resistance of the primary winding W 1 varies with the heat generated by the excitation current I p, the contact DC resistance of the connector contacts CW 1 is unstable and varies depending on the state of the connector contacts CW 1 Therefore, the equivalent AC resistance of the primary winding W 1 also changes depending on the saturation characteristics of the iron core. Therefore, the secondary winding W
The output voltage E s generated at 2 fluctuates greatly. further,
In the vicinity of the saturation magnetic flux density of the iron core, there is instantaneous primary winding W decrease in the equivalent AC resistance of 1 due to abnormal current locally generated in the AC cycle, Therefore, generated in the secondary winding W 2 The waveform of the output voltage E s is significantly distorted. These fluctuations and distortions are that the magnetic flux in the iron core fluctuates and is distorted.
This is an extremely defective test for an iron core, which should have a constant and correct AC magnetic flux. Therefore, even if the voltage E s generated in the secondary winding W 2 is corrected by adjusting the voltage of the AC power supply for each iron core so that the output voltage E s of the secondary winding W 2 is constant, Distortion remains in the waveform, that is, the output voltage E s , and along with this, the peak current portion of the exciting current I p is suppressed, and correct measurement is impossible.
このため、本願出願人は、既に、2次巻線W2の出力電
圧Esの一部を1次巻線W1側にアナログ式に負帰還さ
せ、これにより、出力電圧Esを安定させることを提案
している(参照:特願昭62-018625号)。すなわち、第
8図,第9図(第8図の等価回路図)に示すように、1
次巻線W1に入力交流電源2および交流電流計3を接続
し、2次巻線W2の両端に交流電圧計4を接続し、1次
巻線W1と2次巻線W2との間に電力計Wを接続し、さ
らに差動増幅器5、帰還抵抗6、および位相調整回路7
よりなる負帰還ループが設けられている。ここで、負帰
還ループがないときの入力交流電源2の入力電圧と出力
電圧Esとの比を全体増幅率A′とすれば、 A′=100〜20 と大きく変動すると仮定する。次に、帰還回路を考慮し
た場合、帰還抵抗6により帰還率Fを0.99に設定する
と、出力電圧Esは、 と表わさせるので(E1は交流電源2の電圧であり、こ
の場合は1Vとする)、 となる。このように、出力電圧Esの変動は小さくな
る。従って、コネクタ接点CW1による等価直流抵抗値R
p、1次巻線W1の等価交流抵抗値Rzpおよび直流抵抗
値Rcが変動しても、入力交流電圧の調整はほとんど不
要であり、この結果、鉄心1中の磁束波形すなわち出力
電圧Esの歪みも第9図に示すごとく少なくなる。な
お、増幅器5の増幅率をより大きくして帰還率Fを大き
くすれば、出力電圧Esの安定度が改善できるが、帰還
率Fを大きくとると、巻線の漏れリアクタンス等の影響
で発振現象が起こるのが普通であり、これは位相調整回
路7の抵抗および/またはキャパシタを調整することに
よりある程度防止できる。Therefore, the applicant has already negatively fed back a part of the output voltage E s of the secondary winding W 2 to the primary winding W 1 side in an analog manner, thereby stabilizing the output voltage E s . (See Japanese Patent Application No. 62-018625). That is, as shown in FIGS. 8 and 9 (equivalent circuit diagram of FIG. 8), 1
Connect the winding W input AC power source 2 and the AC ammeter 3 to 1, to connect the secondary winding W across the AC voltmeter 4 2, primary winding W 1 and secondary winding W 2 A power meter W is connected between the differential amplifier 5, the differential amplifier 5, the feedback resistor 6, and the phase adjusting circuit 7.
A negative feedback loop consisting of Here, assuming that the ratio of the input voltage of the input AC power supply 2 and the output voltage E s when there is no negative feedback loop is the overall amplification factor A ′, it is assumed that A ′ = 100 to 20 and a large variation occurs. Next, considering the feedback circuit, when the feedback ratio F is set to 0.99 by the feedback resistor 6, the output voltage E s becomes (E 1 is the voltage of the AC power supply 2, which is 1 V in this case), Becomes In this way, the fluctuation of the output voltage E s becomes small. Therefore, the equivalent DC resistance value R due to the connector contact CW 1
p , even if the equivalent AC resistance value R zp and the DC resistance value R c of the primary winding W 1 fluctuate, almost no adjustment of the input AC voltage is required. As a result, the magnetic flux waveform in the iron core 1, that is, the output voltage. The distortion of E s also decreases as shown in FIG. The stability of the output voltage E s can be improved by increasing the amplification factor of the amplifier 5 to increase the feedback factor F. However, when the feedback factor F is increased, oscillation occurs due to the influence of leakage reactance of the winding. A phenomenon usually occurs, which can be prevented to some extent by adjusting the resistance and / or the capacitor of the phase adjustment circuit 7.
しかしながら、第8図におけるアナログ式負帰還方式の
装置では、たとえば方向性珪素鋼板製鉄心で、磁束密度
が17000ガウス程度迄は充分実用上の精度が確保できる
が、磁束密度が飽和に近い、たとえば18000〜20000ガウ
スで極端な歪み電流波を流して、しかも高度の精度や安
定性を求める場合、帰還率と増幅率をより高めなければ
ならない。しかし、これらを高めていくと、必らず発振
現象に到る限界点に達する。つまり、増幅率が1以上で
あって負帰還ループ中での位相ずれが180°以上だと発
振条件を満たすことになるが、通常、位相ずれは比較的
高周波数域でキャパシタンスの影響によって発生し、上
述の位相調整回路7の調整によっても完全に調整するこ
とは困難であり、さらに負帰還ループ中にインダクタン
ス成分(巻線及び巻線間の漏れインダクタンス等)が加
われば、なお困難となる。従って、アナログ式負帰還を
施しても、上記の様な高い磁束密度では、出力電圧Es
の波形歪みおよび不安定さは残存する。すなわち、アナ
ログ式負帰還ループで、前述の発振条件が満たされた場
合、発振は何かの刺激(微小ノイズ等)を引き金にして
特定の周期(通常10KHz〜1MHz)で正帰還を繰り返し始
め、一瞬の間に振幅が加速度的に成長し、第10図に示
すごとく、発振状態となる。However, in the device of the analog type negative feedback system shown in FIG. 8, for example, an iron core made of grain-oriented silicon steel plate can secure sufficient practical accuracy up to a magnetic flux density of about 17,000 gauss, but the magnetic flux density is close to saturation, for example. If an extremely distorted current wave of 18,000 to 20000 gauss is passed and high precision and stability are required, the feedback rate and amplification rate must be increased. However, if these values are raised, the limit point that reaches the oscillation phenomenon is inevitably reached. That is, if the amplification factor is 1 or more and the phase shift in the negative feedback loop is 180 ° or more, the oscillation condition is satisfied, but the phase shift is usually generated in the relatively high frequency range due to the influence of the capacitance. However, it is difficult to completely adjust even by the adjustment of the phase adjusting circuit 7 described above, and it becomes even more difficult if an inductance component (a winding and a leakage inductance between windings) is added to the negative feedback loop. Therefore, even if the analog negative feedback is performed, the output voltage E s is still high at the high magnetic flux density as described above.
The waveform distortion and instability of ∘ remains. That is, in the analog type negative feedback loop, when the above-mentioned oscillation condition is satisfied, the oscillation is triggered by some stimulus (micro noise etc.) and the positive feedback is repeated at a specific cycle (usually 10 KHz to 1 MHz), In a moment, the amplitude grows at an accelerating rate, and as shown in FIG. 10, the oscillation state occurs.
従って、本発明の目的は、コネクタ状接点利用による巻
線作業を不用化にし、また、極めて高い磁束密度でも、
たとえ接点による直流抵抗値、1次巻線W1の等価交流
抵抗値および直流抵抗値が変動しても鉄心毎の入力電圧
の調整が不要であり、且つ磁束波形に歪みがなく正しく
安定した測定が可能な鉄心試験装置用の電源装置を提供
することにある。Therefore, an object of the present invention is to make the winding work by utilizing the connector-like contact point unnecessary, and also to achieve an extremely high magnetic flux density.
Even if the direct current resistance value due to the contact, the equivalent alternating current resistance value and the direct current resistance value of the primary winding W 1 fluctuate, it is not necessary to adjust the input voltage for each iron core, and there is no distortion in the magnetic flux waveform for stable and accurate measurement An object of the present invention is to provide a power supply device for an iron core testing device.
また、本発明の目的は、整流回路負荷の電源装置もしく
は歪電流負荷用電源装置として用いられる電源装置を提
供することにある。Another object of the present invention is to provide a power supply device used as a power supply device for a rectifier circuit load or a power supply device for a distorted current load.
上述の課題を解決するための手段は第1A図,第1B図
に示される。Means for solving the above problems are shown in FIGS. 1A and 1B.
第1A図においては、負荷に電流を供給するための電源
装置たとえば鉄心1の試験装置を示す。基本正弦波発生
手段は基本正弦波電圧Eoを発生する。誤差電圧検出手
段は、基本正弦波電圧Eoと負荷の出力電圧Esたとえ
ば鉄心1の2次巻線間電圧Esとの電圧誤差ΔEを検出
し、記憶手段は電圧誤差ΔEを記憶して基本正弦波電圧
Eoの1サイクル相当分だけ遅延させる。加算手段は遅
延された電圧誤差ΔE′を基本正弦波電圧Eoに加算
し、入力電流供給手段はこの加算手段の加算結果に応じ
た入力電流Ipを負荷たとえば鉄心1の2次巻線W2に
供給するものである。FIG. 1A shows a power supply device for supplying a current to a load, for example, a test device for iron core 1. The basic sine wave generating means generates a basic sine wave voltage E o . Error voltage detecting means detects a voltage error ΔE between the fundamental sinusoidal voltage E o and the load of the output voltage E s for example core 1 of the secondary winding voltage E s, the storage means stores the voltage error ΔE It is delayed by one cycle of the basic sine wave voltage E o . The adding means adds the delayed voltage error ΔE ′ to the basic sine wave voltage E o , and the input current supplying means supplies the input current I p corresponding to the addition result of the adding means to the load, for example, the secondary winding W of the iron core 1. 2 is supplied.
第1B図においては、第1A図の構成要素に、電圧誤差
検出手段と記憶手段との間に、電圧誤差ΔEに遅延され
た電圧誤差ΔE′を加算する加算手段を付加してある。In FIG. 1B, addition means for adding the delayed voltage error ΔE ′ to the voltage error ΔE is added between the voltage error detection means and the storage means in the constituent elements of FIG. 1A.
第1A図の手段によれば、高頻度の正帰還の繰り返しを
防止するために、基本正弦波の1サイクル分の負帰還す
べき波形を記憶して、1サイクル遅延させて負帰還をか
ける。すなわち、第2図に示すごとく、負帰還すべき波
形として、波形誤差(電圧誤差)の分のみ取り出して記
憶し(A)、1サイクルずらして負帰還して波形を補正
する(B)。これにより、高周波数域での位相が180°
以上のずれがあっても、第3図に示すごとく、基本正弦
波1サイクル毎に正帰還は分断されるので、繰り返しに
よる成長、発振は起こらない。According to the means shown in FIG. 1A, in order to prevent repetition of high-frequency positive feedback, a waveform to be negatively fed back for one cycle of the basic sine wave is stored and delayed by one cycle to perform negative feedback. That is, as shown in FIG. 2, as a waveform to be negatively fed back, only a waveform error (voltage error) is taken out and stored (A), and the waveform is corrected by negatively feeding back by shifting by one cycle (B). This makes the phase 180 ° in the high frequency range.
Even if there is the above deviation, as shown in FIG. 3, the positive feedback is divided for each cycle of the basic sine wave, so that growth and oscillation due to repetition do not occur.
第1B図の手段によれば、さらに波形誤差を、1サイク
ル前の記憶波形に加えて記憶し、次のサイクルで、それ
を負帰還する動作を繰り返す。従って、波形誤差の累積
が基本正弦波に加算され、ほぼ無限に帰還率Fを増加さ
せることができる。たとえば、帰還率として 第1サイクル 0.9 第2サイクル 0.99 第3サイクル 0.999 第4サイクル 0.9999 というように増加する。According to the means shown in FIG. 1B, the waveform error is further stored in addition to the stored waveform one cycle before, and the operation of negatively feeding it back is repeated in the next cycle. Therefore, the accumulated waveform error is added to the basic sine wave, and the feedback factor F can be increased almost infinitely. For example, the return rate increases as follows: 1st cycle 0.9 2nd cycle 0.99 3rd cycle 0.999 4th cycle 0.9999.
第4図は本発明に係る記憶方式負帰還電源装置の第1の
実施例を示すブロック回路図であって、鉄心試験装置に
応用したものである。第4図においては、ディジタル処
理により制御が行われる。すなわち、401は各部を制御
する制御部(CPU),402は周波数切替スイッチ、403は
電圧設定スイッチ(たとえばディジタルスイッチ)であ
る。FIG. 4 is a block circuit diagram showing a first embodiment of the memory type negative feedback power supply device according to the present invention, which is applied to an iron core test device. In FIG. 4, control is performed by digital processing. That is, 401 is a control unit (CPU) that controls each unit, 402 is a frequency changeover switch, and 403 is a voltage setting switch (for example, a digital switch).
404は基本正弦波Eoを発生する基本正弦波発生回路(R
OM)、405は基本正弦波発生回路404の出力電圧を調整す
る電圧を調整する電圧調整回路(乗算器)である。この
場合、基本正弦波発生回路404が発生する基本正弦波E
oの周波数は周波数切替スイッチ402のオン,オフに応
じて制御部401によって変化する。つまり、制御部401は
周波数切替スイッチ402のオン,オフに応じた所定の周
波数のクロック信号を基本正弦波発生回路404に送出す
る。また、制御部401は電圧設定スイッチ403の内容に応
じた電圧乗数αを電圧調整回路405に送出し、この結
果、電圧調整回路405は各基本正弦波Eoのディジタル
値に電圧乗数αを乗算して新たな基本正弦波Eo′を発
生する。404 fundamental sine wave generating circuit for generating a basic sine wave E o (R
OM) and 405 are voltage adjusting circuits (multipliers) for adjusting the voltage for adjusting the output voltage of the basic sine wave generating circuit 404. In this case, the basic sine wave E generated by the basic sine wave generation circuit 404
The frequency of o is changed by the control unit 401 depending on whether the frequency changeover switch 402 is on or off. That is, the control unit 401 sends a clock signal of a predetermined frequency according to the ON / OFF of the frequency changeover switch 402 to the basic sine wave generation circuit 404. The control unit 401 also sends a voltage multiplier α according to the contents of the voltage setting switch 403 to the voltage adjusting circuit 405, and as a result, the voltage adjusting circuit 405 multiplies the digital value of each basic sine wave E o by the voltage multiplier α. Then, a new basic sine wave E o ′ is generated.
406,407は総合遅延時間が基本正弦波Eoの1サイクル
分になるように遅延時間を調整する遅延用メモリであっ
て、たとえば、同時に書込み/読出しが可能な双方向性
メモリである。すなわち、各遅延用メモリ406,407は、
制御部401のクロック信号により歩進されるアドレスカ
ウンタ406a,407aの書込みアドレスWAおよび読出しア
ドレスRAに応じて動作する。この場合、遅延用メモリ
406(407)の書込みアドレスWAと読出しアドレスRAと
の差(RA-WA)に制御部401が発生するクロック信号の周
期を乗算した値により決定される。減算回路408は基本
性弦波Eo′とA/D変換器412によりA/D変換され
た2次巻線W2間出力電圧Esとの電圧誤差ΔEを演算
する。また、加算回路409は基本正弦波Eo′に1サイ
クル分だけ遅延された電圧誤差ΔEを加算する。この加
算結果はD/A変換器410によりD/A変換され、この
アナログ値にもとづきパワーアンプ411が1次巻線W1
に入力電流Ipを供給する。Reference numerals 406 and 407 are delay memories for adjusting the delay time so that the total delay time is one cycle of the basic sine wave E o , and are, for example, bidirectional memories in which writing / reading can be performed simultaneously. That is, the delay memories 406 and 407 are
It operates according to the write address WA and the read address RA of the address counters 406a and 407a which are incremented by the clock signal of the control unit 401. In this case, the delay memory
It is determined by a value obtained by multiplying the difference (RA-WA) between the write address WA and the read address RA of 406 (407) by the cycle of the clock signal generated by the control unit 401. The subtraction circuit 408 calculates a voltage error ΔE between the fundamental chord wave E o ′ and the output voltage E s between the secondary windings W 2 which is A / D converted by the A / D converter 412. The adder circuit 409 adds the voltage error ΔE delayed by one cycle to the basic sine wave E o ′. This addition result is D / A converted by the D / A converter 410, and the power amplifier 411 determines the primary winding W 1 based on this analog value.
To the input current I p .
このように、2次巻線W2の出力電圧Esは負帰還ルー
プ回路(406,408,407,412)により入力電流Ipに負帰
還され、しかも、負帰還すべき波形は基本正弦波Eoの
1サイクル分だけ遅延される。この結果、第5図に示す
ごとく、出力電圧Esは高い磁束密度状態でも安定す
る。In this way, the output voltage E s of the secondary winding W 2 is negatively fed back to the input current I p by the negative feedback loop circuit (406, 408, 407, 412), and the waveform to be negatively fed back is one cycle of the basic sine wave E o. Only delayed. As a result, as shown in FIG. 5, the output voltage E s is stable even in a high magnetic flux density state.
第6図は本発明に係る記憶方式負帰還電源装置の第2の
実施例を示すブロック回路図であって、第4図の構成要
素に対し、遅延用メモリ601、アドレスカウンタ601a、
および加算回路602が付加されている。この場合、3つ
の遅延用メモリ406,407,601の総合遅延時間が基本正弦
波Eoの1サイクル分となるように調整される。従っ
て、第2の実施例によれば、第1の実施例に比較して、
負帰還すべき電圧誤差ΔE′が累積されるので、帰還率
Fを極めて大きくすることができる。FIG. 6 is a block circuit diagram showing a second embodiment of the storage type negative feedback power supply device according to the present invention, which is different from the components shown in FIG. 4 in that a delay memory 601, an address counter 601a,
And an adder circuit 602 is added. In this case, the total delay time of the three delay memories 406, 407, 601 is adjusted to be one cycle of the basic sine wave E o . Therefore, according to the second embodiment, as compared with the first embodiment,
Since the voltage error ΔE ′ to be negatively fed back is accumulated, the feedback rate F can be made extremely large.
さらに、上述の実施例においては、1次巻線W1、2次
巻線W2は、コネクタ形式のもの以外でもよく、また、
その巻数も各1回巻きでも充分安定した高精度の試験
(測定)が可能である。また、接点の配列、配置は自由
に設定できる。さらに、1次巻線W1と2次巻線W2は
同一巻数である必要はない。Further, in the above-described embodiment, the primary winding W 1 and the secondary winding W 2 may be other than the connector type, and
Even if the number of turns is one each, a sufficiently stable and highly accurate test (measurement) is possible. Moreover, the arrangement and arrangement of the contacts can be set freely. Furthermore, the primary winding W 1 and the secondary winding W 2 do not have to have the same number of turns.
また、本発明は第8図のアナログ式負帰還方式を併用す
ることによりさらに早い速度で且つ完全な波形補正が可
能となる。Further, according to the present invention, by using the analog negative feedback system shown in FIG.
さらに、本発明は、カットコア型式の鉄心の試験装置に
も適用でき、また、鉄心試験装置用電源装置以外に、整
流回路負荷用、歪電流負荷用電源装置にも適用し得る。Furthermore, the present invention can be applied to a cut-core type iron core testing device, and can also be applied to a power supply device for a rectifier circuit load and a distorted current load, in addition to the power supply device for an iron core testing device.
以上説明したように本発明によれば、鉄心試験装置の場
合、鉄心毎の巻線作業を省略すると共に、極めて高い磁
束密度でも、入力電圧の調整を行うことなく、正しく且
つ安定した試験(測定)をすることができる。また、帰
還率を極めて大きくできる。As described above, according to the present invention, in the case of the iron core test device, the winding work for each iron core is omitted, and even if the magnetic flux density is extremely high, a correct and stable test (measurement) is performed without adjusting the input voltage. ) Can be done. In addition, the feedback rate can be extremely increased.
第1A図,第1B図は本発明の基本構成を示すブロック
回路図、 第2図,第3図は本発明の作用を説明する図、 第4図は本発明に係る記憶方式負帰還電源装置の第1の
実施例を示すブロック回路図、 第5図は第4図における出力特性を示す図、 第6図は本発明に係る記憶方式負帰還電源装置の第2の
実施例を示すブロック回路図、 第7図は試験巻線の一例を示す図、 第8図は先に提案した鉄心試験装置の一実施例を示す回
路図、 第9図は第8図の等価回路図、 第10図は本発明が解決すべき課題を説明する図であ
る。 1:鉄心 2:交流電源 3:交流電流計 4:交流電圧計 W:電力計 W1:1次巻線 W2:2次巻線 Ip:励磁電流 Es:出力電圧 404:基本正弦発生回路 405:電圧調整回路 406,407,601:遅延用メモリ 408:減算回路 409,602:加算回路1A and 1B are block circuit diagrams showing the basic configuration of the present invention, FIGS. 2 and 3 are diagrams for explaining the operation of the present invention, and FIG. 4 is a memory type negative feedback power supply device according to the present invention. 5 is a block circuit diagram showing a first embodiment of the present invention, FIG. 5 is a diagram showing output characteristics in FIG. 4, and FIG. 6 is a block circuit showing a second embodiment of a storage type negative feedback power supply device according to the present invention. Fig. 7, Fig. 7 is a diagram showing an example of a test winding, Fig. 8 is a circuit diagram showing an embodiment of the previously proposed iron core test apparatus, Fig. 9 is an equivalent circuit diagram of Fig. 8, and Fig. 10 FIG. 4 is a diagram for explaining a problem to be solved by the present invention. 1: Iron core 2: AC power supply 3: AC ammeter 4: AC voltmeter W: Power meter W 1 : Primary winding W 2 : Secondary winding I p : Excitation current E s : Output voltage 404: Basic sine generation Circuit 405: Voltage adjustment circuit 406,407,601: Delay memory 408: Subtraction circuit 409,602: Addition circuit
Claims (2)
源装置であって、 基本正弦波電圧(Eo)を発生する基本正弦波発生手段
と、 該基本正弦波電圧と前記負荷の出力電圧(Es)との電
圧誤差(ΔE)を検出する誤差電圧検出手段と、 該電圧誤差を記憶して前記基本正弦波電圧の1サイクル
相当分だけ遅延させる記憶手段と、 該遅延された電圧誤差(ΔE′)を前記基本正弦波電圧
に加算する加算手段と、 該加算手段の加算結果に応じた入力電流(Ip)を前記
負荷に供給する入力電流供給手段と を具備する記憶方式負帰還電源装置。1. A power supply device for supplying a current and a voltage to a load, comprising a basic sine wave generating means for generating a basic sine wave voltage (E o ), the basic sine wave voltage and an output voltage of the load. Error voltage detection means for detecting a voltage error (ΔE) from (E s ), storage means for storing the voltage error and delaying it by one cycle of the basic sine wave voltage, and the delayed voltage error Negative feedback memory system comprising: an addition means for adding (ΔE ′) to the basic sine wave voltage; and an input current supply means for supplying an input current (I p ) according to the addition result of the addition means to the load. Power supply.
間に、前記電圧誤差(ΔE)に前記遅延された電圧誤差
(ΔE′)を加算する加算手段を設けた請求項1に記載
の記憶方式負帰還電源装置。2. The adding means for adding the delayed voltage error (ΔE ') to the voltage error (ΔE) is provided between the voltage error detecting means and the delay means. Memory type negative feedback power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1260088A JPH0630308B2 (en) | 1988-01-25 | 1988-01-25 | Memory type negative feedback power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1260088A JPH0630308B2 (en) | 1988-01-25 | 1988-01-25 | Memory type negative feedback power supply |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01188916A JPH01188916A (en) | 1989-07-28 |
| JPH0630308B2 true JPH0630308B2 (en) | 1994-04-20 |
Family
ID=11809844
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1260088A Expired - Fee Related JPH0630308B2 (en) | 1988-01-25 | 1988-01-25 | Memory type negative feedback power supply |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0630308B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3614677B2 (en) * | 1998-08-12 | 2005-01-26 | 株式会社リコー | Differential transformer inspection equipment |
| CN103728366B (en) * | 2013-12-30 | 2016-03-30 | 中国计量科学研究院 | A kind of signal analysis device for the continuous iron loss measurement of electrical sheet and method |
-
1988
- 1988-01-25 JP JP1260088A patent/JPH0630308B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01188916A (en) | 1989-07-28 |
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