JPH0630379B2 - Master slice type semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice semiconductor device, and more particularly to a master slice semiconductor device that can configure a delay circuit without reducing the number of logic function blocks.

<Prior Art> The master slice type semiconductor device achieves various functions by standardizing the diffusion process for forming elements and changing the final wiring pattern to realize an integrated circuit of an electronic circuit. Widely used in.

Therefore, some electronic circuits realized in the master slice type semiconductor device require a delay circuit,
An example of such a delay circuit is shown in FIG. 1 in the figure
Represents the internal cell area, and 2 and 3 respectively represent the synchrotor and the flip-flop in the internal cell area 1. Between the inverter 2 and the flip-flop 3, there is provided a delay circuit 8 configured by connecting a large number of inverters 4,5, 6, ... 7 in series, and for each inversion of the inverters 4-7. Inverter 2 using the time required
And a signal delay is caused between the flip-flop 3 and the flip-flop 3. The output of the flip-flop 3 is output to the outside via another logic function block (not shown) or the input / output area 9.

Further, as another example of the delay circuit, the delay circuit 10 including a resistor and a capacitor is formed in the internal cell region 1,
When a signal delay is required, a logic circuit is connected to the delay circuit 10 to realize the signal delay.

<Problems to be Solved by the Invention> However, in a delay circuit formed by connecting a plurality of logic elements in multiple stages, the delay time is increased because the elements that should form the logic circuit are originally used in the delay circuit configuration. In the case of a long time, the inversion time of the logic element is extremely fast, so that a large number of logic elements are used and the original logic circuit cannot be constructed. On the other hand, in the internal cell region 1, the delay circuit 10 including a resistor and a capacitor may be formed in advance in anticipation of the need for a delay circuit.
There is a problem that the number of logic elements that can be formed is reduced, and in addition, in each example, each element is completed by the time of wiring, so if there are variations in the characteristics of each element due to process parameter fluctuations. However, even with the same configuration, there is a problem in that there is a difference in delay time and correction is impossible.

<Means for Solving Problems> In view of the above problems, the present invention forms a capacitive element by a buffer circuit in an unused input / output region, and connects the capacitive element to a logic block requiring a delay function. By doing so, it is possible to adjust the delay time without affecting the configuration of the logic block in the internal cell area, and also by making it possible to take out a signal requiring delay to the outside.

<Embodiment> FIG. 1 is a diagram for explaining an embodiment of the present invention, in which 11 is an internal cell region and 12 is an input / output region. Two logic blocks 13 and 1 in the internal cell area 11
When a signal delay is required between four, the logic block 13 is connected via the connection line 15 to the buffer circuit 16 in the input / output area 12 which is not used for input / output of the logic signal. As shown in detail in FIG. 3, the buffer circuit 16 is composed of a complementary MOS inverter 17 and a resistance element 18 for protection against electrostatic withstand voltage.
The source of each MOS transistor forming the S inverter is connected to the gate, and forms a capacitance body by the diffusion capacitance of the channel portion of the MOS transistor. Resistor 18
Is connected to a bonding pad 19, which is connected to the bonding wire 20 and the package lead 21.
Variable capacitor 2 provided on the outside of the semiconductor device via the
2 can be connected. Reference numerals 23 and 24 respectively indicate a semiconductor chip and a package.

Next, to describe the operation, when the inversion signal of the logic block 13 is determined by the capacitance value of the capacitor of the wiring resistance buffer circuit 16 of the connection line 15, the resistance value of the resistor 18, and the capacitance value of the variable capacitor 22. The constant causes a constant delay which is then applied to logic block 14.

<Effect> As described above, according to the present invention, since the buffer circuit in the input / output area forms the capacitor to configure the delay circuit, all the logic blocks in the internal cell area are used for the logic circuit configuration. In addition to being able to do it, you can connect a capacitor to the outside,
The effect that the delay time can be adjusted after wiring is obtained.

In addition, in one embodiment of the present invention, since the capacitor is formed by the transistors that form the buffer circuit, it is possible to easily form a large-capacity capacitor simply by wiring between the source and the gate of the transistor. Also has.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional example, and FIG. 3 is a circuit diagram showing a main part of FIG. 11 ... Internal cell area, 12 ... Input / output area, 13, 1
4 ... Logical function block, 16 ... Buffer circuit.

Claims (1)

[Claims] 1. A single semiconductor substrate is provided with a plurality of internal cell regions having a plurality of logic function blocks, and a plurality of buffer circuits each having at least one transistor and connectable to the logic function blocks. In a master slice type semiconductor device including an input / output region, a delay circuit is configured by forming a capacitive element with a transistor for configuring the buffer circuit and connecting the capacitive element to a wiring connected to the logic function block. Master slice type semiconductor device.