JPH0834249B2 - Semiconductor gate array device - Google Patents

Description

TECHNICAL FIELD The present invention relates to improvements in a semiconductor gate array device.

(Prior Art) Semiconductor gate array devices are being actively developed in order to shorten the development period of logic LSIs and to improve the economic efficiency. This kind of semiconductor gate array device includes a cell group having a plurality of basic gate cells on a semiconductor substrate, and an input / output circuit arranged in the peripheral portion of the cell group and for inputting / outputting a signal to / from the basic gate cell. It is configured by forming. The basic gate cell is configured by connecting a plurality of transistors, and is arranged in a matrix on the semiconductor substrate leaving the wiring region. A desired logic circuit is constructed by appropriately wiring the basic gate cell and the input / output circuit.

In the semiconductor gate array device as described above, the number of basic gate cells arranged is determined in advance, and for example, if there are 1000 gates, it is configured to have about 1000 basic gate cells in total.

By the way, it may be necessary to provide a delay circuit in the logic circuit. In such a case, when the delay time may be short, a flip-flop or a gate circuit is formed in the logic circuit to form the delay circuit.

An example of the delay circuit provided in such a conventional semiconductor gate array device will be described with reference to FIGS. 3 (a) and 3 (b). Here, a delay circuit is formed in the basic gate cell group. That is, the delay circuit 33 is connected between the gates 31 and 32, but the delay circuit 33 is configured by using a basic gate cell. Changes in the signals at points a to d in the circuit of FIG. 3 (a) are shown in FIG. 3 (b). Fig. 3 (b)
As is apparent from the above, the delay circuit 33 forms a pulse signal whose signal rise time is delayed by Δt.

(Problems to be Solved by the Invention) To increase the delay time Δt, a delay circuit 33 is formed by connecting a large number of basic gate cells. When a relatively long delay time is required, a desired delay circuit cannot be constructed without using a large number of gate cells. On the other hand, as described above, the number of gates mounted on the semiconductor substrate is predetermined depending on the gate scale.
Therefore, a large delay time cannot be obtained by simply increasing the number of gate cells used for the delay circuit. This is because if a large number of gate cells are used for the delay circuit, the number of remaining gate cells mounted on the semiconductor substrate may not be sufficient to form a desired logic circuit. .

Therefore, if the number of gates is insufficient, a box (master) one rank higher must be used. As a result, it is necessary to use an expensive semiconductor gate array device equipped with too many gate cells as compared with the scale of the logic circuit to be constructed.

Therefore, it is an object of the present invention to obtain a large delay time without reducing the number of basic gate cells to be used, and therefore, the semiconductor gate array which is excellent in the use efficiency of the gate cells and excellent in the economical efficiency. To provide a device.

(Means for Solving the Problems) A semiconductor gate array device of the present invention is provided with a cell group having a plurality of basic gate cells and a cell group arranged in the vicinity of the cell group, for inputting and outputting a signal to and from the basic gate cell. A semiconductor gate array device having a plurality of input / output circuits formed on a semiconductor substrate, wherein an electrode pad portion is provided between at least two input / output circuits of the input / output circuits. The delay means is composed of the capacitance formed of the semiconductor substrate and the protective resistance of at least one of the input / output circuits, thereby achieving the above object.

(Examples) The present invention will be described below with reference to Examples.

An embodiment of the present invention will be described with reference to FIG. First
FIG. 1A shows a circuit diagram of an embodiment of the present invention, and FIG. 1B shows signal waveforms at points a to d in this circuit.

In this embodiment, a delay circuit utilizing a pair of input / output circuits is formed between the gates 11 and 12 in the gate cell group of the gate array device. That is, of the plurality of input / output circuits arranged in the peripheral portion of the gate cell group on the semiconductor substrate, the output buffer circuit 13 serving as an extra input / output circuit.
A delay circuit is formed between the Schmitt input buffer circuit 14 and the Schmitt input buffer circuit 14.

The output end of the output buffer circuit 13 is connected to the electrode pad 15 formed on the semiconductor substrate by a wiring pattern. Similarly, the input end of the Schmitt input buffer circuit 14 is connected to the electrode pad 16 also formed on the semiconductor substrate by a wiring pattern. These electrode pads
15 and 16 are connected to each other by a conductive portion 17 for connection. The one electrode pad 16 is electrically connected to the substrate potential (GND) by the capacitance C formed between the electrode pad 16 and the semiconductor substrate.

The output buffer circuit 13 is shown in more detail in FIG. A protection resistor 21 is inserted in series on the output end side of the output buffer circuit 13. Therefore, the protection resistor 21 and the capacitance C formed between the electrode pad 16 and the semiconductor substrate form a CR delay circuit. This delay circuit has a time constant (T =
It has a delay time according to CR).

In this embodiment having such a configuration, an arbitrary delay time can be obtained by appropriately selecting the value of the capacitance C or the resistance 21. That is, as shown in FIG. 1 (b), the rising time of the signal at the point c is delayed, and the falling time to the threshold voltage V _TH of the gate 12 is delayed. The magnitude of this delay time can be adjusted by appropriately selecting the value of the capacitance C or the resistance 21.

Moreover, since this delay circuit is constructed by utilizing the surplus input / output circuit, it is not necessary to use the gate cells in the cell group, and it can be seen that the use efficiency of the number of used gates can be greatly improved. Also, the delay time can be appropriately selected by adjusting the number of pairs of input / output circuits used.

(Effects of the Invention) As described above, according to the present invention, the delay unit is provided by using the protection resistance of the input / output circuit arranged in the peripheral portion of the cell group and the capacitance formed by the electrode pad portion and the semiconductor substrate. Composed. Therefore, the production process can be simplified by using no external capacitance, an arbitrary delay time can be obtained, and the input / output circuit to be used and the input / output circuit including the electrode pad between them can be obtained. A larger arbitrary delay time can be easily obtained by increasing the number of copies. Moreover, since it is not necessary to use the basic gate cells in the cell group to form the delay circuit, it is possible to effectively increase the gate use efficiency.

Therefore, the use efficiency of the internal gate cell can be remarkably improved as compared with the conventional one in which the delay circuit is configured, so that the semiconductor gate array device excellent in economical efficiency can be realized.

[Brief description of drawings]

FIG. 1 (a) is a circuit diagram of an embodiment of the present invention, and FIG. 1 (b) is a diagram showing signal waveforms at various points in the embodiment.
2 is a circuit diagram showing the details of the output buffer circuit, FIG. 3 (a) is a circuit diagram for explaining a delay circuit in a conventional gate array device, and FIG. 3 (b) is a signal waveform in a conventional example. It is a figure explaining. 11, 12 …… Gate, 13 …… Output buffer circuit, 14 …… Input Schmidt buffer circuit, 15,16 …… Electrode pad, 17
...... Connection conductive part, 21 ...... Protection resistance, C ...... Capacity.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H03K 19/173 9199-5K

Claims (1)

[Claims] 1. A cell group having a plurality of basic gate cells,
A semiconductor gate array device, which is arranged in the vicinity of the cell group and has a plurality of input / output circuits for inputting / outputting signals to / from the basic gate cell, which is formed on a semiconductor substrate. An electrode pad portion is provided between at least two input / output circuits, and a delay unit is configured by the capacitance formed by the electrode pad portion and the semiconductor substrate and at least one of the input / output circuit protective resistors. Semiconductor gate array device.