JPH0630396B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0630396B2 JPH0630396B2 JP62276303A JP27630387A JPH0630396B2 JP H0630396 B2 JPH0630396 B2 JP H0630396B2 JP 62276303 A JP62276303 A JP 62276303A JP 27630387 A JP27630387 A JP 27630387A JP H0630396 B2 JPH0630396 B2 JP H0630396B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- collector
- barrier layer
- quantum well
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
- H10D48/30—Devices controlled by electric currents or voltages
- H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H10D48/36—Unipolar devices
- H10D48/362—Unipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunnelling transistors [RTT], bulk barrier transistors [BBT], planar doped barrier transistors [PDBT] or charge injection transistors [CHINT]
Landscapes
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】 〔概要〕 AlGaAs/GaAs，InGaAs/InP等のヘテロ接合を用いたホッ
トエレクトロントランジスタ(HET)に関し， コレクタベース間リークを増加させないで，コレクタバ
リア内のΓ−Ｌ谷間散乱による電子走行時間の低下を防
止することを目的とし， 半導体基板上に順次形成された一導電型コレクタ層，コ
レクタバリア層，一導電型ベース層，さらにその上に，
第１の量子井戸バリア層，量子井戸ウエル層，第２の量
子井戸バリア層からなる量子井戸層，あるいはエミッタ
バリア層のいずれかの層，および一導電型エミッタ層と
を有し，該コレクタバリア層が該コレクタ層側より厚さ
方向に一部一導電型不純物をドープしてなるように構成
する。Detailed Description [Outline] A hot electron transistor (HET) using a heterojunction such as AlGaAs / GaAs, InGaAs / InP, etc. For the purpose of preventing a decrease in electron transit time due to, one-conductivity type collector layer, collector barrier layer, one-conductivity type base layer, which are sequentially formed on the semiconductor substrate, and further thereon.
A first quantum well barrier layer, a quantum well well layer, a quantum well layer including a second quantum well barrier layer, or an emitter barrier layer, and a one-conductivity-type emitter layer, and the collector barrier The layer is formed by partially doping one conductivity type impurity in the thickness direction from the collector layer side.
本発明は半導体装置，特にAlGaAs/GaAs，InGaAs/InP等
のヘテロ接合を用いたホットエレクトロントランジスタ
(HET)に関する。The present invention relates to a semiconductor device, particularly a hot electron transistor using a heterojunction such as AlGaAs / GaAs or InGaAs / InP.
Regarding (HET).
HETは電子がエミッタよりベースに注入されたとき，高
い位置エネルギを運動エネルギに変換して高速で走行で
きる利点を持つ。その飽和速度は通常のトランジスタで
は107cm/secであるが，HETではその10倍程度になる。HET has the advantage that when electrons are injected into the base from the emitter, it converts high potential energy into kinetic energy and can travel at high speed. The saturation speed is 10 7 cm / sec for ordinary transistors, but it is about 10 times that for HET.
HETの中でも，共鳴トンネリングホットエレクトロン(RH
ET)は，共鳴トンネリング効果を利用し，高いエネルギ
を持つホットエレクトロンの動きを制御できるので，高
速の論理，記憶等の機能を持つことができる。さらに，
少数のデバイスでLSIを構成する回路機能を実現できる
ため将来の新機能デバイスとして注目されている。Resonant tunneling hot electrons (RH
Since ET) can control the movement of hot electrons with high energy by utilizing the resonance tunneling effect, it can have functions such as high-speed logic and memory. further,
It is attracting attention as a new functional device in the future because it can realize the circuit function that constitutes an LSI with a small number of devices.
従って，ここではAlGaAs/GaAs，InGaAs/InPヘテロ接合
を用いたRHETを例にとり説明する。Therefore, here, RHET using AlGaAs / GaAs and InGaAs / InP heterojunctions will be described as an example.
第４図は従来のAlGaAs/GaAsヘテロ接合を用いたRHETの
断面図である。FIG. 4 is a sectional view of a conventional RHET using an AlGaAs / GaAs heterojunction.
図において，GaAs基板１上に，例えばMBE法により順次n
+-GaAsコレクタ層２，Al0.3Ga0.7Asコレクタバリア層
３，n-GaAsベース層４， さらにAl0.3Ga0.7Asバリア層５，GaAsウエル層６，Al
0.3Ga0.7Asバリア層７からなる量子井戸層，およびn+-G
aAsエミッタ層８を成長する。In the figure, n on the GaAs substrate 1 is sequentially processed by, for example, the MBE method.
+ -GaAs collector layer 2, Al 0.3 Ga 0.7 As collector barrier layer 3, n-GaAs base layer 4, further Al 0.3 Ga 0.7 As barrier layer 5, GaAs well layer 6, Al
0.3 Ga 0.7 As Quantum well layer consisting of barrier layer 7 and n + -G
The aAs emitter layer 8 is grown.
上記各層の諸元は，例えば次の通りである。The specifications of the above layers are as follows, for example.
エミッタ層８，ベース層４，コレクタ層２上にそれぞれ
厚さ200/3000ÅのAuGe/Au電極が取り付けられる。 AuGe / Au electrodes having a thickness of 200 / 3000Å are attached on the emitter layer 8, the base layer 4, and the collector layer 2, respectively.
単に，HETの場合は，共鳴量子井戸層であるバリア層
５，ウエル層６，バリア層７の代わりに，エミッタバリ
ア層として，厚さ100〜250ÅのAl0.3Ga0.7As層を形成す
る。In the case of HET, an Al 0.3 Ga 0.7 As layer having a thickness of 100 to 250 Å is formed as an emitter barrier layer instead of the barrier layer 5, the well layer 6 and the barrier layer 7 which are the resonance quantum well layers.
第５図は従来例のRHETのバンド構造図である。 FIG. 5 is a band structure diagram of a conventional RHET.
図において，Al0.3Ga0.7Asコレクタバリア層３のΓ谷
（伝導帯底ECと一致）とＬ谷のセパレーションエネルギ
ΔＥ（Γ−Ｌ）が約0.25eVと，n+-GaAsコレクタ層２の
約0.3eVと比較して小さいため，バイアス電圧が加えら
れたコレクタバリア層３中を通過するホットエレクトロ
ン（矢印で図示される）がΓ谷よりＬ谷に移り，Γ−Ｌ
谷間散乱によりその走行速度を低下させ問題となってい
る。In the figure, the separation energy ΔE (Γ−L) of the Γ valley (matching the conduction band bottom E C ) of the Al 0.3 Ga 0.7 As collector barrier layer 3 and the L valley is about 0.25 eV, and the n + -GaAs collector layer 2 has Since it is smaller than about 0.3 eV, hot electrons (shown by an arrow) passing through the collector barrier layer 3 to which a bias voltage is applied move from the Γ valley to the L valley, and Γ−L
There is a problem that the traveling speed decreases due to the valley scattering.
因に，Γ谷の電子の有効質量m*は m*＝0.068m0． ここに，m0：電子の静止質量 であり，Ｌ谷ではその10倍程度と大きくなり，電子のエ
ネルギは低下し，電子はコレクタに到達しなくなる。By the way, the effective mass m * of the electrons in the Γ valley is m * = 0.068m 0 . Where m 0 is the static mass of the electron, which is about 10 times as large in the L valley, the energy of the electron decreases, and the electron does not reach the collector.
本発明は，上記のコレクタバリア内のΓ−Ｌ谷間散乱に
よる電子走行時間の低下を防止することを目的とする。An object of the present invention is to prevent a decrease in electron transit time due to Γ-L valley scattering in the collector barrier.
上記問題点の解決は，半導体基板上に順次形成された一
導電型コレクタ層，コレクタバリア層，一導電型ベース
層，さらにその上に，第１の量子井戸バリア層，量子井
戸ウエル層，第２の量子井戸バリア層からなる量子井戸
層（RHETの場合），あるいはエミッタバリア層のいずれ
かの層，および一導電型エミッタ層（HETの場合）とを
有し，該コレクタバリア層が該コレクタ層側より厚さ方
向に一部一導電型不純物をドープしてなる半導体装置に
より達成される。To solve the above problems, a one-conductivity-type collector layer, a collector barrier layer, a one-conductivity-type base layer, which are sequentially formed on a semiconductor substrate, and a first quantum well barrier layer, a quantum well well layer, and A quantum well layer consisting of two quantum well barrier layers (in the case of RHET) or an emitter barrier layer, and a one conductivity type emitter layer (in the case of HET), wherein the collector barrier layer is This is achieved by a semiconductor device in which an impurity of one conductivity type is partially doped in the thickness direction from the layer side.
本発明は，ΔＥ（Γ−Ｌ）は従来のAlGaAsコレクタバリ
ア層が約0.25eVと小さく，コレクタバリア層にコレクタ
ベース間電圧VCBを加えたときに，コレクタバリア層内
を略バリスティックに走行するホットエレクトロンはΓ
−Ｌ谷間散乱を受けるようになるのを，コレクタバリア
層にコレクタ側より一部ｎ型不純物をドープして実質的
なコレクタバリア厚さを小さくしてΓ−Ｌ谷間散乱によ
る電子走行速度の低下を防止するようにしたものであ
る。In the present invention, ΔE (Γ-L) is as small as about 0.25 eV in the conventional AlGaAs collector barrier layer, and when the collector-barrier layer voltage V CB is applied to the collector barrier layer, it travels in the collector barrier layer in a substantially ballistic manner. Hot electrons are Γ
-L valley scattering occurs because the collector barrier layer is partially doped with n-type impurities from the collector side to reduce the substantial collector barrier thickness and the electron traveling speed is reduced due to Γ-L valley scattering. Is to prevent.
Γ−Ｌ谷間散乱を防止する一方法としてコレクタバリア
層をできるだけ薄くすればよいが，そうするとコレクタ
ベース間のリーク電流が増加するという問題が生ずる。
そこで，コレクタバリア層の厚さはそのままにして，コ
レクタ側にｎ型不純物を一部ドープすると，ドープ領域
に到達した電子はコレクタに収集されたのと同等にな
り，実質的なバリア厚さを減少してΓ−Ｌ谷間散乱を防
止して，かつコレクタ耐圧を維持することができるよう
になる。One way to prevent Γ-L valley scattering is to make the collector barrier layer as thin as possible, but this causes a problem that the leak current between the collector and the base increases.
Therefore, if the collector barrier layer thickness is left unchanged and the collector side is partially doped with n-type impurities, the electrons reaching the doped region become equivalent to being collected in the collector, and the substantial barrier thickness is reduced. It becomes possible to prevent the Γ-L valley scattering and to maintain the collector breakdown voltage.
第１図は本発明の一実施例によるAlGaAs/GaAsヘテロ接
合を用いたRHETの断面図である。FIG. 1 is a sectional view of an RHET using an AlGaAs / GaAs heterojunction according to an embodiment of the present invention.
図において，半絶縁性GaAs基板１上に，例えばMBE法に
より順次n+-GaAsコレクタ層２，n-Al0.3Ga0.7As層3Aお
よびAl0.3Ga0.7As層3Bからなるコレクタバリア層３，n-
GaAsベース層４，さらに，Al0.3Ga0.7Asバリア層５，Ga
Asウエル層６，Al0.3Ga0.7Asバリア層７からなる量子井
戸層，およびn+-GaAsエミッタ層８を成長する。In the figure, on the semi-insulating GaAs substrate 1, a collector barrier layer 3, n consisting of n + -GaAs collector layer 2, n-Al 0.3 Ga 0.7 As layer 3A and Al 0.3 Ga 0.7 As layer 3B is sequentially formed by, for example, the MBE method. -
GaAs base layer 4, Furthermore, Al 0.3 Ga 0.7 As barrier layer 5, Ga
As well layer 6, quantum well layer composed of Al 0.3 Ga 0.7 As barrier layer 7, and n + -GaAs emitter layer 8 are grown.
上記各層の諸元は，例えば次の通りである。The specifications of the above layers are as follows, for example.
エミッタ層８，ベース層４，コレクタ層２上にそれぞれ
厚さ200/3000ÅのAuGe/Au電極が取り付けられる。 AuGe / Au electrodes having a thickness of 200 / 3000Å are attached on the emitter layer 8, the base layer 4, and the collector layer 2, respectively.
単に，HETの場合は，量子井戸層５，６，７の代わりに
エミッタバリア層として，厚さ100〜250ÅのAl0.3Ga0.7
As層を形成する。Simply, in the case of HET, instead of the quantum well layers 5, 6 and 7, an emitter barrier layer of Al 0.3 Ga 0.7 with a thickness of 100 to 250 Å is used.
As layer is formed.
第２図は実施例のRHETのバンド構造図である。FIG. 2 is a band structure diagram of the RHET of the example.
図において，コレクタバリア層３の厚さは1/2になった
のと等価であり，Γ−Ｌ谷間散乱による電子走行速度の
低下は起こらない。In the figure, the thickness of the collector barrier layer 3 is equivalent to being halved, and the electron traveling speed does not decrease due to Γ-L valley scattering.
以上の実施例と，コレクタバリア層を半分に薄くした場
合と，従来例とを比較した結果を次に示す。The following is the result of comparison between the above-described embodiment, the case where the collector barrier layer is made half thin, and the conventional example.
上記のように，実施例の場合はコレクタ走行時間が低下
し，リーク電流は増加しない。 As described above, in the case of the embodiment, the collector transit time is reduced and the leak current does not increase.
GaAsベース層の(R)HETよりさらに高速のInGaAsベース層
の(R)HETについても本発明は同様の効果を有する。The present invention has the same effect for (R) HET of InGaAs base layer, which is faster than (R) HET of GaAs base layer.
いま，両者を比較すると， であり，InGaAsの方が有効質量，ΔＥ（Γ−Ｌ）ともに
大きく有利である。Now, comparing the two, Therefore, InGaAs is more advantageous in terms of both effective mass and ΔE (Γ−L).
次にInGaAsベース層の(R)HETの実施例について説明す
る。Next, an example of (R) HET for the InGaAs base layer will be described.
第３図は本発明の他の実施例で，InGaAs/InAlGaAsヘテ
ロ接合を用いたRHETの断面図である。FIG. 3 is a sectional view of an RHET using an InGaAs / InAlGaAs heterojunction according to another embodiment of the present invention.
図において、InP基板11上に，例えばMBE法により順次n+
-In0.53Ga0.47Asコレクタ層12，n-In0.52(Al0.5Ga0.5)
0.48Asコレクタバリア層13A，In0.52(Al0.5Ga0.5)0.48A
sコレクタバリア層13B，n-In0.53Ga0.47Asベース層14，
さらにIn0.53Al0.47Asバリア層15，In0.53Ga0.47Asウエ
ル層16，In0.53Al0.47Asバリア層17からなる量子井戸
層，およびn+-In0.53Ga0.47Asエミッタ層18を成長す
る。In the figure, on the InP substrate 11, n +
-In 0.53 Ga 0.47 As collector layer 12, n-In 0.52 (Al 0.5 Ga 0.5 )
0.48 As Collector barrier layer 13A, In 0.52 (Al 0.5 Ga 0.5 ) 0.48 A
s collector barrier layer 13B, n-In 0.53 Ga 0.47 As base layer 14,
Further, a quantum well layer including an In 0.53 Al 0.47 As barrier layer 15, an In 0.53 Ga 0.47 As well layer 16, an In 0.53 Al 0.47 As barrier layer 17, and an n + -In 0.53 Ga 0.47 As emitter layer 18 are grown.
上記各層の諸元は，例えば次の通りである。The specifications of the above layers are as follows, for example.
エミッタ層18，ベース層14，コレクタ層12上にそれぞれ
厚さ200/3000ÅのCr/Au電極が取り付けられる。 Cr / Au electrodes having a thickness of 200 / 3000Å are attached on the emitter layer 18, the base layer 14, and the collector layer 12, respectively.
単に，HETの場合は，共鳴量子井戸層15，16，17の代わ
りにエミッタバリア層として，厚さ100〜250ÅのIn0.53
Al0.47As層を形成する。Simply, in the case of HET, instead of the resonant quantum well layers 15, 16 and 17, an emitter barrier layer of In 0.53 with a thickness of 100 to 250 Å is used.
An Al 0.47 As layer is formed.
以上説明したように本発明によれば，(R)HETにおいてコ
レクタベース間リーク電流を増加させないで，コレクタ
バリア内のΓ−Ｌ谷間散乱による電子走行時間の低下を
防止することができる。As described above, according to the present invention, it is possible to prevent a decrease in electron transit time due to Γ-L valley scattering in the collector barrier without increasing the collector-base leak current in (R) HET.
第１図は本発明の一実施例によるAlGaAs/GaAsヘテロ接
合を用いたRHETの断面図， 第２図は実施例のRHETのバンド構造図， 第３図は本発明の他の実施例で， InGaAs/InAlGaAsヘテロ接合を用いたRHETの断面図， 第４図は従来のAlGaAs/GaAsヘテロ接合を用いたRHETの
断面図， 第５図は従来例のRHETのバンド構造図である。 図において， １はGaAs基板， ２はn+-GaAsコレクタ層， 3Aはn-Al0.3Ga0.7Asコレクタバリア層， 3BはAl0.3Ga0.7Asコレクタバリア層， ４はn-GaAsベース層， ５はAl0.3Ga0.7As量子井戸バリア層， ６はGaAs量子井戸ウエル層， ７はAl0.3Ga0.7As量子井戸バリア層， ８はn+-GaAsエミッタ層， 11はInP基板， 12はn+-In0.53Ga0.47Asコレクタ層， 13Aはn-In0.52(Al0.5Ga0.5)0.48Asコレクタバリア層， 13BはIn0.52(Al0.5Ga0.5)0.48Asコレクタバリア層， 14はn-In0.53Ga0.47Asベース層， 15はIn0.53Al0.47As量子井戸バリア層， 16はIn0.53Ga0.47As量子井戸ウエル層， 17はIn0.53Al0.47As量子井戸バリア層， 18はn+-In0.53Ga0.47Asエミッタ層 である。FIG. 1 is a sectional view of an RHET using an AlGaAs / GaAs heterojunction according to an embodiment of the present invention, FIG. 2 is a band structure diagram of the RHET of the embodiment, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a sectional view of an RHET using an InGaAs / InAlGaAs heterojunction, FIG. 4 is a sectional view of an RHET using a conventional AlGaAs / GaAs heterojunction, and FIG. 5 is a band structure diagram of a conventional RHET. In the figure, 1 is a GaAs substrate, 2 is an n + -GaAs collector layer, 3A is an n-Al 0.3 Ga 0.7 As collector barrier layer, 3B is an Al 0.3 Ga 0.7 As collector barrier layer, 4 is an n-GaAs base layer, 5 Is an Al 0.3 Ga 0.7 As quantum well barrier layer, 6 is a GaAs quantum well well layer, 7 is an Al 0.3 Ga 0.7 As quantum well barrier layer, 8 is an n + -GaAs emitter layer, 11 is an InP substrate, 12 is n + - In 0.53 Ga 0.47 As collector layer, 13A is n-In 0.52 (Al 0.5 Ga 0.5 ) 0.48 As collector barrier layer, 13B is In 0.52 (Al 0.5 Ga 0.5 ) 0.48 As collector barrier layer, 14 is n-In 0.53 Ga 0.47 As base layer, 15 is In 0.53 Al 0.47 As quantum well barrier layer, 16 is In 0.53 Ga 0.47 As quantum well well layer, 17 is In 0.53 Al 0.47 As quantum well barrier layer, 18 is n + -In 0.53 Ga 0.47 As It is the emitter layer.
Claims (1)
ス層，さらにその上に， 第１の量子井戸バリア層，量子井戸ウエル層，第２の量
子井戸バリア層からなる量子井戸層，あるいはエミッタ
バリア層のいずれかの層， および一導電型エミッタ層とを有し， 該コレクタバリア層が該コレクタ層側より厚さ方向に一
部一導電型不純物をドープしてなることを特徴とする半
導体装置。1. A one-conductivity-type collector layer, a collector-barrier layer, a one-conductivity-type base layer, which are sequentially formed on a semiconductor substrate, and a first quantum well barrier layer, a quantum well well layer, and a second quantum well barrier layer. A quantum well barrier layer composed of a quantum well barrier layer or an emitter barrier layer, and an emitter layer of one conductivity type, wherein the collector barrier layer is partially of one conductivity type in the thickness direction from the collector layer side. A semiconductor device characterized by being doped with impurities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62276303A JPH0630396B2 (en) | 1987-10-30 | 1987-10-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62276303A JPH0630396B2 (en) | 1987-10-30 | 1987-10-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01117356A JPH01117356A (en) | 1989-05-10 |
| JPH0630396B2 true JPH0630396B2 (en) | 1994-04-20 |
Family
ID=17567571
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62276303A Expired - Fee Related JPH0630396B2 (en) | 1987-10-30 | 1987-10-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0630396B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115117209A (en) * | 2022-07-01 | 2022-09-27 | 西安电子科技大学广州研究院 | Gallium nitride heterojunction bipolar photonic transistor and preparation method thereof |
-
1987
- 1987-10-30 JP JP62276303A patent/JPH0630396B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01117356A (en) | 1989-05-10 |
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