JPH0630482B2 - Digital multiple conversion circuit - Google Patents

Description

The present invention relates to a digital signal conversion circuit. In particular,
The present invention relates to the multiplexing conversion circuit. The present invention is suitable for use in microwave communication.

[Conventional technology]

Conventionally, when a digital signal is multiplexed, all the time slots allocated for auxiliary signal transmission in the multiplexing technique are used to determine the synchronization frequency of the synchronization system and select the stuff rate.

[Problems to be solved by the invention]

The selection of the staff rate in the above synchronization method is as follows.
There is a problem that it is not easy to set the synchronization frequency.

The present invention solves the above-mentioned problems, and when multiplexing high-speed, medium-speed, and low-speed signal trains of different frequency bands in a high-speed frequency band, synchronization in synchronization of the medium-speed and low-speed signal trains An object of the present invention is to provide a digital multiplex conversion circuit that can easily determine a frequency and secure a stuff rate.

[Means for solving problems]

The present invention provides, in a digital multiplex conversion circuit, I first synchronizing circuits for synchronizing I high-speed digital signals and J second synchronizing circuits for synchronizing J medium-speed digital signals. Necessary for a circuit, K third synchronizing circuits for synchronizing K low-speed digital signals, and a synchronizing circuit and a multiplexing circuit for converting each of the signals into a synchronizing signal according to a frame format of digital multiplex conversion. Generation circuit including a synchronization frequency oscillator circuit for generating various timing signals, and J-second synchronization circuit output signals are stored in the assigned time slots of a plurality of synchronization signal trains from one column to P columns, respectively. Storing the J first serial-parallel conversion circuits for converting to parallel signals of the column and the K third synchronization circuit output signals in the allocation time slots of the plurality of synchronization signal sequences And K-number of the second serial-parallel conversion circuit for converting the parallel signals Q columns from each one column for the I
Output signals of the first synchronization circuits, output signals of the J conversion circuits, output signals of the K second conversion circuits, frame synchronization signals from the timing generation circuit, and other auxiliary transmission lines. According to the frame format of the digital multiplex conversion, the medium-speed or low-speed digital signal is composed of R number of multiplexing circuits for multiplexing a part of the allocated time slot.

[Action]

The digital multiplex conversion circuit of the present invention does not use all the time slots prepared for multiplexing the medium-speed and low-speed signal trains, but performs serial-parallel conversion on the medium-speed and low-speed signal trains, and Multiplexing is performed by using a part instead of the whole, thereby giving a degree of freedom to the synchronization frequency of the medium-speed and low-speed signal trains and ensuring the stuffing rate of the synchronization system.

[Embodiment] An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention, FIG. 2 is a simplified drawing of an essential part of FIG. 1, and FIG. 3 is a frame format explanatory view thereof.

The high speed digital signals 1 to 1 are input to the multiplexing circuits 106 to 106 (the outputs are the multiplexed signals 13 to 13) via the synchronization circuits 101 to 101. The medium-speed digital input signals 2 to 2 are transferred to the first serial / parallel conversion circuit 10 via the synchronization circuits 102 to 102.
7 to 107 (the output is input to the multiplexing circuits 106 to 106). The low-speed digital input signals 3 to 3 are synchronized by the synchronization circuit 10
It is input to the second serial / parallel conversion circuits 108 to 108 (outputs are input to the multiplexing circuits 106 to 106) via 3 to 103. The output of the synchronization frequency oscillation circuit 104 is the timing generation circuit 105.
To the synchronizing circuits 101 to 101, 102 to 102, 103 to 103, and further to the multiplexing circuits 106 to 106.

Although various timing control signals are required for operations such as synchronization, serial / parallel conversion, multiplexing, time slot control, etc., this function is the same as the conventional stuff multiplex conversion, and is omitted here.

FIG. 2 is an explanatory diagram including one part each. Fig. 3
(a) is a frame format in which a high-speed digital signal before synchronization is multiplexed with (S-1) bits after synchronization, and an additional bit is inserted at a rate of 1 bit for each S bit. Are known. FIG. 3 (b-1) shows a series of 1 bit, that is, a series of S bits. Reference numeral F indicates a frame synchronization time slot, X indicates a parity time slot for monitoring the transmission path quality, or another purpose such as pulse stuffing information, a time slot for transmitting an alarm, and Y
Is a time slot for medium speed digital signals, and Z is a time slot for low speed digital signals. A frame synchronization time slot is referred to as one frame, and the total number of Y allocated time slots in one frame is y, the total number of allocated Z time slots is z, and the total number of constituent time slots is n. FIGS. 3 (b-2) and 3 (b-3) show the synchronized medium-speed digital signal 5 and synchronized low-speed digital signal 6, respectively. For explanation, the number of used time slots of the medium-speed digital signal is (y -2), and the number of time slots for low-speed digital signals is (z-1).

In FIG. 2, which schematically shows the essential parts of the embodiment of the present invention consisting of one part each, a high speed digital signal 1, a medium speed digital signal 2 and a low speed digital signal 3 are respectively synchronized circuits 101, 102, 103. Entered in. The respective synchronization circuits 101, 102, 103 synchronize the respective input signals 1, 2, 3 in an asynchronous relationship with each other by synchronizing the signal trains 4, 5, 6 by a pulse stuffing method well known as a synchronization technique. Convert to. Each timing signal 7, 8 and 9 required at this time is generated by a timing generation circuit 105 including a synchronization frequency oscillation circuit 104.

For the synchronization timing signals 8 and 9 of the medium-speed digital signal 2 and the low-speed digital signal 3, the number of used time slots is set to 1 in order to partially use the allocated time slots, Y and Z, respectively. Per frame,
It is output so as to be controlled to (y-2) and (z-1), respectively.

Therefore, in the frame format shown in FIG. 3, the synchronization frequency necessary for synchronizing the medium speed digital signal 2 and the low speed digital signal 3 is the synchronized medium speed digital signal frequency. And synchronized low-speed digital signal frequency Indicated by. Here, _H represents the frequency of the synchronized high-speed digital signal, and y'and z'represent the number of times the medium / low-speed digital signal time slot is used in one frame.

By this operation, the synchronized middle-speed / low-speed digital signal outputs 5 and 6 are stored in the partially used time slots of Y and Z in FIG. 3 (b-1), as shown in FIG. 3 (b-2), ( The signal sequence is as shown in b-3).

Each synchronized middle-speed / low-speed digital signal is input to the first / second serial-parallel conversion circuits 107 and 108, but since there is one high-speed digital signal sequence to be synchronously multiplexed, the one shown in FIG. Since the serial-parallel conversion circuit does not perform any conversion, the input and output are the same.

When the number of medium-speed / low-speed digital signal trains and the number of high-speed digital signal trains are plural (in the case of FIG. 1), serial / parallel (1 train → (Multiple columns) conversion will be applied.

Synchronized high-speed digital signal 4, medium-speed digital signal 5 (Fig. 3 (b-2)), low-speed digital signal 6 (Fig. 3)
(b-3)) is multiplexed by the multiplexing circuit 106 according to the frame format shown in FIG.
(a)). That is, the high-speed digital signal 4 is shown in the (S-1) -bit white time slot portion shown in FIG. 3 (a), the medium-speed digital signal 5 and the low-speed digital signal 6 are shown in FIG. 3 (b-1). It is multiplexed into the Y and Z time slot portions shown (the shaded time slot portions in FIG. 3 (a)).

Pulse stuffing type synchronization circuits 101, 102,
In 103, it is an absolute requirement that the staff rate be 0 to 1.0. The stuffing rate is determined by the frequency before and after synchronization and the frame format for multiplexing. Therefore, in the synchronizing circuits 101, 102, and 103 of the signal trains in which the synchronizing frequency bands are remarkably different, instead of fixing the synchronizing frequency of the frequency band other than the high-speed frequency band, synchronization is performed by using the time slot for multiplexing. The frequency can be freely selected. That is, the synchronized medium-speed digital signal frequency And synchronized low-speed digital signal frequency Even if _{H 1} , S, n, y, and z are determined, the degree of freedom can be given to the synchronization frequency by the values of y ′ and z ′. Since the synchronization frequency can be freely selected in this way, it becomes possible to easily select the stuff rate in the synchronization system.

Similar effects can be obtained by expanding the above into high-speed, medium-speed, and low-speed digital signal series of I series, J series, and K series.

Reference numeral 12 in FIGS. 1 and 2 means a frame synchronization signal, a parity signal, or the like.

Note that detailed portions of the timing control signals necessary for various operations are omitted in this description.

〔The invention's effect〕

As described above, instead of using all the time slots allocated for auxiliary signal transmission in setting the auxiliary signal transmission time slot in the multiplexing technique,
The use of a part of the time slots gives a degree of freedom to the synchronization frequency for auxiliary signal transmission and facilitates selection of the stuffing rate of the synchronization system.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. FIG. 2 is a simplified block configuration diagram of a main part of an apparatus according to the present invention. FIG. 3 is a frame format diagram of the embodiment of the present invention. 101 to 103 ... Synchronizing circuit, 104 ... Synchronizing frequency oscillation circuit, 105 ... Timing generating circuit, 106 ... Multiplexing circuit,
107 ... first serial / parallel conversion circuit, 108 ... second serial / parallel conversion circuit, H ... synchronized high-speed digital signal frequency, I ... number of high-speed digital signals 4, J ... medium-speed digital Number of signals 5, K ... Number of low-speed digital signals 6, F ... Time slot for frame synchronization, X ... Pulse stuffing information, Y ... Time slot for medium-speed digital signals (allocation number y) , Z ……
Time slots for low-speed digital signals (allocation number z).

Claims (1)

[Claims] 1. I first synchronization circuits for synchronizing I (I is an integer of 1 or more) high speed digital signals, and J (J is an integer of 1 or more) medium speed digital signals. J second synchronizing circuits for synchronizing, K third synchronizing circuits for synchronizing K (K is an integer of 1 or more) low-speed digital signals, and the signals are subjected to digital multiplex conversion. And a timing generation circuit including a synchronization frequency oscillation circuit for generating various timing signals necessary for the multiplexing circuit according to the frame format of J. 1 to store the second synchronization circuit output signal of each of the plurality of synchronization signal trains in the allocated time slots of the plurality of synchronization signal trains.
J first serial-to-parallel conversion circuits for converting from columns to P columns of parallel signals, and 1 for storing the K third synchronization circuit output signals in assigned time slots of a plurality of synchronization signal sequences, respectively.
K second serial-parallel conversion circuits for converting from columns to Q columns of parallel signals; output signals of the I first synchronization circuits; output signals of the J first conversion circuits; According to the frame format of the digital multiplex conversion, the output signals of the K second conversion circuits, the frame synchronization signal from the timing generation circuit, and the other auxiliary transmission line signals are assigned, and assigned time slots for medium-speed or low-speed digital signals. And R multiplexing circuits (R is an integer of 1 or more) for multiplexing in a part of the digital multiplex conversion circuit.