JPH0632141B2 - Intermittent drive circuit for photoelectric smoke detector - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an intermittent drive circuit for a photoelectric smoke detector.

[Prior Art] FIG. 11 shows a conventional example of a photoelectric smoke detector (Japanese Patent Publication No. 60-14).
FIG. 398). In the figure, l ₁ ,
l ₂ is a sensor line, which is connected to the receiver. The receiver is supplied with DC power supply voltage between the sensor lines l _1, l _2, when between sensor lines l _1, l ₂ is short-circuited, originating a fire alarm signal by detecting an increase in the line current To inform. 1 is a diode bridge, the AC input terminals of which are sensor lines l ₁ , l ₂
The DC output terminal is connected to the internal circuit of the sensor. The diode bridge 1 may be omitted, but it is provided so that a worker can normally operate even when the sensor lines l ₁ and l ₂ are wired in reverse polarities during construction. 2 is a switching circuit, which is composed of a self-holding circuit composed of thyristor elements and transistors, is turned on by a trigger signal from the counting circuit 12, short-circuits the sensor lines l ₁ and l _2, and sends a smoke detection signal to the receiver. It is what is sent. Reference numeral 3 denotes a constant voltage circuit, which converts the DC voltage obtained at the DC output terminal of the diode bridge 1 into a predetermined constant voltage and supplies it to the internal circuit. Reference numeral 4 is an oscillation circuit, which generates a reference clock signal. A timing control circuit 5 divides the reference clock signal from the oscillation circuit 4 to generate a light emission control signal for controlling the light emission timing of the light emitting element 6. Reference numeral 6 is a light emitting element composed of an LED (light emitting diode). A drive circuit 7 intermittently drives the light emitting element 6 in accordance with a light emission control signal output from the timing control circuit 5. Reference numeral 8 denotes a light receiving element, which receives a weak pulsed light generated by the pulsed light from the light emitting element 6 hitting and scattering smoke particles. An amplifier 9 amplifies a weak electric signal from the light receiving element 8. Reference numeral 10 denotes a comparator, which compares the output signal from the amplifier 9 with the reference signal from the reference voltage source 11 to determine the presence or absence of smoke, and to generate an output signal when it is determined to be smoke inflow. A reference voltage source 11 supplies a reference signal to the comparator 10 for determining the presence or absence of smoke. Reference numeral 12 is a counting circuit, which supplies a trigger signal to the switching circuit 2 when the output signal from the comparator 10 is obtained at least twice.

[Problems to be Solved by the Invention] As described above, the photoelectric smoke detector emits light of high brightness from the light emitting element 6 in order to detect weak scattered light due to invasion of smoke by the light receiving element 8. There is a need to. If the light emitting element 6 is continuously driven, the power consumption increases, so it is desirable to intermittently drive the light emitting element 6 as described above.
It is necessary to control the drive current so that the amount of light emission of is reduced with a predetermined negative gradient with respect to the temperature change, and therefore the drive circuit 7 handles the analog potential. In such a circuit that handles an analog potential, a current generally flows from the power supply line even during a pause period of intermittent driving, and therefore, even if intermittent driving is performed, the effect of reducing current consumption is small. Therefore, during the rest period of intermittent drive,
It is conceivable that no current flows in the circuit for generating the analog potential. However, in that case, there is a possibility that the analog potential may fall into an unstable state when shifting to the pause period of the intermittent drive, and heat is generated in the transistor for passing a current to the light emitting element 6, or switching loss occurs. there is a possibility.

Japanese Patent Application Laid-Open No. 54-26697 discloses a circuit configuration of an intermittent drive circuit for a photoelectric smoke detector, in which a current does not flow in a circuit for generating an analog potential during a pause period of intermittent drive. However, in the circuit configuration disclosed in this publication, it is necessary to interpose two transistors in series with the light emitting element, and a large current for driving the light emitting element flows through each transistor, resulting in a large power loss. There is a drawback that In particular, the current of the circuit for generating the analog potential and the current of the light emitting element simultaneously flow in one of the two transistors,
It is also necessary to increase the base drive current, which increases power loss.

The present invention has been made in view of such a point, and an object of the present invention is to reliably cut off the power supply current in the pause section in the intermittent drive circuit of the photoelectric smoke detector, and Prevents unstable operation when transitioning,
In addition, the power loss due to the transistor used for intermittent driving is also reduced.

[Means for Solving the Problems] In the intermittent drive circuit of the photoelectric smoke detector according to the present invention, in order to solve the above problems, as shown in FIG. The drive circuit is intermittently driven based on the control signal LEDON for intermittent driving of the light emitting element 6 of the photoelectric smoke sensor, which is supplied with power by the potential difference between _CC and the second power supply line V _SS1. Based on the control signal LEDON for control, the light-emitting element 6 is controlled to be turned off during the rest period and turned on during the driving period of the light-emitting element 6, and between the first and second power supply lines V _CC and V _SS1 . ,
The first transistor Tr ₆ connected in series with the constant voltage element ZD ₃ and the first resistance element R ₆ and the analog potential generated in the constant voltage element ZD ₃ when the first transistor Tr ₆ is on are The second transistor Tr ₇ is connected to the light emitting element 6 and the second resistance element R ₇ in series between the first and second power supply lines V _CC and V _SS1.
And is connected in parallel to the constant voltage element ZD ₃ ,
An insulated gate transistor Tr ₁₀ is controlled so that it is turned off during a drive period of the light emitting element 6 and turned on during a rest period of the light emitting element 6 based on a control signal for intermittent driving. Is.

[Operation] According to the present invention, as described above, in the intermittent drive circuit of the photoelectric smoke detector, the circuit for handling the analog potential is intermittently driven by the control signal LEDON from the outside, and the intermittent drive is stopped. Is configured so that no current flows. Therefore, even if the current consumption is large in the section where the control signal LEDON is at “High” level, the control signal L
If the section where EDON is at the "Low" level is sufficiently long, the current consumption is greatly reduced.

In addition, even during the pause period of the intermittent drive, the power supply line V
_{The CC} and the power supply line V _SS1 are charged to a predetermined potential difference and do not drop the power supply voltage itself. Therefore, when the control signal LEDON becomes “High” level, the analog potential becomes a predetermined valid state. The time required to reach it can be shortened. Therefore, the period during which the control signal LEDON is at the “High” level can be shortened, and in this respect as well, low current consumption can be achieved.

In this way, the power supply line V
_{In the case where the CC} and the power supply line V _SS1 are charged to a predetermined potential difference, the transistor Tr ₇ for driving the light emitting element 6 must be dropped unless the analog potential is drastically dropped when shifting from the driving section to the rest section. Becomes an intermediate state between the ON state and the OFF state, which may cause heat generation of the transistor Tr ₇ or power loss due to switching. Therefore, in the drive circuit shown in FIG. 1, the control signal LEDO
When N shifts from "High" level to "Low" level,
The insulated gate transistor Tr ₁₀ is turned on to abruptly change the analog potential generated at both ends of the constant voltage element ZD _{3 to} the potential of the power supply line V _SS1 , thereby driving the light emitting element 6. The base potential of the bipolar transistor Tr ₇ for reverse biasing is reverse biased by the forward voltage drop (n−1) × V _F of the (n−1) diode array, and rapidly shifts to the off state. Therefore, an intermediate state between the ON state and the OFF state does not occur,
Power loss due to heat generation and switching of the transistor Tr ₇ can be reduced. Also, an insulated gate transistor Tr
Once the gate input capacitance is charged, ₁₀ can maintain the low impedance state without continuing to flow the gate drive current any more, so the power supply current during the idle period can be cut off. Even if the intermittent driving idle period is long, the current consumption does not increase.

[Embodiment] FIG. 2 is a diagram showing a circuit configuration of an embodiment of the present invention.
In the block diagram of the conventional example shown in FIG. 11, the circuit configurations of the switching circuit 2, the constant voltage circuit 3, and the drive circuit 7 are specifically illustrated. First, the switching circuit 2 includes a PNP transistor Tr ₁ and an NPN transistor Tr ₂ , which are connected so as to form a self-holding circuit. The emitter of the PNP transistor Tr ₁ is
Connected to the positive output terminal of diode bridge 1,
The emitter of the transistor Tr ₂ is connected to the negative output terminal of the diode bridge 1. PNP transistor Tr ₁
Is connected to the collector of the NPN transistor Tr _{2 and} the collector of the PNP transistor Tr ₁ is connected to the base of the NPN transistor Tr ₂ . Resistors R ₁ and R ₂ are connected in parallel between the base and emitter of each of the transistors Tr ₁ and Tr ₂ . The base of the NPN transistor Tr ₂ serves as a trigger terminal and is connected to the output of the counting circuit 12 via the diode D ₀ .

When the output signal OUT of the counting circuit 12 becomes “High” level, the NPN transistor Tr is passed through the diode D _0.
2 to the base current flows, the base current flows in the PNP transistor Tr ₁ by the collector current of the NPN transistor Tr _2, thereafter, the base current of the NPN transistor Tr ₂ is supplied by the collector current of the PNP transistor Tr _1, the switching circuit Since the self-holding state (latch-up state) is established and the DC output terminals of the diode bridge 1 are short-circuited, the sensor lines l ₁ and l ₂ are short-circuited. As a result, the line current flowing through the sensor lines l ₁ and l ₂ increases, and the receiver connected to the other ends of the sensor lines l ₁ and l ₂ detects the smoke detection signal. After that, the switching circuit 2 maintains the self-holding state until the reset switch is operated on the receiver side to interrupt the line current flowing through the sensor lines l ₁ and l ₂ .

Next, the configuration of the constant voltage circuit 3 will be described. The constant voltage circuit 3 includes three NPN transistors Tr ₃ , Tr ₄ , Tr ₅ . The collector of the transistor Tr ₃ is connected to the positive output terminal of the diode bridge 1. Transistor Tr ₃
The base of the diode bridge is connected via a first constant voltage element composed of a series circuit of Zener diode ZD ₁ and diode D ₁ and a second constant voltage element composed of a series circuit of Zener diode ZD ₂ and diode D _2. 1 is connected to the negative output terminal. The diodes D ₁ and D ₂ are provided to compensate the temperature coefficient of the Zener voltage of the Zener diodes ZD ₁ and ZD ₂ . A current flows from the positive output terminal of the diode bridge 1 to the first and second constant voltage elements via the bias resistor R ₃ connected between the collector and the base of the transistor Tr ₃ . As a result, the zener voltage V _ZD1 of the zener diode ZD ₁ is applied across the first constant voltage element.
A constant voltage (V _ZD1 + V _F ) is generated by adding the forward drop voltage V _F of the diode D _{1 and} the forward voltage V _F. Further, a constant voltage (V _ZD2 + V _F ) which is the sum of the Zener diode ZD ₂ Zener voltage V _ZD2 and the forward drop voltage V _F of the diode D ₂ is generated across the second constant voltage element. Therefore, at the base of the transistor Tr ₃ , a voltage (V _ZD1 + V _ZD2 + 2 × V _F ) which is the _{sum of} the voltages across the first and second constant voltage elements is generated. The base-emitter voltage of the transistor Tr ₃ is V
_{Assuming BE3} , the emitter voltage of the transistor Tr ₃ is (V
_ZD1 + V _ZD1 + 2 × constant at V _F -V _BE3). This voltage is charged in the power source capacitor C ₁ through the low resistance R ₄ and becomes a power source voltage between the power source lines V _CC and V _SS1 . Also,
When the base-emitter voltage of the transistor Tr ₅ is V _BE5 , the emitter voltage of the transistor Tr ₅ is (V _ZD2 +
It becomes constant at V _F -V _BE5). This voltage is charged in the power supply capacitor C ₂ and becomes a power supply voltage between the power supply lines V _DD and V _SS2 . The transistor Tr ₄ is provided in order to prevent overcurrent, and if the emitter current of the transistor Tr ₃ is at an appropriate level, the voltage generated across the low resistance R ₄ is small, so the transistor Tr ₄ does not operate. When the emitter current of the transistor Tr ₃ increases abnormally, the low resistance R
_A base current flows through the transistor Tr ₄ due to the voltage generated across the transistor _4, and the base current of the transistor Tr ₃ is shunted between the collector and the emitter of the transistor Tr ₄ to limit the emitter current of the transistor Tr ₃ .

Next, the configuration of the drive circuit 7 will be described. The drive circuit 7 includes two NPN transistors Tr ₆ , Tr ₇ and 3
When the light emission control signal LEDON from the timing control circuit 5 is at “High” level, the drive current I _{6 is} supplied to the light emitting element 6 including the NMOS transistors Tr ₈ , Tr ₉ , Tr ₁₀ and the PMOS transistor Tr _11. When the light emission control signal LEDON is at the “Low” level, the drive circuit 7 itself is in a high impedance state in which the drive circuit 7 itself consumes no current.

Light emission control signal LEDON from the timing control circuit 5
Is applied to the gate of the NMOS transistor Tr ₈ . The source of the NMOS transistor Tr ₈ is the power line V
_It is connected to _SS1 and its drain is connected to the power supply line V _CC via a biasing resistor R ₅ . Resistor R ₅ and NMO
The drain of the S-transistor Tr ₈ is connected to the NMOS transistors Tr ₉ , Tr ₁₀ and the PMOS transistor Tr _11.
Is connected to the gate. NMOS transistor T
The sources of r ₉ and Tr ₁₀ are connected to the power supply line V _SS1 and PM
The source of the OS transistor Tr ₁₁ is connected to the power supply line V _CC . The drain of the NMOS transistor Tr _{9 and} the drain of the PMOS transistor Tr ₁₁ are commonly connected to the base of the NPN transistor Tr ₆ . The collector of the NPN transistor Tr ₆ is connected to the power supply line V _CC ,
The emitter is connected to the cathode of the Zener diode ZD ₃ via the resistor R _6, and the anode of the Zener diode ZD ₃ is connected to the power supply line V _SS1 . The drain of the NMOS transistor Tr ₁₀ is connected to the cathode of the Zener diode ZD ₃ , and the base of the NPN transistor Tr ₇ is connected to the cathode of the Zener diode ZD _{3 through} the (n−1) diode series array. The emitter of the NPN transistor Tr ₇ is connected to the power supply line V _SS1 via the resistor R ₇ . The collector of the NPN transistor Tr ₇ is connected to the cathode of the light emitting element 6, and the anode of the light emitting element 6 is connected to the power supply line V _CC .

The operation of the drive circuit 7 will be described below. The light emission control signal LEDON from the timing control circuit 5 is “Hig
At the "h" level, the NMOS transistor Tr ₈ is turned on, and the NMOS transistors Tr ₉ , Tr ₁₀ and PM are
Since the gate potential of the OS transistor Tr ₁₁ drops,
The NMOS transistors Tr ₉ and Tr ₁₀ are in the off state, PMO
The S transistor Tr ₁₁ is turned on. Therefore, NPN
The base potential of the transistor Tr ₆ rises, and current flows through the series circuit of the resistor R ₆ and the Zener diode ZD ₃ via the collector and emitter of the NPN transistor Tr ₆ . As a result, a voltage equal to the Zener voltage V _ZD3 is generated at the cathode of the Zener diode ZD ₃ . The forward voltage drop (n-1) voltage obtained by subtracting a × V _F of the voltage (n-1) pieces of the diode series array, is applied to the base of the NPN transistor Tr _7, NPN transistor Tr ₇ is turned And the drive current I _{6 is} applied to the light emitting element _6.
Flows.

Next, the light emission control signal LED from the timing control circuit 5
When ON becomes “Low” level, the NMOS transistor Tr ₈ is turned off and the bias resistor R ₅ causes N.
Since the gate potentials of the MOS transistors Tr ₉ and Tr ₁₀ and the PMOS transistor Tr ₁₁ rise, the NMOS transistors Tr ₉ and Tr ₁₀ are in the ON state and the PMOS transistor T
r ₁₁ is turned off. Therefore, the NPN transistor Tr ₆
Of the NPN transistor Tr ₆ does not flow through the collector-emitter of the NPN transistor Tr ₆ . Further, both ends of the Zener diode ZD ₃ are connected to the NMOS transistor Tr ₁₀
Therefore, the cathode potential of the Zener diode ZD ₃ is lowered, the NPN transistor Tr ₇ is turned off, and the drive current I ₆ of the light emitting element ₆ is stopped.

The power-on reset circuit 13 includes a power supply capacitor C ₁
Of the power-on reset signal RE to the oscillation circuit 4, the timing control circuit 5, and the count circuit 12
Supply SET. The analog signal processing circuit 14 has a first
It includes an amplifier 9, a comparator 10 and a reference voltage source 11 shown in FIG. The oscillator circuit 4 supplies the reference clock signal OSC to the timing control circuit 5. Timing control circuit 5
Divides the reference clock signal OSC into the drive circuit 7
To the analog signal processing circuit 14 and the timing control signals PHI1 and PHI
HI2 is supplied, and the reset signal RS is supplied to the count circuit 12.
It supplies T and the upclock signal UPCLK. The comparison output signal COMP is supplied from the analog signal processing circuit 14 to the count circuit 12. The oscillator circuit 4, the timing control circuit 5, the analog signal processing circuit 14, and the count circuit 12 operate at a low voltage and consume little current, so that power is supplied from the capacitor C ₂ . On the other hand, the drive circuit 7 of the light emitting element 6 instantaneously consumes a large amount of current, so that power is supplied from the capacitor C ₁ . In this way, by separating the power supply line V _SS of the drive circuit 7 from the power supply line V _DD of the other circuit, there is no possibility that the power supply voltage of the other circuit will momentarily drop when the light emitting element 6 emits light. It is possible to prevent malfunction of the circuit.

FIG. 3 is a circuit diagram specifically showing the configurations of the oscillation circuit 4, the timing control circuit 5, the analog signal processing circuit 14, and the count circuit 12.

First, the oscillator circuit 4 includes a capacitor C _T and a resistor R _T for setting a time constant, two inverters G ₁ and G _2, and a NAND gate G ₃ for controlling oscillation. One input of the NAND gate G ₃ is connected to the output of the inverter G ₁ via the resistor R _T, and is also connected to the input of the inverter G _{1 and} the output of the inverter G ₂ via the capacitor C _T. NAN
The output of the D gate G ₃ is connected to the input of the inverter G ₂ ,
The power-on reset signal RESET is input to the other input of the NAND gate G ₃ via the inverter G ₄ . When the power-on reset signal RESET becomes "Low" level, the output of the inverter G ₄ becomes a "High" level, so NAND gate G ₃ is a signal passable condition, the output of the inverter G ₂ is, R _T resistor And a reference clock signal OSC having a period determined by the time constant of the capacitor C _T is obtained.

The reference clock signal OSC is supplied to the timing control circuit 5
Is input to the frequency dividing circuit 5a. Frequency divider circuit 5a
Consists of 15 stages of D flip-flops connected in series,
The D flip-flop of each stage has its inverted output connected to its own data input D and also to the clock input CLK of the next stage. The reference clock signal OSC is supplied to the clock input CLK of the first stage D flip-flop, and the divided output B ₁₅ of the reference clock signal OSC is obtained from the output Q of the last stage D flip-flop.

The frequency-divided output B ₁₅ is input to the shift register circuit 5b in the timing control circuit 5. The shift register circuit 5b is formed by connecting seven stages of D flip-flops in cascade, and the output Q of each stage D flip-flop is connected to the data input D of the next stage. The frequency-divided output B _{15 of the} frequency-dividing circuit 5a is supplied to the data input D of the D flip-flop in the first stage. The output Q (divided output B ₂ ) of the D flip-flop of the second stage in the frequency dividing circuit 5a is supplied to the clock input CLK of the D flip-flop of each stage.

The power-on reset signal RESET is supplied to the reset input R of each D flip-flop in the frequency dividing circuit 5a and the shift register circuit 5b.

The output of the third stage to 7-stage in the shift register circuit 5b of the D flip-flop _{Q 3, 3, Q 4,} Q 5, 5, 6, 7 and divided output B ₁₄ is a frequency dividing circuit 5a, the timing control circuit 5 are input to AND gates G _{5 to} G ₉ of the logic circuit 5 c in FIG. ₅ to control signals PHI 1, PHI 2, L.
EDON, RST, and UPCLK are generated respectively.

Next, the configuration of the analog signal processing circuit 14 including the amplifier 9, the comparator 10 and the reference voltage source 11 will be described.

The amplifier 9 is formed by connecting three stages of operational amplifiers OP ₁ , OP ₂ and OP ₃ in cascade, and the reference voltage Vr from the reference voltage circuit 15 is applied to the non-inverting input of each operational amplifier. The cathode of the light receiving element 8 formed of a silicon photodiode (SPD) is connected to the inverting input of the first stage operational amplifier OP ₁ . The anode of the light receiving element 8 is the power supply line V _SS2
It is connected to the. Therefore, the PN junction of the light receiving element 8 is reversely biased, and the photocurrent flowing in the reverse direction to the PN junction due to light irradiation is detected as a voltage signal by the operational amplifier OP ₁ . For this reason, the operational amplifier O
A high resistance is used as the feedback resistor R ₈ connected between the output of P ₁ and the inverting input. Second stage operational amplifier OP
₂ constitutes a voltage amplification circuit, and its voltage amplification factor is
It is determined by the ratio of the input resistance R ₉ and the feedback resistance R ₁₀ . The third stage operational amplifier OP ₃ also constitutes a voltage amplifier circuit, and the voltage amplification factor thereof is determined by the ratio of the input resistance R ₁₁ and the feedback resistance R ₁₂ . The output of the operational amplifier OP ₃ is connected to one end of the capacitor C ₃ for DC cut, the other end of the capacitor C ₃ is connected to the non-inverting input of the operational amplifier OP _4.
The output of the operational amplifier OP ₄ is fed back to its inverting input, and thus the operational amplifier OP ₄ is a buffer amplifier acting as an impedance converter. The output of the operational amplifier OP ₄ is passed through a low-pass filter composed of a resistor R ₁₃ and a capacitor C ₄ , and an operational amplifier O for comparator O
It is connected to the non-inverting input of P ₅ . The other end of the DC cut capacitor C ₃ is connected to the output of the reference voltage circuit 15 via the analog switch SW ₁ . The output of the reference voltage circuit 15 is applied to the non-inverting input of the operational amplifier OP ₆ . The output of the operational amplifier OP ₆ is a resistor R
It is connected to the power supply line V _SS2 via ₁₄ and the resistor R ₁₅ . The connection point between the resistors R ₁₄ and R ₁₅ is fed back to the inverting input of the operational amplifier OP ₆ . The reference voltage V _REF obtained from the resistor R ₁₄ is applied to the inverting input of the operational amplifier OP ₅ for the comparator. The output of the operational amplifier OP ₅ is N
RS flip-flop 1 including OR gates G ₁₀ and G ₁₁
It is considered as a set input for 2a. The reset signal RST output from the AND gate G ₈ is supplied to the reset input of the RS flip-flop 12a. Also,
The output of the RS flip-flop 12a is used as the up / down selection signal UDS of the up / down counter 12b. The reset input R of the up-down counter 12b, the power-on reset signal RESET is supplied to the up clock input UPCLK, up clock signal UPCLK output from the AND gate G ₉ are supplied.

FIG. 4 shows the circuit configuration of the count circuit 12. The count circuit 12 includes an RS flip-flop 12a including the NOR gates G ₁₀ and G ₁₁ described above, and an up / down counter 12b. Up-down counter 12b
Has two D flip-flops. The power-on reset signal RESET is supplied to the reset input R of each D flip-flop, and the up clock signal UPCLK is supplied to the clock input CKL.
The outputs Q ₁₀ and Q ₂₀ of each D flip-flop are AN
It is input to the D gate G _12, and the output of the AND gate G ₁₂ becomes the output signal OUT of the count circuit 12. The data inputs D ₁₀ and D ₂₀ of each D flip-flop are the up / down selection signal UDS and the output Q ₁₀ of each D flip-flop.
When the detection signal COMP of smoke scattered light generated at each of the logic circuits G ₁₃ and G _{14 respectively} based on Q ₂₀ has become “High” level three times in the past, the output signal OUT becomes “High” level. , The switching circuit 2 is configured to be triggered.

By the way, in the drive circuit 7 shown in FIG.
If the zener voltage of the zener diode ZD ₃ is V _ZD3 ,
The driving current of the light emitting element 6 is I ₆ = {V _ZD3 − (n−1) × V _F −V _BE7 } / R ₇ = (V _ZD3 −n × V _F ) / R ₇ . However, the base-emitter voltage V _BE7 of the transistor Tr ₇ is equal to the forward drop voltage V _F of each of the (n−1) diodes. As is clear from the above, in the drive circuit 7 shown in FIG. 2, the temperature characteristic of the base-emitter voltage V _BE7 of the transistor Tr ₇ affects the temperature characteristic of the drive current I ₆ of the light emitting element 6. It will be.

FIG. 5 shows another circuit example of the drive circuit 7. As compared with the drive circuit 7 shown in FIG. 2, a current mirror circuit including PNP transistors Tr ₁₄ and Tr ₁₅ is added, and the base-emitter voltage V _BE7 of the transistor Tr _{7 is applied to} the base-emitter of the transistor Tr _17. The drive current I _{6 of the} light emitting element 6 is canceled by the voltage V _BE17.
The temperature characteristic of is different only in that it is determined only by the zener diode ZD ₃ and (n-1) diodes.

First, when the light emission control signal LEDON is at the “High” level, as described above, the NMOS transistor Tr ₈ is on, the NMOS transistors Tr ₉ and Tr ₁₀ are off, and P
Since the MOS transistor Tr ₁₁ is turned on, PM
The gate potentials of the OS transistor Tr ₁₂ and the NMOS transistor Tr ₁₃ rise, the PMOS transistor Tr ₁₂ turns off and the NMOS transistor Tr ₁₃ turns on. Therefore, the PNP transistor Tr ₁₄ has a resistor R ₁₆
The constant current determined by the current flows through the PNP transistor Tr ₁₅ and the same current flows into the base of the transistor Tr ₆ . At this time, the gate potential of the NMOS transistor Tr ₁₆ is low, NMOS transistor Tr ₁₆ is OFF state, NPN transistor Tr ₁₇ is made ready for operation. When the voltage across the resistor R ₆ rises, the NPN transistor Tr ₁₇ diverts the base current of the NPN transistor Tr ₆ to reduce the voltage across the resistor R ₆ and the base-emitter voltage V _{BE17 of the} transistor Tr _17. Negative feedback control is performed so that it becomes equal to. Therefore, in the drive circuit 7, the drive current I ₆ of the light emitting element 6 is: I ₆ = {V _VD3 − (n−1) × V _F } / R ₇ . This is because the base-emitter voltage V _BE7 of the transistor Tr _{7 and} the base-emitter voltage V _{BE17 of the} transistor Tr ₁₇ cancel each other out.

Next, when the light emission control signal LEDON is at the “Low” level, as described above, the NMOS transistor Tr ₈ is off, the NMOS transistors Tr ₉ and Tr ₁₀ are on, and P
Since the MOS transistor Tr ₁₁ is turned off, PM
The gate potentials of the OS transistor Tr ₁₂ and the NMOS transistor Tr ₁₃ drop, the ROMS transistor Tr ₁₂ is turned on and the NMOS transistor Tr ₁₃ is turned off. Therefore, no current flows through the PNP transistor Tr ₁₄ and no current flows through the PNP transistor Tr ₁₅ . Since the NMOS transistor Tr _16, Tr ₁₀ is turned on, the base potential of the NPN transistor Tr _6, Tr ₇ decreases, the NPN transistor Tr _6, Tr ₇ is completely turned off. Therefore, the control signal PHI1 is "Lo".
At the w "level, no current flows from the power supply line V _CC to the power supply line V _SS1 .

Here, the (n-1) diodes used in the drive circuit 7 are the temperature coefficient of the Zener voltage V _ZD3 of the Zener diode ZD ₃ , the temperature coefficient of the light emitting efficiency of the light emitting element 6, the light receiving efficiency of the light receiving element 8 and the current −. In consideration of the temperature coefficient of the high resistance R ₈ for voltage conversion, the number is selected so that the temperature coefficients on the light emitting side and the light receiving side are almost zero as a whole. The specific method will be described later.

Next, to illustrate a specific circuit configuration of the operational amplifier OP ₁ ~OP ₆ in Figure 6. This operational amplifier includes MOS transistors Tr _{18 to} Tr ₃₀ , a resistor R _17, and an inverter G ₁₅ .
When the control signal PHI1 is at "High" level, a voltage signal obtained by amplifying the difference between the voltages applied to the input terminals IN1 and IN2 is generated at the output terminal OUT1, and the control signal PH1 is generated.
When I1 is at "Low" level, the output terminal OUT
1 goes to "Low" level and power lines V _DD and V
_The feature is that it operates so that no current flows during _SS2 . The operation will be briefly described below. First, when the control signal PHI1 is at the “High” level, the gate potentials of the PMOS transistor Tr ₁₈ and the NMOS transistor Tr ₂₀ rise, so that the PMOS transistor Tr ₁₈ is turned off and the NMOS transistor Tr ₁₈ is turned off. The transistor Tr ₂₀ is turned on. Therefore, the gate potentials of the PMOS transistors Tr ₁₉ , Tr ₂₁ , Tr ₂₆ , Tr ₂₈ decrease, and they function as resistance elements. Therefore, the input terminal IN
The voltage corresponding to the difference between the voltages applied to 1 and IN2 is M
It is generated by a differential amplifier composed of OS transistors Tr _{22 to} Tr ₂₅ , and this voltage is generated by the MOS transistors Tr ₂₇ , Tr ₂₇ .
It is amplified at ₂₉ two stages and output to the output terminal OUT1.
At this time, the MOS transistors Tr ₂₆ and Tr ₂₈ act as load resistances of the MOS transistors Tr ₂₇ and Tr ₂₉ . Next, when the control signal PHI1 becomes "Low" level, PM
Since the gate potentials of the OS transistor Tr ₁₈ and the NMOS transistor Tr ₂₀ decrease, the PMOS transistor Tr 20
₁₈ is turned on, and the NMOS transistor Tr ₂₀ is turned off. Therefore, the PMOS transistors Tr ₁₉ , Tr
_The gate potentials of ₂₁ , Tr ₂₆ and Tr ₂₈ rise, and the gates are cut off. Therefore, no current flows from the power line V _DD to the power line V _SS2 . Further, the inverter G ₁₅ is supplied with power by the power supply lines V _DD and V _SS2 , but since all the inverters of this embodiment are CMOS inverters, no current flows after the state transition. Therefore, when the control signal PHI1 is at "Low" level, the operational amplifier O
P _{1 to} OP ₆ consume no current at all.

Next, FIG. 7 shows a specific circuit configuration of the reference voltage circuit 15. This circuit outputs an inverted signal of the control signal PHI1.
Then, when ▼ is at the “High” level, the reference voltage Vr is generated at the output terminal OUT2, and when the control signal PHI1 is at the “Low” level, the current from the power line V _DD to the power line V _SS2 is cut off. It is characterized by operating as described above. Hereinafter, the control signal PH
The principle that the reference voltage Vr is generated as a constant voltage when I1 is at "High" level will be described.

_Assuming that the base-emitter voltages of the transistors Tr ₃₆ and Tr ₃₉ are V _EB36 and V _EB39 and the current flowing through the transistors Tr ₃₉ and Tr ₃₆ is I, then V _BE36 = V _BE39 + I · R. If the ratio of the emitter area of the transistor Tr _{36 and} the emitter area of the transistor Tr ₃₉ is selected to be 1: S, the collector currents Ic ₃₆ and Ic ₃₉ of the respective transistors are as follows.

Ic ₃₆ = Is · exp (V _BE3 / V _T ) Ic ₃₉ = S × Is · exp (V _BE2 / V _T ), where Is is the saturation current, V _T = kT / q, k is the Boltzmann constant, and q is Electronic charge, T is absolute temperature.

Substituting this into the equation, I = (V _T / R) lnS The number of transistors Tr ₄₁ , Tr ₄₂ , ... Connected in series is m.
In this case, Vo = I · kR + mV _BE = mV _BE + (V _T / R) lnS Choose m = 2, S = 2, Then, k = 67.89 Therefore, if R = 1 kΩ, kR becomes 67.9 kΩ, and the constant voltage circuit has a temperature coefficient of 0. Thus, m
And S can be selected appropriately to keep the output voltage Vr constant.

Further, in this embodiment, the light emitting element 6 and the light receiving element 8,
By adjusting the temperature characteristic of the drive current I ₆ of the drive circuit 7 as follows based on the temperature coefficient of the internal resistance voltage Vr of the high resistance R ₈ for current-voltage conversion and the reference voltage circuit 15, the light receiving output Vo Realizes a photodetector circuit that does not change with temperature.

Receiving the output current I ₈ of the light receiving element 8, the first stage of the operational amplifier O
It flows through the high resistance R ₈ of P ₁ and is converted into a voltage signal. When the output voltage of the reference voltage circuit 15 is Vr, the operational amplifier OP ₁
The output voltage Vo of the above becomes Vo = Vr−I ₈ · R ₈ . When the partial differential coefficient with respect to the change ∂T of the temperature T is obtained for both sides, here, So that Here, it is assumed that the high resistance R ₈ for current-voltage conversion is a diffusion resistance of the integrated circuit, and the temperature variation (∂R ₈ / ∂
T) / R ₈ is assumed to be 2000 ppm / ° C. Further, the temperature variation of the light receiving output current I ₈ of the light receiving element 8 (∂I ₈ / ∂T) / I
Assuming ₈ is -2000ppm / ° C, Becomes However, if the light receiving element 8 is a general silicon photodiode (SPD), the temperature coefficient of the light receiving output current I ₈ is positive, and the temperature variation of the output voltage Vo can be zero as described above. Can not. Therefore,
The amount of light emitted from the light emitting element 8 may be decreased as the temperature rises so that the temperature variation of the light receiving output current I ₈ of the light receiving element 8 has a negative gradient. That is, the light receiving output current I ₈ of the light receiving element 8 is proportional to the quantity of light from the light emitting element 6, since the quantity of light from the light emitting element 6 is considered to be proportional to the drive current I _6, with increasing temperature the quantity of light from the light emitting element 6 It is thought that it should be reduced. Now, assuming that the temperature coefficient of the light receiving output current of the light receiving element 8 alone is 3000 ppm / ° C., and the temperature coefficient of the light emission amount of the light emitting element 6 is −5000 ppm / ° C., (∂Vo / ∂T)
It can be approximated to 0.

Next, the temperature characteristics of the drive circuit 7 will be described. In FIG. 2, the Zener diode ZD ₃ Zener voltage is V
_ZD3 , base-emitter voltage of transistor Tr ₇ and
Assuming that the forward drop voltage of each of the (n-1) diode series arrays is V _F , the current I ₆ flowing through the light emitting element ₆ is I ₆ = {V _ZD3 −n · V _F } / R ₇ . When the partial differential coefficient with respect to the change ∂T of the temperature T is obtained for both sides, Now, the temperature variation of the luminous efficiency of the light emitting element 6 is −6250 ppm.
/ ° C. At this time, in the temperature range of −15 ° C. to 65 ° C., the light emission amount of the light emitting element 6 varies from + 25% to −25%. Quantity of light from the light emitting element 6 decreases with increasing temperature, but decreases the light reception output current I ₈ of the light receiving element 8, the light receiving output current of the light receiving element 8 alone, current - resistance of the high resistance R ₈ for voltage conversion The value has the property of increasing conversely with increasing temperature. Therefore, the light emission amount of the light emitting element is -5000.
If it is ppm / ° C., the temperature coefficient (∂Vo / ∂T) of the output voltage Vo of the light receiving circuit can be set to 0, so that the temperature coefficient of the drive current I ₆ in the drive circuit 7 of the light emitting element 6 is 1250ppm / If the temperature is set to ° C, the temperature coefficient of the entire circuit can be zero.

Here, the resistor R ₇ in the equation is a discrete portion whose temperature coefficient can be ignored, and V _ZD3 = 6.9 V, ∂V _ZD3 / ∂T
_{= 3mV / ℃, ∂V F /} ∂T = -2mV / ℃, V F = 0.7
If it is V, Value may be 1250 ppm / ° C. = 1.25 × 10 ⁻³ . At this time, n = 1.596≈2.
Therefore, the number of diodes may be (n-1) = 1.

As described above, by appropriately selecting the number of (n-1) diodes in the drive circuit 7, the temperature coefficient of the output voltage Vo of the photodetector circuit can be made zero.

In the case of using the other drive circuit 4 shown in Fig. _{5, I 6 = {V ZD3 +} V BE - (n-1) V F -V BE} / R 7 = {V ZD3 - (n- 1) V _F } / R ₇ , and n = 3 if the same calculation as above is performed. Therefore, the number of diodes should be (n−1) = 2.

In this way, in this embodiment, the photodetector circuit having a constant temperature coefficient of the output voltage is realized.

A time chart of the above circuit is shown in FIG. When the frequency of the reference clock signal OSC from the oscillator circuit 4 is 10 kHz, the frequency-divided output B ₁₅ of the 15-stage frequency divider circuit 5a becomes a clock signal with a period of 3.2768 seconds. This frequency-divided output B ₁₄ is input to the 7-stage shift register circuit 5b and is shifted using the frequency-divided output B ₂ of the second stage of the frequency divider circuit 5a to output Q ₁ to the output of each stage of the shift register circuit 5b. Make Q ₇ . This signal is decoded by the logic circuit 5c, and the control signal PH
I1, PHI2, the light emission control signal LEDON, the up clock signal UPCLK, and the reset signal RST are created.

The control signal PHI1 is a control signal for enabling the analog signal processing circuit 14 including the amplifier 9, the comparator 10, and the reference voltage source 11, and the analog signal processing circuit is in a low level section of the control signal. The power supply current of 14 is cut off to reduce the current consumption. At the same time, the rising control signal PHI2, the analog switch SW ₁ is turned on, to charge the buffer amplifier side of the terminal of the DC blocking capacitor C ₃ to the reference voltage Vo, the result,
Both ends of the capacitor C ₃ become equal to the reference voltage Vo. Control signal PHI2 becomes "Low" level, after the analog switch SW ₁ is turned off, the emission control signal LEDON is "Hig
The h "level is reached, and the drive circuit 7 causes the light emitting element 6
A drive current I ₆ flows through this. The current consumption of the drive circuit 7 also becomes zero in the section where the light emission control signal LEDON is at the “Low” level. The output signal of the light receiving element 8 obtained by receiving the scattered light of smoke by the light emission of the light emitting element 6 is amplified by the amplifier 9, and the received light signal CPLS is the reference voltage V _{REF of the} comparator 10.
When the above is reached, the comparison output signal COMP of the comparator 10 becomes the "High" level. This signal COMP is latched by the RS flip-flop 12a of the count circuit 12 and taken into the up / down counter 12b of the count circuit 12 by the up clock signal UPCLK when the up / down selection signal UDS is at "High" level. In the count circuit 12, the count output signal OUT becomes “High” level only when the light reception signal CPLS exceeds the reference voltage V _REF for three consecutive times. The time chart of this operation is shown in FIG. The number of consecutive times can be freely set in the counter 12b by the circuit configuration. When the count output signal OUT becomes "High" level, the trigger signal is supplied to the switching circuit 2 and the sensor circuit is connected.
A short circuit occurs between l ₁ and l ₂ , and the smoke detection signal is sent as a current signal to the receiver side. The diode D ₀ connected to the trigger terminal of the switching circuit 2 is inserted to ensure the self-holding state even when the count output signal OUT returns to the “Low” level during the self-holding operation of the switching circuit 2. It is a thing.

As described above, in this embodiment, when the scattered light due to the smoke flowing into the sensor exceeds the reference value three times in a row, the switching circuit 2 is turned on and the smoke detection signal is sent to the receiver side. Is. Since such sensors are distributed over a wide range and a large number are connected in parallel between the sensor lines l ₁ and l ₂ , it is desirable to suppress the current consumption thereof to a low level. .

Therefore, in the present embodiment, first, in order to reduce the current consumption of the analog signal processing circuit 14, as described above,
Control signal PHI generated by timing control circuit 5
1, the analog signal processing circuit 14 is driven intermittently. The power supply voltage V _{CC is set} to 10 V and V _{DD is set} to 5 V, and the analog signal processing circuit 14 is enabled.
Assuming that the gh "level section is 1.4 msec, even if the entire analog signal processing circuit 14 consumes a current of 10 mA, there is only a 1.4 msec current consumption section once in about 3.2 seconds. 10mA × 1.4msec / 3.2s
Since ec = 4.38 μA, it is possible to significantly reduce power consumption. Further, the drive circuit 7 has the light emission control signal LEDON.
Since no current flows in the section of “Low” level, even if the driving current I _{6 of} 100 mA is applied to the light emitting element 6, the “High” level section of the light emission control signal LEDON is 2
Assuming 00 μsec, 100 mA × 200 μsec / 3.2 s
Since ec = 6.25 μA, it is possible to significantly reduce power consumption.

In addition, the constant voltage circuit 3 and the power-on reset circuit 13
The current consumption is about 7 μA, and the logic circuit part including the timing control circuit 5 and the count circuit 12 has a CMOS structure and consumes less current. Even if this is included with the current consumption (5 μA) of the oscillation circuit 4 of 10 kHz, the total is 5 μA. It is within 10 μA. Therefore, even if all of the above consumption currents are added, the total becomes 4.38 + 6.25 + 7 + 10 = 27.63 μA, which is a low consumption current of 30 μA or less.

Further, in this embodiment, the voltage of the power supply lines V _CC and V _DD is switched on and off to achieve low current consumption for intermittent driving of the analog circuit portion such as the drive circuit 7 and the analog signal processing circuit 14. However, instead of providing a transistor for current cutoff control individually in each analog circuit to cut off the current, each analog circuit is in a valid state compared to the method of turning on and off the voltage of the power supply line. Therefore, the light receiving output of the light receiving element 8 generated by the scattered light due to smoke can be taken up to the counting circuit 12 in a short period of 1.4 msec as a whole. Therefore, the effective time of the analog circuit portion can be shortened, and the current consumption can be significantly reduced as compared with the conventional case.

The sensor circuit of this embodiment as described above is configured as a semiconductor integrated circuit using the dielectric isolation technique. Below, the first
The manufacturing process of the dielectric isolation substrate will be described with reference to FIG. First, an oxide film (SiO ₂ ) is formed on the N ⁻ type single crystal silicon substrate 21 by a well-known semiconductor process method, and a desired portion of the oxide film 22 is etched by a photolithography technique and an oxide film etching technique. Then
Then, anisotropic etching of the silicon crystal is performed with an alkali anisotropic etching solution to form a V-shaped groove.
(See FIG. 10 (a)). After that, a silicon oxide film (S
An insulating film 22 made of iO ₂ ) is formed. Since this silicon oxide film is used as an insulating film, Si ₃ N ₄ or the like may be used for that purpose. A polycrystalline silicon layer 23 serving as a support is formed on the insulating film 22 (see FIG. 10 (b)). The thickness of the polycrystalline silicon layer 23 is not particularly limited, but is set to be approximately the same as the thickness of the single crystal silicon substrate 21. After that, surface polishing is performed from the single crystal silicon substrate 21 side, and polishing removal is performed until the insulating film 22 is exposed (see FIG. 10C). The surface polishing starts with rough lapping, then gradually becomes finer, and at the final stage, mirror finishing by polishing is performed. Through the above steps, a dielectric isolation substrate including a plurality of single crystal silicon regions which are wrapped in the insulating film 22 and exist on the polycrystalline silicon layer 23 like islands is completed. A circuit element is formed in each of the single crystal silicon regions where the island exists.

Due to the integration using the dielectric isolation technology described above, all elements except the power supply capacitors C ₁ and C ₂ , the light emitting element 6 and the resistor R ₃ of the constant voltage circuit 3 can be formed on the same chip, and at the same time small and lightweight. It can be realized. The resistor R ₃ has a high withstand voltage and high resistance, and can be integrated if the problem of increasing the element occupying area is excluded.

[Effect of the Invention] According to the present invention, in the intermittent drive circuit of the photoelectric smoke detector, during the pause period of the intermittent drive, without dropping the power supply voltage between the first power supply line and the second power supply line, The first transistor cuts off energization to the analog potential generation circuit including the constant voltage element and the first resistance element, and
By short-circuiting both ends of the constant voltage element with insulated gate type transistors, the second transistor driven by the analog potential generated at both ends of the constant voltage element is surely turned off, and the current to the light emitting element is cut off. Therefore, the first power supply line and the second power supply line transit to a high impedance state, and the power supply current during the idle period can be cut off without dropping the power supply voltage. Therefore, it is not necessary to secure a time for raising the power supply voltage between the first power supply line and the second power supply line after the drive period of the intermittent drive is started, and thus a predetermined voltage is provided across the constant voltage element. The time until the analog potential is obtained can be shortened, and the effects of both the shortening of the driving period and the interruption of the power supply current in the idle period can be combined, resulting in a significant reduction in current consumption.

In addition, the first power supply line and the second
The high-impedance state between the power supply lines cuts off the power supply current during the pause period to reduce the current consumption, but the part that generates a predetermined analog potential during the intermittent drive period has a low impedance. By fixing the potential to one of the power supply lines as a state, it is possible to prevent unstable operation. Moreover, the use of an insulated gate transistor as a means for bringing the portion that generates the predetermined analog potential into a low impedance state has the advantage that no consumption current flows after the gate input capacitance is charged. The current consumption can be reduced while realizing stable operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a basic example of an intermittent drive circuit of a photoelectric smoke detector of the present invention, FIG. 2 is a block circuit diagram of an embodiment of the present invention, and FIG. 3 is a digital circuit and analog used in the same. Specific circuit diagram of the signal processing circuit, FIG. 4 is a specific circuit diagram of the count circuit used in the same as above, FIG. 5 is a circuit diagram showing another example of the drive circuit used in the same above, FIG. Circuit diagram, FIG. 7 is a concrete circuit diagram of the reference voltage circuit used in the same as above, FIG. 8 is an operation waveform diagram of the sensor circuit in the same as above, FIG. 9 is an operation waveform diagram of the counting circuit used in the same as above, and FIG. FIG. 11 is a cross-sectional view showing a manufacturing process of a dielectric isolation integrated circuit for realizing the above circuit, and FIG. 11 is a block circuit diagram of a conventional example. V _CC is the first power supply line, V _SS1 is the second power supply line,
Tr ₆ , Tr ₇ , Tr ₈ , Tr ₁₁ are transistors, and LEDON is a control signal.

Claims (1)

[Claims] 1. A drive circuit for supplying electric power by a potential difference between a first power supply line and a second power supply line and intermittently driving a light emitting element of a photoelectric smoke detector based on a control signal for intermittent driving. Based on the control signal for intermittent driving, the light-emitting element is controlled to be turned off during a rest period and turned on during a light-emitting element drive period, and a constant voltage is applied between the first and second power supply lines. The first transistor connected in series with the element and the first resistance element and the first transistor connected to the first transistor when the first transistor is turned on are brought into conduction by receiving the analog potential generated in the constant voltage element. A second transistor connected in series with the light emitting element and the second resistance element between the power supply lines, and connected in parallel with the constant voltage element, based on a control signal for intermittent driving. In the drive section of the light emitting element Off and becomes, intermittent driving circuit of the photoelectric smoke sensor, characterized in that it comprises an insulated gate transistor which is controlled to be turned on in the rest period of the light emitting element.