JPH0632473B2 - PLL error calculation circuit - Google Patents

Description

The present invention relates to a PLL error calculation circuit that locks a sampling clock to a burst signal of a television video signal.

[Conventional technology]

FIG. 4 shows a conventional PLL error calculation circuit disclosed in, for example, Japanese Patent Laid-Open No. 59-16491. In FIG. 4, 1 is a delay element, 2 is a sign inverter, 3 and 8 are adders,
Reference numerals 4 and 5 are accumulators, 6 is a multiplier to which a tan θ (θ: current sample phase) signal is input, and 7 is a sign inverter.

Next, the operation will be described. FIG. 5 is a waveform diagram showing a burst signal portion of the input video signal. When the sampling clock is selected to be 4 _sc ( _sc : color subcarrier frequency), there are four sampling points in one cycle of the burst signal. These sampling points are P _4j , P _4j-1 , P _4j-2 ,
P _4j-3, and the amplitudes at these points are (P _4j ), (P
_4j-1 ), (P _4j-2 ), and (P _4j-3 ). Also, half the amplitude of the burst signal is b, and the magnitude of the synchronization signal is a,
Digital conversion is performed based on the sync signal head. Normally, the burst signal includes 8 cycles, but now it is assumed to be k cycles and the PLL
The error signal Er of is obtained by the following equation.

φ is the phase difference between the burst signal and the sampling timing, and (P _4j-3 ) = a + b · sin θ, (P _4j-2 ) = a
+ B · cos θ, (P _4j−1 ) = ab−sin θ, (P
_4j ) = ab−cos θ, the error signal Er is given by the following equation.

Er = 2 kb · sin (θ−φ) / cosφ Therefore, when the sample clock is locked at the phase φ, the error becomes zero. The lock phase is changed by giving tanφ. The circuit that executes these calculations is the PLL error calculation circuit shown in FIG.

[Problems to be solved by the invention]

The burst signal waveform of the broadcast wave actually transmitted has a sinusoidal envelope as shown in FIG. Since the conventional error calculation circuit accumulates error signals during the burst period, it is affected by the burst signal amplitude change due to the envelope,
There is a drawback that the error signal has an error.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a PLL error calculation circuit capable of giving a more accurate error signal.

[Means for solving problems]

In order to achieve such an object, the present invention provides a sample in which a burst signal included in a color signal separated from a television video signal sampled at four times the color subcarrier frequency has a maximum absolute value of amplitude. While finding the point,
A control circuit that outputs a code signal according to the positive or negative sign of the burst signal at this sample point, and a burst signal value at the sample point one before the sample point after the sample point found by this control circuit And a sign inverter that inverts the sign of the output of this subtractor, and a selector that outputs either the output of the subtractor or the output of the sign inverter according to the sign signal output from the control circuit. It was done like this.

[Action]

In the error calculation circuit according to the present invention, points before and after the maximum or minimum point of the burst signal amplitude are the sampling points.

〔Example〕

First, the principle of the error calculation circuit according to the present invention will be described. After being quantized by the A / D converter, the Y / C separated color signal includes a burst signal, the waveform of which is as shown in FIG. When the amplitude of the burst signal b, put the amplitude of the envelope and sin .omega.t, the burst signal waveform is definitive and b · sin2π _sc t · sinωt. The value of the sample point P _m that gives the maximum value of the amplitude of the burst signal shown in FIG. 2 matches the burst signal amplitude b, but if the sample phase is deviated by θ, the amplitude of the sample point P _m (P _m ) Is given by (P _m ) ≈b · cos θ.

Further, before and after the sample points of sample points P _m P _{m + 1} and P _m-1
The amplitudes (P _{m + 1} ) and (P _m-1 ) of (p _{m + 1} ) ≈b ′ · sin θ (P _m-1 ) ≈ -b '· sin θ.

Here, as an error signal (P _m + 1) - if calculating the _{(P m-1), (} P m + 1) - get (P m-1) = 2b '· sinθ.

Depending on the waveform, as shown in FIG. 3, the absolute value of the minimum amplitude may be larger than the absolute value of the maximum amplitude of the burst signal waveform. The third sampling point is the smallest amplitude
This is indicated by _P'm in the figure. In this case, 'before and after the sample points of the _m P' sample point P 'and m + _1, the amplitude of these points _{(P' m-1, P} m-1), (P 'm + 1) Then, (P ′ _{m + 1} ) ≈−b ′ · sin θ (P ′ _m−1 ) ≈b ′ · sin θ, so that [− ((P ′ _{m + 1} ) − (P ′ _m-1 ) ] = 2b '· sin θ and the error signal may be obtained.

In the case of a television broadcast wave, if the burst signal of the nth line is a signal as shown in FIG. 2, (n + 1)
Since the burst of the line is out of phase by π, it becomes a signal as shown in FIG. Therefore, the absolute values of the maximum amplitude (P _m ) in FIG. 2 and the maximum amplitude (P ′ _m ) in FIG. 3 are almost equal when θ is small. Further, this value is the amplitude value of the burst signal that is least affected by the envelope amplitude. Then, by calculating the error signal from the sample points before and after these, the PLL error signal with the least influence of the envelope amplitude can be obtained. The lock phase of the PLL is adjusted so that the phase difference from the phase of the burst signal becomes zero. Therefore, at the sample point, R-
An output that matches the Y and B-Y axes is obtained.

Next, an embodiment of the PLL error calculation circuit according to the present invention is shown in FIG. In FIG. 1, 9 is a control circuit to which the color signal d is input, 10 and 91 are delay circuits that input the color signal d and delay the data of one sample, 11 is a subtractor, 12 is a sign inverter, 13 is a selector, 14 is a data latch circuit, 92 is an absolute value conversion circuit, 93 is a data latch circuit, 94 is a comparison circuit, and T is an input terminal.

Next, the operation will be described. Sampling in which the signals at the sampling points P _j-1 , P _j , P _{j + 1} , P _j-1 signal, P _j signal, and P _{j + 1} signal input to the input terminal T in time series are synchronized with the sampling frequency. By delaying with the delay circuit 10 according to the clock, it is possible to take out at the same time. In this case, if the current signal is the P _{j + 1} signal, the signal at the previous sampling point is the P _j signal, and the signal at the previous sampling point is the P _j-1 signal.

In the control circuit 9, the _Pj signal, which is the signal immediately before the current _{Pj + 1} signal, is _generated by the delay circuit 91, and the absolute value of the value of the _Pj signal is further calculated by the absolute value conversion circuit 92. Create P _j |. Next, the comparison circuit 94 compares the value | P _max | of the signal at a certain sampling point currently held in the data latch circuit 93 with the newly created | P _j |. In the initial state, | P _max | may be set to zero by the reset function of the data latch circuit 93.
The output signal c1 of the comparison circuit 94 causes the data latch circuit 93 to capture new data | P _j | when | P _j | ≧ | P _max |. | P _j | <| P _max | when | P
Hold _max |. Therefore, the data latch circuit 93 holds the largest amplitude value in the time-series signal value sequence that has been entered so far. The amplitude value can be calculated by taking the absolute value. Further, the control circuit 9 is a comparison circuit 94.
And outputs the comparison result signals c1 and the code signal c2 of P _j to the data latch circuit 14 and the selector 13.
The value of the sign signal c2 is "0" if it has a positive value and "1" if it has a negative value, for example, if the value of the signal input to the input terminal T is a two's complement code. .

Next, the calculation of the error output will be described. First, the subtractor 11
And the value of the P _{j + 1} signal (P _{j + 1} ) -the value of the P _j-1 signal (P _j-1 ).
Is calculated and output as a difference signal e. The sign inverter 12 receives the difference signal e and outputs an inverted difference signal f having a value of − [(P _{j + 1} ) − (P _j−1 )]. The selector 13, according to the sign signal c2, P _j is the time of the positive (P j _{+ 1)} - When outputting a difference signal e value _{(P j-1), P} j is negative - [(P _{j + 1} ) −
The inverted difference signal f of the value of (P _j-1 )] is output. The data latch circuit 14 receives | P _j | according to the comparison result signal c1.
When ≧ | P _max |, a new data value (P _{j + 1} ) − (P
_j-1 ) or-[(P _{j + 1} )-(P _j-1 )] is taken in, and when _{│P j} │ <│P _max │, the data value held so far is held.

When the signal of each sample point of the color subcarrier signal having the sine wave envelope is input, the value of the signal held by the data latch circuit 93 of the control circuit 9 until the end (until the end of the burst window signal W) | P _max | is (P _m )
(See FIG. 2). In addition, the data latch circuit 14
The value held up to the end is the error value (P _{m + 1} −P _m−1 ) or − (P ′ _{m + 1} −P ′ _m−1 ) calculated before and after the peak value of the burst. Yes (see FIGS. 2 and 3). In this way, the error signal g (data latch circuit 1
4 output signal).

〔The invention's effect〕

As described above, the present invention can minimize the influence of the amplitude of the burst signal by using the signal values at the sample points before and after the sample point at which the absolute value of the amplitude value of the burst signal becomes maximum. Therefore, there is an effect that an error due to a change in the amplitude of the burst signal can be minimized.

[Brief description of drawings]

FIG. 1 is a system diagram showing an embodiment of a PLL error calculation circuit according to the present invention, FIGS. 2 and 3 are waveform diagrams showing burst signals included in color signals, and FIG. 4 is a conventional PLL.
FIG. 5 is a waveform diagram showing a burst signal included in the video signal, which is a system diagram showing the error calculation circuit. 9 ... Control circuit, 10, 91 ... Delay circuit, 11 ... Subtractor, 12 ... Sign inverter, 13 ... Selector, 14,
93 ... Data latch circuit, 92 ... Absolute value conversion circuit, 9
4 ... Comparison circuit, T ... input terminal.

Claims (1)

[Claims] 1. A sample point at which the absolute value of the absolute value of the amplitude of a burst signal included in a color signal separated from a television video signal sampled at four times the color subcarrier frequency is found, and this sample point is also found. Control circuit that outputs a sign signal according to the positive / negative of the burst signal of, and subtraction that subtracts the burst signal value of the sample point one before from the burst signal value of the sample point one sample point after that found by this control circuit And a sign inverter that inverts the sign of the output of the subtractor, and a selector that outputs either the output of the subtractor or the output of the sign inverter according to the sign signal output from the control circuit. A PLL error calculation circuit characterized by the above.