JPS6352496B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for synchronizing a sampling clock signal to a reference phase signal, which is used when converting an analog input signal including a reference phase signal, such as a color television signal, into a digital signal. Related to phase locked circuits.

A color television signal such as an NTSC signal is converted into a digital signal by an A/D converter, and then digitally separated into a luminance signal (Y signal) and two chromaticity signals (I signal and Q signal). hand,
Methods of digitally processing these signals have become widely used. For example, a digital processor that performs linear transformation such as reduction, enlargement, and rotation of an image is one example.

In such a digital color separation circuit (hereinafter referred to as a digital decoder) that separates an NTSC signal into a Y signal, an I signal, and a Q signal,
The sampling frequency in the A/D converter used to convert the NTSC signal to a digital signal, that is, the sampling clock signal frequency, is selected to be an integral multiple of the color subcarrier frequency, for example, 3 times or 4 times the color subcarrier frequency. Sampling must be performed in phase synchronization with a certain predetermined phase relationship.

As a circuit for obtaining a sampling clock signal whose phase is synchronized to, for example, four times the color subcarrier frequency, there is a digital phase synchronization circuit as shown in FIG.

In FIG. 1, a composite color television signal, for example, an NTSC signal, input to an input terminal 10 is an A/
After being converted into a digital signal by the D converter 11,
It is taken out to the output terminal 12. The output of the A/D converter 11 is also applied to a synchronization separation circuit 13, where the digital signal of the synchronization signal portion is separated. Based on the signal separated by the synchronization separation circuit 13, the burst extraction circuit 14 converts the A/D converter 11 into
This circuit extracts only the part corresponding to the color burst signal, which is the reference phase signal, from the digital signal obtained in the above. That is, in Fig. 2, A/D
This figure shows how _the converter ₁₁ samples _the vicinity of the color burst signal in the NTSC signal _. Only the signal is extracted by the burst extraction circuit 14.

The digital signal corresponding to the color burst signal extracted in this way is sent to the error calculation circuit 15.
guided by. This error calculation circuit 15 has _a reference value of the phase difference between the color burst signal and the sampling clock signal supplied to the A/D converter 11 (this is referred to as a reference phase difference ₎ . This is given as information, and the error of the actual phase difference with respect to this reference phase difference θ ₀ is calculated based on the following equation.

E= _k 〓 ^j=1 (P _4j-3 −P _4j-1 )−{ _k 〓 ^j=1 (P _4j-2 −P _4j )}
tanθ ₀ ...(1) In other words, the sample values of P ₁ to P _4K in Figure 2 are:
If the reference level of the color burst signal is a, the amplitude of the color burst signal is b, and the actual phase difference between the color burst signal and the sampling clock signal is θ, then it is expressed as follows.

P _4j-3 =a+bsinθ...(2) P4j _-2 =a+bsin(θ+π/2)=a+bcosθ...(3) P4j _-1 =a+bsin(θ+π)=a-bsinθ...(4) P _4j = a+bsin(θ+3π/2)=a−bcosθ...(5) In this case, equation (1) is E= _k 〓 ^j=1 2bsinθ−( _k 〓 ^j=1 2bcosθ)tanθ ₀ =2kb/cosθ ₀ (sinθ・cosθ ₀ − cosθ・sinθ ₀ ) = 2 kb/cosθ ₀ sin (θ − θ ₀ ) ...(6) Therefore, the error signal E becomes 0 if θ=θ ₀ , and θ if θ≠θ ₀ The value corresponds to the difference between and θ ₀ .

The error calculation circuit 15 that executes the calculation shown in equation (1) can be realized, for example, by the circuit shown in FIG. In FIG. 3, the digital signal corresponding to the color burst signal inputted to the input terminal 30 by the burst extraction circuit 14 is applied to the shift register 32-1 via the subtraction circuit 31. The output of shift register 32-1 is further sent to shift register 3.
Added to 2-2. The output of the shift register 32-2 is applied to the other input terminal of the subtraction circuit 31. It is assumed that the subtraction circuit 31 is connected to subtract the output of the shift register 32-2 from the digital signal input to the input terminal 30. The shift registers 32-1 and 32-2 are reset by a synchronizing signal, and each time a digital signal corresponding to the color burst signal is input to the input terminal 30, that is, at the period of the sampling clock signal, the shift registers 32-1 and 32-2 are reset to the color burst signal. Assume that a clock signal is provided at the corresponding sampling instant. When a digital signal of sample values P ₁ to P _K is input from the input terminal 30 in this state, at the end of the color burst signal, the outputs S ₁ and S ₂ of the shift registers 32-1 and 32-2 are respectively The value will be as follows.

S ₁ = _k 〓 ^j=1 (P _4j −P _4j-2 ) ……(7) S ₂ = _k 〓 ^j=1 (P _4j-1 −P _4j-3 ) ……(8) Shift register 32− 1 output S ₁ is multiplier circuit 3
3 and is the output of the reference signal generator 34.
Multiplied by the digital value of tanθ ₀ , subtraction circuit 35
is input to one input terminal of On the other hand, the output of the shift register 32-2 is input to the other input terminal of the subtraction circuit 35. The subtraction circuit 35 is the multiplication circuit 3
The output of shift register 32-2 is subtracted from the output of shift register 32-2. At this time, subtraction circuit 3
The output S of 5 is expressed as follows.

S=S ₁ ×tanθ ₀ −S ₂ = _k 〓 ^j=1 (P _4j-3 −P _4j-1 )−{ _k 〓 ^j=1 (P _4j-2 −P _4j )}tanθ ₀ …(9 ) S in equation (9) is equal to the error signal E shown in equation (1).

The error signal E of θ with respect to θ ₀ calculated in this way by the error calculation circuit 15 is sent to the D/A converter 16.
is held for a sufficient time to perform the conversion operation, for example, until the arrival of the next color burst signal, and a digital signal corresponding to this error signal E is output from the error calculation circuit 15. This error calculation circuit 1
The output of 5 is converted into an analog signal by a D/A converter 16, and then provided to a voltage controlled oscillator 18 as an oscillation frequency control voltage via a loop filter 17. The output of this voltage controlled oscillator 18 is then supplied to the A/D converter 11 as a sampling clock signal.

The phase synchronized circuit configured in this way is an A/D
The converter 11, the burst extraction circuit 14, the error calculation circuit 15, and the D/A converter 16 function as a phase comparator, and the error signal E is calculated from the digital signal after A/D conversion. A/
This has the advantage that all unstable factors including the aperture delay of the D converter 11 can be absorbed.

However, in this case, since the phase comparison between the output of the voltage controlled oscillator 18, which is the sampling clock signal, and the color burst signal is performed digitally via the A/D converter 11, the A/D converter There is a dead zone in the phase comparison characteristic due to the quantization accuracy of 11, and it is impossible in principle to reduce the phase fluctuation of the sampling clock signal to zero.
That is, even if the sampling point of the color burst signal by the sampling clock signal fluctuates between two adjacent threshold values determined by the quantization precision of the A/D converter 11, the The digital signal that is the output does not change. Therefore, when the error signal E has converged to zero, even if the phase of the sampling clock signal fluctuates within the angle Δθ ₀ proportional to the minimum quantization step of the A/D converter 11, the error signal E remains zero. Since it does not change as it is,
The loop gain of the phase locked loop becomes zero. In other words, the phase comparison characteristics of the phase locked circuit shown in Fig. 1 are as follows:
As shown in FIG. 4, the error signal E changes stepwise for each angle Δθ ₀ that depends on the minimum quantization step ΔS of the A/D converter 11, and when the error signal E becomes zero, the loop gain becomes zero. This causes a steady phase error and phase jitter in the phase locked circuit. Of these, the steady phase error is digitized.
Although it has relatively little negative effect on NTSC signals, phase jitter has a negative effect on NTSC signals.
This results in very large deterioration such as a decrease in N.

The present invention has been made in view of the above points, and provides a sampling clock synchronized with a reference phase signal, which is necessary when converting an analog input signal including a reference phase signal such as a color television signal into a digital signal. The object of the present invention is to significantly reduce the phase jitter of a sampling clock signal caused by the quantization accuracy of an A/D converter in a phase locked circuit that obtains a signal.

The present invention converts the output of the error calculation circuit, that is, the phase difference between the reference phase signal and the sampling clock signal of the A/D converter into a digital value that changes in a stepwise manner, which is an error signal with respect to a predetermined reference phase difference. , a certain minute digital value smaller than one step of the digital value of this error signal is added. As a result, the phase control of the sampling clock signal becomes bang-bang control, so that the phase jitter of the sampling clock signal can be kept very small.

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 5 is a block diagram showing the configuration of a phase locked circuit according to an embodiment of the present invention, in which a digital level generation circuit 50 and an adder circuit 5 are added to the circuit of FIG.
1 has been added. That is, the digital level generation circuit 50 is a circuit that generates a digital signal of a constant minute value, and the addition circuit 51 adds this digital signal to the digital signal output from the error calculation circuit 15. The output of the adder circuit 51 is then supplied to the D/A converter 16.

The phase comparison characteristic of the phase synchronized circuit configured as shown in FIG. 5 is as shown in FIG. It is shifted by the corresponding amount Δe. Therefore, when the digital value of the output of the digital level generation circuit 50 is expressed as the error signal E in the phase comparison characteristic, Δe
If selected so that it is within one step ΔE of
The operation of this phase synchronized circuit is bang-bang control that works so that θ-θ ₀ converges to −Δθ ₀ /2. In other words, at the convergence point of θ-θ ₀ -Δθ ₀ /2, the error signal E does not become zero but has two values, +Δe and (-ΔE+Δe), and the loop gain of the phase-locked loop becomes infinite. It becomes large and has bang-bang control characteristics. As a result, the sampling clock signal has a steady phase error of -
Although Δθ ₀ /2 occurs, if the loop filter 17 is designed optimally, the phase jitter becomes very small.

That is, in the phase locked circuit shown in Fig. 1,
Although the sampling clock signal at most produces a phase jitter corresponding to an angle Δθ ₀ proportional to the minimum quantization step of the A/D converter 11, according to the present invention, this phase jitter is made sufficiently smaller than Δθ ₀ . Is possible.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, a case was explained in which a positive level digital signal was generated by the digital level generation circuit 50, but even when a negative level digital signal is generated, the steady phase error of the sampling clock signal is +Δθ ₀ /2. Similarly, the phase jitter of the sampling clock signal is reduced by bang-bang control.

Further, in the above embodiment, the sampling clock signal is phase synchronized with a frequency four times the color subcarrier frequency, but by changing the calculation formula in the error calculation circuit 15, it is possible to synchronize the sampling clock signal with a frequency that is four times the color subcarrier frequency. Alternatively, it is possible to configure the phase synchronization to be a rational number multiple.

In addition, in order to make the phase locked circuit non-localized,
It is also possible to insert a digital integration circuit or a digital loop filter between the adder circuit 51 and the D/A converter 16, and to remove the loop filter 17 made of an analog circuit.

Furthermore, instead of calculating the error signal E itself as shown in equation (1), the error calculation circuit 15 may calculate an amount proportional to this E and generate a digital signal corresponding to the calculation. Of course.

Further, although all the sampling values of the color burst signal are used in equation (1), it is clear that K in equation (1) may be any number as long as it is equal to or less than the number of cycles of the color burst signal.

Further, in the above embodiment, an example was explained in which a sampling clock signal synchronized with a color burst signal is obtained when an NTSC signal, which is a composite color television signal, is A/D converted. The present invention is applicable to a circuit that obtains a sampling clock signal synchronized with a reference phase signal when A/D converting not only a color television signal but also an analog signal containing a reference phase signal in general. For example, in certain signal transmission systems and communication systems, a pilot signal that provides a reference phase is intermittently inserted into a signal wave and transmitted from the transmitting side, and a sampling clock signal synchronized with this pilot signal is created on the receiving side. It is conceivable that the signal wave may be A/D converted and digitally processed; however, in such a case, the pilot signal may also be
By handling the color burst signal in the same way as the color burst signal in the NTSC signal, the same effect as in the embodiment described above can be obtained.

As explained above, according to the present invention, it is possible to achieve phase synchronization with the reference phase signal and to avoid quantization errors of the A/D converter, which is necessary when A/D converting an analog signal into which a reference phase signal has been inserted. It is possible to obtain a sampling clock signal in which the phase jitter caused by the sampling clock signal is significantly reduced, which is extremely effective when applied to the digital decoder mentioned above.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional digital phase synchronization circuit, FIG. 2 is a waveform diagram of a color burst signal section to explain its operation, and FIG. 3 is a specific example of the error calculation circuit 15 in FIG. FIG. 4 is a diagram showing the phase comparison characteristics of the phase-locked circuit shown in FIG. 1, FIG. 5 is a block diagram of a phase-locked circuit according to an embodiment of the present invention, and FIG. FIG. 3 is a diagram showing phase comparison characteristics of a phase locked circuit. 11...A/D converter, 13...Synchronization separation circuit, 14...Burst extraction circuit, 15...Error calculation circuit, 16...D/A converter, 17...Loop filter, 18...Voltage control Oscillator, 50...digital level generation circuit, 51...addition circuit.

Claims (1)

[Claims] 1. A clock signal source, and an A/D converter that receives the clock signal from the clock signal source as a sampling clock signal and converts an analog input signal into which a reference phase signal is inserted into a digital signal. , means for extracting a digital signal corresponding to the reference phase signal from the output of the A/D converter;
means for obtaining an error signal of the phase difference between the reference phase signal and the sampling clock signal with respect to a predetermined reference phase difference as a digital value that changes in a stepwise manner using the digital signal obtained by this means; means for adding a certain minute digital value to the digital value of the error signal obtained by this means; a D/A converter for converting the digital value to which the minute digital value has been added by this means into an analog signal; A phase synchronization circuit comprising: means for controlling the phase of the sampling clock signal to be synchronized with the reference phase signal based on the output of the /A converter. 2. Claim 1, wherein the analog input signal is a color television signal, and the reference phase signal is a color burst signal.
Phase-locked circuit described in section.