JPH0633235B2 - Silicon single crystal excellent in oxide film withstand voltage characteristic and method for manufacturing the same - Google Patents
Silicon single crystal excellent in oxide film withstand voltage characteristic and method for manufacturing the sameInfo
- Publication number
- JPH0633235B2 JPH0633235B2 JP1086505A JP8650589A JPH0633235B2 JP H0633235 B2 JPH0633235 B2 JP H0633235B2 JP 1086505 A JP1086505 A JP 1086505A JP 8650589 A JP8650589 A JP 8650589A JP H0633235 B2 JPH0633235 B2 JP H0633235B2
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- Prior art keywords
- single crystal
- oxide film
- silicon single
- wafer
- silicon
- Prior art date
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Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、チョクラルスキー法により製造された酸化膜
耐圧特性の優れたシリコン単結晶およびその製造方法に
関する。TECHNICAL FIELD The present invention relates to a silicon single crystal which is manufactured by the Czochralski method and has excellent oxide film withstand voltage characteristics, and a manufacturing method thereof.
（従来の技術） 従来、シリコン単結晶の育成に関して種々の方法が知ら
れている。なかでも、石英坩堝内のシリコン融液に付け
た種結晶を引き上げる事により単結晶棒を成長させるチ
ョクラルスキー法は工業的に広く用いられている。この
方法で製造された単結晶ウェハ（以下、ＣＺウェハと称
する。）の酸化膜耐圧は、フローティング・ゾーン法に
より製造された単結晶ウェハ（以下、ＦＺウェハと称す
る。）、およびチョクラルスキー法により製造された単
結晶基板にシリコン薄膜をエピタキシャル成長させたウ
ェハ（以下、ｅｐｉウェハと称する）の酸化膜耐圧に比
べて著しく低い事が知られている（例えば、小柳光正
「サブミクロンデバイスII、３ゲート酸化膜の信頼性」
（昭和６３年１月３０日発行）、丸善（株）、ｐ７
０）。にもかかわらず、ＣＺウェハには種々の特徴があ
るため現在でもデバイス用材料として広く利用されてい
る。しかし、近年、ＭＯＳデバイス集積度の増大にとも
ないゲート酸化膜の信頼性向上が強く望まれるところと
なり、酸化膜耐圧はその信頼性を決定する重要な材料特
性の１つであるため、酸化膜耐圧特性の優れたＣＺウェ
ハ及びその製造技術の開発が急務となっていた。ところ
が、従来の技術では、本発明者らが行なった第２表に示
す実験結果に見られるように、酸化膜耐圧特性の優れた
ＣＺウェハを製造することはできなかった。(Prior Art) Various methods are conventionally known for growing a silicon single crystal. Among them, the Czochralski method of growing a single crystal rod by pulling a seed crystal attached to a silicon melt in a quartz crucible is widely used industrially. The oxide film breakdown voltage of the single crystal wafer (hereinafter, referred to as CZ wafer) manufactured by this method is the same as that of the single crystal wafer (hereinafter, referred to as FZ wafer) manufactured by the floating zone method and the Czochralski method. It is known that the oxide film breakdown voltage of a wafer (hereinafter, referred to as an epi wafer) in which a silicon thin film is epitaxially grown on a single crystal substrate manufactured by M. Gate oxide film reliability "
(Published January 30, 1988), Maruzen Co., Ltd., p7
0). Nevertheless, since CZ wafers have various characteristics, they are still widely used as device materials. However, in recent years, it has been strongly desired to improve the reliability of the gate oxide film with the increase in the integration density of MOS devices, and the oxide film breakdown voltage is one of the important material characteristics that determine the reliability. There has been an urgent need to develop a CZ wafer having excellent characteristics and its manufacturing technology. However, with the conventional technique, it was not possible to manufacture a CZ wafer having excellent oxide film breakdown voltage characteristics, as shown in the experimental results shown in Table 2 conducted by the present inventors.
（発明が解決しようとする課題） 第３図に示すように、チョクラルスキー法では石英ガラ
ス製坩堝１に原料である多結晶シリコンを入れ、これを
ヒーターにより加熱して原料融液２とする。この後、種
結晶３を原料融液２に浸漬し、種結晶３や坩堝１を回転
させながら単結晶棒４を引き上げる。これらの操作は、
通常、ガス導入口６から導入されたチャンバー５内を矢
印で示したように流れる不活性ガスの雰囲気下で行なわ
れる。こういった方法でシリコン単結晶を成長させる場
合のプロセス制御因子には、坩堝回転速度、種結晶回転
速度、結晶成長雰囲気、融液温度、結晶引き上げ速度、
その他多数のものがあり、これらの因子の内のどれがＣ
Ｚウェハの酸化膜耐圧特性を支配するかについては従来
全く知られていなかった。また、ｅｐｉウェハと同等の
酸化膜耐圧を示すＣＺウェハが製造できたと言う報告も
皆無であり、実際そのようなウェハは存在しなかった。
例えば、従来のチョクラルスキー法による大直径（直径
５０mm以上）無転位シリコン単結晶の引き上げ速度は
１．２mm/min以上（例えば、阿部孝夫「超ＬＳＩプロセ
スデータハンドブック、第１章単結晶引き上げ技術」
（昭和５７年４月１５日発行）、（株）サイエンスフォ
ーラム、ｐ６４）であり、このような条件において作製
されたシリコン単結晶から製造されたＣＺウェハは、第
２表に示す実験結果に見られるように酸化膜耐圧特性
（後述するＣモード合格率）がｅｐｉウェハに比較して
明らかに悪いものであった。(Problems to be Solved by the Invention) As shown in FIG. 3, in the Czochralski method, polycrystalline silicon as a raw material is put in a quartz glass crucible 1 and heated by a heater to obtain a raw material melt 2. . After that, the seed crystal 3 is immersed in the raw material melt 2, and the single crystal rod 4 is pulled up while rotating the seed crystal 3 and the crucible 1. These operations are
Usually, it is carried out in an atmosphere of an inert gas flowing in the chamber 5 introduced from the gas introduction port 6 as indicated by an arrow. Process control factors for growing a silicon single crystal by such a method include crucible rotation speed, seed crystal rotation speed, crystal growth atmosphere, melt temperature, crystal pulling speed,
There are many others and which of these factors is C
It has not been known at all whether or not it governs the oxide film breakdown voltage characteristics of the Z wafer. Further, there is no report that a CZ wafer showing an oxide film breakdown voltage equivalent to that of an epi wafer could be manufactured, and such a wafer did not actually exist.
For example, the pulling speed of a large diameter (diameter 50 mm or more) dislocation-free silicon single crystal by the conventional Czochralski method is 1.2 mm / min or more (for example, Takao Abe “VLSI Process Data Handbook, Chapter 1 Single Crystal Pulling Technology”). "
(Published April 15, 1982), Science Forum Co., Ltd., p64), and the CZ wafer manufactured from the silicon single crystal manufactured under such conditions can be seen in the experimental results shown in Table 2. As can be seen, the breakdown voltage characteristic of the oxide film (C-mode pass rate described later) was obviously worse than that of the epi wafer.
本発明は、デバイス製造用の酸化膜耐圧特性に優れたＣ
Ｚウェハが得られる従来に無いシリコン単結晶を提供す
る事、およびそのようなシリコン単結晶をチョクラルス
キー法により工業的に製造するためのプロセス制御条件
を定める事を目的とする。INDUSTRIAL APPLICABILITY The present invention is a C excellent in oxide film breakdown voltage characteristics for device manufacturing
It is an object to provide an unprecedented silicon single crystal from which a Z wafer can be obtained, and to define process control conditions for industrially manufacturing such a silicon single crystal by the Czochralski method.
（課題を解決するための手段） 本発明のシリコン単結晶は、チョクラルスキー法により
製造された直径１００mm以上のシリコン単結晶ウェハで
あって、上層がアルミニウム、下層がドープされた多結
晶シリコンからなる直径５mmの２層ゲート電極を有する
多数個のＭＯＳダイオードを該シリコン単結晶ウェハ上
に実装し、基板シリコンから多数キャリアが注入される
極性の直流電圧を各ＭＯＳダイオードに印加して電圧ラ
ンピング法により前記ウェハの酸化膜耐圧を評価した場
合において、酸化膜を通して流れる電流密度が１μＡ／
cm2の時の該酸化膜にかかる平均電界が８．０ＭＶ／cm
以上を示すＭＯＳダイオードの個数の割合が１ウェハに
付き６０％以上であることを特徴とする。(Means for Solving the Problem) A silicon single crystal of the present invention is a silicon single crystal wafer having a diameter of 100 mm or more, which is manufactured by the Czochralski method. The upper layer is aluminum and the lower layer is polycrystalline silicon. A large number of MOS diodes having a double-layered gate electrode having a diameter of 5 mm are mounted on the silicon single crystal wafer, and a DC voltage of a polarity in which majority carriers are injected from the substrate silicon is applied to each MOS diode to perform a voltage ramping method. When the breakdown voltage of the oxide film of the wafer is evaluated by, the current density flowing through the oxide film is 1 μA /
The average electric field applied to the oxide film at cm 2 is 8.0 MV / cm
The ratio of the number of MOS diodes described above is 60% or more per wafer.
また、本発明のシリコン単結晶の製造方法は、チョクラ
ルスキー法により直径１００mm以上でかつ前記の優れた
酸化膜耐圧特性を有するシリコン単結晶を製造する方法
において、結晶成長速度を０．８mm/min以下とすること
を特徴とする。The method for producing a silicon single crystal according to the present invention is a method for producing a silicon single crystal having a diameter of 100 mm or more and excellent oxide film withstand voltage characteristics according to the Czochralski method, with a crystal growth rate of 0.8 mm / It is characterized in that it is not more than min.
（作用） 以下、図表を参照しながら、本発明の具体的構成と作用
を説明する。(Operation) The specific configuration and operation of the present invention will be described below with reference to the drawings.
第１図は、本発明のシリコン単結晶の酸化膜耐圧を評価
する際、シリコンウェハ上に実装したＭＯＳダイオード
の断面であり、シリコンウェハ１１の上にＳｉＯ２層１
２が形成され、その上に上層がアルミニウム１４、下層
がドープさた多結晶シリコン１３からなる直径５mmの２
層ゲート電極１５が形成されている。そしてこのような
直径５mmの２層ゲート電極１５を有するＭＯＳダイオー
ド９が、第２図に示すようにシリコンウェハ８（ゲート
酸化により形成されたＳｉＯ２膜を有するシリコンウェ
ハ）上に多数個形成されている。The first figure in evaluating the oxide dielectric breakdown voltage of the silicon single crystal of the present invention, a cross section of MOS diodes mounted on a silicon wafer, SiO 2 layer on a silicon wafer 11 1
2 with a diameter of 5 mm consisting of aluminum 14 as the upper layer and polycrystalline silicon 13 as the lower layer.
The layer gate electrode 15 is formed. Then, as shown in FIG. 2 , a large number of MOS diodes 9 having such a two-layer gate electrode 15 having a diameter of 5 mm are formed on a silicon wafer 8 (a silicon wafer having a SiO 2 film formed by gate oxidation). ing.
次に、本発明のシリコン単結晶における酸化膜耐圧特性
に関する評価手段を第１表により説明する。チョクラル
スキー法により製造された直径１００mm以上のシリコン
単結晶棒をスライスし、ラッピング、ポリッシングな
ど、通常、シリコンウェハを工業的に製造するために必
要な諸工程を経て得られたウェハを洗浄し（１）、ゲー
ト酸化を行ってＳｉＯ２層を形成し（２）、多結晶シリ
コン膜を堆積させ（３）、この多結晶シリコンにイオン
注入してドープする（６）。酸化前洗浄（４）及び多結
晶シリコンの酸化（５）はイオン注入（６）の前処理で
ある。ついで、アニール前洗浄（７）を行ない、ドライ
ブアニールして多結晶シリコン中のドーパントを固溶化
し（８）、多結晶シリコン酸化膜をエッチング除去し
（９）、アルミニウムを蒸着してアルミニウム層を形成
する（１０）。つぎに、直径５mmの２層ゲート電極を実
装するためにリソグラフィー（１１）によりポジレジス
ト膜をコートして、パターニングした後、アルミニウム
層をエッチングし（１２）、多結晶シリコン膜をエッチ
ングして（１３）、レジスト膜を除去する（１４）。そ
して、水素アニールによりＳｉ／ＳｉＯ２界面を安定化
した後（１５）、表面にレジスト膜を塗布してＭＯＳダ
イオードを保護し（１６）、プラズマエッチングにより
裏面多結晶シリコン膜を除去する（１７）。表面に保護
用のレジスト膜を再度塗布して（１８）、裏面酸化膜を
エッチングにより除去し（１９）、ｐ型の場合には金、
ｎ型の場合には金・アンチモン合金を蒸着して裏面電極
を形成する（２０）。最後に、保護用レジスト膜を除去
した後（２１）、電圧ランピング法により酸化膜耐圧特
性を評価する（２２）。電圧ランピング法とは、第１図
において、基板シリコンから多数キャリアが注入される
極性の直流電圧をアルミニウム層１４と裏面電極との間
に印加し、その電圧を時間に対してステップ状に増加さ
せる方法である。本発明では、該電圧ランピング法の１
ステップあたりの電圧増加を電界換算で０．２５ＭＶ／
cm、保持時間を２００ms／ステップとし、第１図におけ
るＳｉＯ２層１２を通して流れる電流密度が１．０μＡ
／cm2となるときにＳｉＯ２層１２にかかる平均電界が
８．０ＭＶ／cm以上を示すＭＯＳダイオードの個数の割
合（これをＣモード合格率という）でシリコン単結晶の
酸化膜耐圧特性を評価した。本発明のシリコン単結晶は
Ｃモード合格率が６０％以上である。Next, the means for evaluating the oxide film breakdown voltage characteristics of the silicon single crystal of the present invention will be described with reference to Table 1. Slicing a silicon single crystal rod with a diameter of 100 mm or more manufactured by the Czochralski method, lapping, polishing, etc., and cleaning the wafer obtained through the various steps normally required for industrially manufacturing a silicon wafer. (1) Gate oxidation is performed to form a SiO 2 layer (2), a polycrystalline silicon film is deposited (3), and this polycrystalline silicon is ion-implanted and doped (6). Pre-oxidation cleaning (4) and polycrystalline silicon oxidation (5) are pre-treatments for ion implantation (6). Then, pre-anneal cleaning (7) is performed, drive annealing is performed to solidify the dopant in the polycrystalline silicon (8), the polycrystalline silicon oxide film is removed by etching (9), and aluminum is evaporated to form an aluminum layer. Form (10). Next, a positive resist film is coated by lithography (11) to mount a two-layer gate electrode with a diameter of 5 mm, and after patterning, the aluminum layer is etched (12) and the polycrystalline silicon film is etched ( 13), the resist film is removed (14). After the Si / SiO 2 interface is stabilized by hydrogen annealing (15), a resist film is applied on the surface to protect the MOS diode (16), and the back surface polycrystalline silicon film is removed by plasma etching (17). . A protective resist film is applied again on the surface (18), and the backside oxide film is removed by etching (19). In the case of p-type, gold,
In the case of n-type, a gold / antimony alloy is vapor-deposited to form a back electrode (20). Finally, after removing the protective resist film (21), the oxide film breakdown voltage characteristic is evaluated by the voltage ramping method (22). In the voltage ramping method, in FIG. 1, a DC voltage having a polarity in which majority carriers are injected from the substrate silicon is applied between the aluminum layer 14 and the back electrode, and the voltage is increased stepwise with respect to time. Is the way. In the present invention, one of the voltage ramping methods is used.
The voltage increase per step is 0.25 MV /
cm, the holding time is 200 ms / step, and the current density flowing through the SiO 2 layer 12 in FIG. 1 is 1.0 μA.
When the average electric field applied to the SiO 2 layer 12 is 8.0 MV / cm or more when it becomes / cm 2 , the oxide film withstand voltage characteristic of the silicon single crystal is evaluated by the ratio of the number of MOS diodes (this is called the C mode pass rate). did. The silicon single crystal of the present invention has a C mode acceptance rate of 60% or more.
第３図は、本発明が対象とするチョクラルスキー法によ
りシリコン単結晶棒を製造する装置の１例である。この
装置の構成を簡単に述べると、ガス導入口６および排気
口７を備えたチャンバー５内に、石英ガラス製坩堝１を
回転に配置し、一方、この坩堝１上方に、先端部に種結
晶３をチャック（図示せず）によって保持する引上げワ
イヤを配置したものである。本発明は、第３図に示すよ
うな装置により、坩堝１に収容した原料融液から単結晶
棒４を引き上げ、固液界面でシリコン単結晶を成長させ
る際、その結晶引き上げ速度を０．８mm/min以下とす
る。引き上げ速度がこの値より大きいと、Ｃモード合格
率が６０％未満となって、従来のシリコン単結晶と同程
度となる。しかしながら、引き上げ速度が０．８mm/min
以下であると、Ｃモード合格率が上昇して６０％以上、
さらに、０．５mm/min以下でｅｐｉウェハとほぼ同等の
９０％以上となり、ゲート酸化膜の信頼性が著しく向上
する。FIG. 3 shows an example of an apparatus for producing a silicon single crystal ingot by the Czochralski method, which is the object of the present invention. Briefly describing the configuration of this device, a quartz glass crucible 1 is rotatably arranged in a chamber 5 provided with a gas inlet 6 and an exhaust port 7, while a seed crystal is provided above the crucible 1 at the tip. A pulling wire for holding 3 by a chuck (not shown) is arranged. According to the present invention, the single crystal ingot 4 is pulled out from the raw material melt housed in the crucible 1 and the silicon single crystal is grown at the solid-liquid interface by the apparatus as shown in FIG. / min or less. When the pulling rate is higher than this value, the C-mode pass rate is less than 60%, which is about the same as that of the conventional silicon single crystal. However, the pulling speed is 0.8 mm / min
If it is less than 60%, the C-mode pass rate increases,
Further, at 0.5 mm / min or less, it becomes 90% or more, which is almost equal to that of the epi wafer, and the reliability of the gate oxide film is significantly improved.
［実施例］ 次に本発明の実施例を説明する。[Examples] Next, examples of the present invention will be described.
第３図に示した装置を使用して、結晶引き上げ前の原料
融液２の量を３５〜６５kg、不活性ガスとしてのアルゴ
ン吹き込み流量を５０〜１００Ｎ／minとして、単結
晶棒４を０．８mm/min以下の速度で引き上げ単結晶を成
長させた。一方、本発明のシリコン単結晶との比較のた
めに０．８mm/minを越える速度で引き上げた単結晶棒も
製造した。得られたシリコン単結晶ウェハの製造条件お
よび特性を第２表に示す。なお、試料No.５は、原料多
結晶シリコンを融液２に連続的に供給しつつ、０．４mm
/minの速度で単結晶棒を引き上げた。また、、試料No.
９および１０は、磁場を加えながら単結晶棒を引き上げ
た。これらの単結晶棒からウェハを切り出し、ラッピン
グ、ポリッシングなど、通常、シリコンウェハを工業的
に製造するために必要な工程を経て、片面が鏡面のＣＺ
ウェハを作製した。Using the apparatus shown in FIG. 3, the amount of the raw material melt 2 before crystal pulling is set to 35 to 65 kg, the flow rate of argon as an inert gas is set to 50 to 100 N / min, and the single crystal rod 4 is adjusted to 0. A single crystal was grown at a rate of 8 mm / min or less. On the other hand, for comparison with the silicon single crystal of the present invention, a single crystal ingot pulled at a rate exceeding 0.8 mm / min was also manufactured. Table 2 shows the manufacturing conditions and characteristics of the obtained silicon single crystal wafer. Sample No. 5 was 0.4 mm while continuously supplying the raw material polycrystalline silicon to the melt 2.
The single crystal rod was pulled up at a speed of / min. Also, sample No.
In Nos. 9 and 10, the single crystal rod was pulled up while applying a magnetic field. Wafers are cut out from these single crystal rods, and lapping, polishing, and the like, which are usually necessary for industrially producing silicon wafers, and one side of which is CZ with a mirror surface.
A wafer was prepared.
これらＣＺウェハの酸化膜耐圧特性は、前述のように、
第１表の工程によりＣモード合格率を求め、評価した。
第２表に示す結果から明らかなように、結晶引き上げ速
度を０．８mm/min以下とすることにより、従来予想もで
きなかった高レベルでＣＺウェハの酸化膜耐圧特性が著
しく向上するものであった。The oxide film breakdown voltage characteristics of these CZ wafers are as described above.
The C-mode pass rate was obtained and evaluated by the steps shown in Table 1.
As is clear from the results shown in Table 2, by setting the crystal pulling rate to 0.8 mm / min or less, the oxide film withstand voltage characteristic of the CZ wafer is remarkably improved at a high level that could not be predicted conventionally. It was
［発明の効果］ 以上詳述したように、本発明のＣＺウェハは従来にない
優れた酸化膜耐圧特性を有するため、ゲート酸化膜の信
頼性が高く、ＭＯＳデバイス用のウェハに適する。 [Effects of the Invention] As described in detail above, the CZ wafer of the present invention has excellent oxide film breakdown voltage characteristics that have not been obtained in the past, and therefore has a high reliability of the gate oxide film and is suitable for a wafer for a MOS device.
第１図は本発明シリコン単結晶の酸化膜耐圧特性を評価
するためにシリコンウェハ上に実装したＭＯＳダイオー
ドの一部断面図、第２図はＭＯＳダイオードを実装した
該ウェハの平面図、第３図はチョクラルスキー法におい
て用いられる製造装置の一例の構成を示す図である。 １……石英ガラス製坩堝、２……原料融液、３……種結
晶、４……シリコン単結晶棒、５……チャンバー、６…
…ガス導入口、７……排気口、８……ゲート酸化により
形成されたＳｉＯ２膜を有するシリコンウェハ、９……
ＭＯＳダイオード（電極直径５mm）、１０……ＭＯＳダ
イオード（電極直径１，２，３，４，６mm）、１１……
基板シリコン、１２……ＳｉＯ２膜（厚さ約２５０
Å）、１３……多結晶シリコン層（厚さ約５０００
Å）、１４……アルミニウム層（厚さ２０００〜５００
０Å）、１５……２層ゲート電極。FIG. 1 is a partial cross-sectional view of a MOS diode mounted on a silicon wafer for evaluating the oxide film breakdown voltage characteristics of the silicon single crystal of the present invention, and FIG. 2 is a plan view of the wafer on which the MOS diode is mounted. The figure is a diagram showing a configuration of an example of a manufacturing apparatus used in the Czochralski method. 1 ... Quartz glass crucible, 2 ... Raw material melt, 3 ... Seed crystal, 4 ... Silicon single crystal rod, 5 ... Chamber, 6 ...
... gas inlet, 7 ... exhaust, 8 ... silicon wafer having SiO 2 film formed by gate oxidation, 9 ...
MOS diode (electrode diameter 5 mm), 10 ... MOS diode (electrode diameter 1, 2, 3, 4, 6 mm), 11 ...
Substrate silicon, 12 ... SiO 2 film (thickness about 250
Å), 13 ... Polycrystalline silicon layer (thickness about 5000
Å), 14 ... Aluminum layer (thickness 2000-500
0Å), 15 ... Two-layer gate electrode.
フロントページの続き (72)発明者 金子 高之 山口県光市大字島田3434番地 ニッテツ電 子株式会社光工場内 (56)参考文献 特開 昭62−138384（ＪＰ，Ａ)Front page continuation (72) Inventor Takayuki Kaneko 3434 Shimada, Hikari-shi, Yamaguchi Prefecture, Hikari Plant, Nittetsu Electronic Co., Ltd. (56) References JP 62-138384 (JP, A)
Claims (2)
１００mm以上のシリコン単結晶ウェハであって、上層が
アルミニウム、下層がドープされた多結晶シリコンから
なる直径５mmの２層ゲート電極を有する多数個のＭＯＳ
ダイオードを該シリコン単結晶ウェハ上に実装し、基板
シリコンから多数キャリアが注入される極性の直流電圧
を各ＭＯＳダイオードに印加して電圧ランピング法によ
り前記ウェハの酸化膜耐圧を評価した場合において、酸
化膜を通して流れる電流密度が１μＡ／cm2の時の該酸
化膜にかかる平均電界が８．０ＭＶ／cm以上を示すＭＯ
Ｓダイオードの個数の割合が１ウェハに付き６０％以上
であることを特徴とする酸化膜耐圧特性に優れたシリコ
ン単結晶。1. A silicon single crystal wafer having a diameter of 100 mm or more manufactured by the Czochralski method, which has a large number of two-layer gate electrodes having an upper layer of aluminum and a lower layer of polycrystalline silicon having a diameter of 5 mm. MOS
In the case where a diode is mounted on the silicon single crystal wafer, a DC voltage of a polarity in which majority carriers are injected from the substrate silicon is applied to each MOS diode and the oxide film breakdown voltage of the wafer is evaluated by the voltage ramping method, oxidation is performed. MO showing an average electric field of 8.0 MV / cm or more applied to the oxide film when the current density flowing through the film is 1 μA / cm 2.
A silicon single crystal excellent in oxide film withstand voltage characteristics, characterized in that the number of S diodes is 60% or more per wafer.
の直径１００mm以上でかつ酸化膜耐圧特性に優れたシリ
コン単結晶を製造する方法であって、結晶成長速度を
０．８mm/min以下とすることを特徴とするシリコン単結
晶の製造方法。2. A method for producing a silicon single crystal having a diameter of 100 mm or more and excellent oxide film withstand voltage characteristics according to the Czochralski method, wherein the crystal growth rate is 0.8 mm / min or less. A method for producing a silicon single crystal, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1086505A JPH0633235B2 (en) | 1989-04-05 | 1989-04-05 | Silicon single crystal excellent in oxide film withstand voltage characteristic and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1086505A JPH0633235B2 (en) | 1989-04-05 | 1989-04-05 | Silicon single crystal excellent in oxide film withstand voltage characteristic and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02267195A JPH02267195A (en) | 1990-10-31 |
| JPH0633235B2 true JPH0633235B2 (en) | 1994-05-02 |
Family
ID=13888840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1086505A Expired - Lifetime JPH0633235B2 (en) | 1989-04-05 | 1989-04-05 | Silicon single crystal excellent in oxide film withstand voltage characteristic and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0633235B2 (en) |
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| JP2546745B2 (en) * | 1991-03-15 | 1996-10-23 | 信越半導体株式会社 | Method for manufacturing semiconductor device |
| JP2521007B2 (en) * | 1992-06-30 | 1996-07-31 | 九州電子金属株式会社 | Method for producing silicon single crystal |
| JP2862158B2 (en) * | 1993-08-27 | 1999-02-24 | 信越半導体株式会社 | Silicon single crystal manufacturing equipment |
| JP3006368B2 (en) * | 1993-10-18 | 2000-02-07 | 住友金属工業株式会社 | Method and apparatus for producing silicon single crystal having excellent oxide film breakdown voltage characteristics |
| JP2006066928A (en) * | 1994-09-09 | 2006-03-09 | Renesas Technology Corp | Method of manufacturing semiconductor device |
| JPH08337490A (en) * | 1995-06-09 | 1996-12-24 | Shin Etsu Handotai Co Ltd | Silicon single crystal almost free from crystal defect and its production |
| JP3844536B2 (en) * | 1996-01-19 | 2006-11-15 | コマツ電子金属株式会社 | Single crystal pulling device |
| JP4020987B2 (en) * | 1996-01-19 | 2007-12-12 | 信越半導体株式会社 | Silicon single crystal having no crystal defects around the wafer and its manufacturing method |
| JP3531333B2 (en) * | 1996-02-14 | 2004-05-31 | 信越半導体株式会社 | Crystal manufacturing apparatus by Czochralski method, crystal manufacturing method, and crystal manufactured by this method |
| EP1273684B1 (en) | 1997-04-09 | 2005-09-14 | MEMC Electronic Materials, Inc. | Low defect density, vacancy dominated silicon |
| US6379642B1 (en) | 1997-04-09 | 2002-04-30 | Memc Electronic Materials, Inc. | Vacancy dominated, defect-free silicon |
| MY135749A (en) | 1997-04-09 | 2008-06-30 | Memc Electronic Materials | Process for producing low defect density, ideal oxygen precipitating silicon |
| JP3596257B2 (en) * | 1997-11-19 | 2004-12-02 | 三菱住友シリコン株式会社 | Manufacturing method of silicon single crystal wafer |
| TW508378B (en) * | 1998-03-09 | 2002-11-01 | Shinetsu Handotai Kk | A method for producing a silicon single crystal wafer and a silicon single crystal wafer |
| TW589415B (en) | 1998-03-09 | 2004-06-01 | Shinetsu Handotai Kk | Method for producing silicon single crystal wafer and silicon single crystal wafer |
| KR100541882B1 (en) | 1998-05-01 | 2006-01-16 | 왁커 엔에스씨이 코포레이션 | Silicon Semiconductor Substrate and Method of Manufacturing the Same |
| US6224668B1 (en) | 1998-06-02 | 2001-05-01 | Shin-Etsu Handotai Co., Ltd. | Method for producing SOI substrate and SOI substrate |
| US6291874B1 (en) | 1998-06-02 | 2001-09-18 | Shin-Etsu Handotai Co., Ltd. | Method for producing silicon single crystal wafer for particle monitoring and silicon single crystal wafer for particle monitoring |
| JPH11349393A (en) | 1998-06-03 | 1999-12-21 | Shin Etsu Handotai Co Ltd | Silicon single crystal wafer and production of silicon single crystal wafer |
| JP2003517412A (en) | 1998-06-26 | 2003-05-27 | エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド | Method for growing defect-free silicon crystals with arbitrarily large diameter |
| KR20010034789A (en) | 1998-10-14 | 2001-04-25 | 헨넬리 헬렌 에프 | Epitaxial silicon wafers substantially free of grown-in defects |
| US7105050B2 (en) | 2000-11-03 | 2006-09-12 | Memc Electronic Materials, Inc. | Method for the production of low defect density silicon |
| US6846539B2 (en) | 2001-01-26 | 2005-01-25 | Memc Electronic Materials, Inc. | Low defect density silicon having a vacancy-dominated core substantially free of oxidation induced stacking faults |
| JP2003060163A (en) * | 2001-08-14 | 2003-02-28 | Hitachi Ltd | Method for manufacturing semiconductor integrated circuit device |
| US7544583B2 (en) | 2003-09-08 | 2009-06-09 | Sumco Corporation | SOI wafer and its manufacturing method |
| WO2005027217A1 (en) | 2003-09-08 | 2005-03-24 | Sumco Corporation | Soi wafer and its manufacturing method |
| US7446016B2 (en) | 2003-09-08 | 2008-11-04 | Sumco Corporation | Method for producing bonded wafer |
| WO2007137182A2 (en) | 2006-05-19 | 2007-11-29 | Memc Electronic Materials, Inc. | Controlling agglomerated point defect and oxygen cluster formation induced by the lateral surface of a silicon single crystal during cz growth |
| EP2138610A1 (en) * | 2007-03-19 | 2009-12-30 | Mnk-sog Silicon, Inc. | Method and apparatus for manufacturing silicon ingot |
| CN105002557A (en) * | 2015-08-12 | 2015-10-28 | 常州天合光能有限公司 | Gallium, germanium and boron co-doped polycrystalline silicon and preparation method thereof |
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| JPS41404Y1 (en) * | 1964-02-02 | 1966-01-18 | ||
| JPS5556098A (en) * | 1978-10-17 | 1980-04-24 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Method and apparatus for producing si single crystal rod |
| JPS56100195A (en) * | 1980-01-09 | 1981-08-11 | Hitachi Ltd | Growing method for semiconductor single crystal |
| JPS6124240A (en) * | 1984-07-13 | 1986-02-01 | Toshiba Corp | Semiconductor substrate |
| JPS62138384A (en) * | 1985-12-11 | 1987-06-22 | Shin Etsu Handotai Co Ltd | Method and device for pulling single crystal |
| JPS62158189A (en) * | 1985-12-27 | 1987-07-14 | Fujitsu Ltd | Production of single crystal of semiconductor and its device |
| JPS62182191A (en) * | 1986-01-31 | 1987-08-10 | Hidekazu Fujita | Method for controlling shape of pulled-up crystal in cz process and apparatus therefor |
| JPH0639353B2 (en) * | 1986-02-28 | 1994-05-25 | 東芝セラミックス株式会社 | Silicon single crystal pulling device |
| JPS62288191A (en) * | 1986-06-06 | 1987-12-15 | Kyushu Denshi Kinzoku Kk | Method for growing single crystal and device therefor |
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1989
- 1989-04-05 JP JP1086505A patent/JPH0633235B2/en not_active Expired - Lifetime
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|---|---|
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