JPH063368B2 - Mark inspection device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mark inspection device for an electronic component having a mark on the outer periphery of a resin encapsulation portion, and more particularly to an axial lead type electronic component having a bent lead portion. The present invention relates to a mark inspection device that can reliably remove an unmarked electronic component immediately after it as a defective product.

[Prior Art] FIG. 3 (a) is a plan view showing a part of a conventional mark inspection apparatus for an axial lead type electronic component.

This mark inspection device is an axial lead type electronic component,
For example, it is a device for inspecting the presence or absence of printing of the polarity display mark 3 provided on the outer periphery of the resin sealing portion 2 of the diode 1, and the inspection is performed as follows.

First, in a state in which the lead portions of the diode 1 provided with the polarity display mark 3 in the previous step are placed in the recesses 4a, 5a of the pair of opposed conveyor belts 4, 5 arranged continuously in the longitudinal direction. Supplied continuously.

Then, the diode 1 is transferred from the right side to the left side in the drawing together with the conveyor belts 4 and 5, but is opposed to the resin sealing portion 2 of the diode 1, that is, the upper position of the center of the conveyor belts 4 and 5 in the width direction. A mark sensor 6 shown by a broken line is provided at a position directly above.

The mark sensor 6 is an optical sensor, and the band-shaped polarity display mark 3 provided on the outer circumference of the sealing portion 2 of the diode 2 that continuously passes the light narrowed down by the lens immediately below the sensor 6. Is configured to project light to the position.

Since the resin sealing portion 2 of the diode 1 is made of black resin and a white polarity display mark is provided on the outer periphery of the black resin, the projected light is received by the mark sensor 6 as different reflected light. Is incident on the section.

When the reflected light is incident on the light receiving portion of the mark sensor 6, it is converted into an electrical signal inside, and the signal is sent to a determination circuit (not shown), and the polarity display mark 3 is correctly marked on the diode 1. It is automatically determined whether or not this has been done.

For example, in FIG. 3A, if the polarity display mark 2 is missing in the diode D ₃ of the diodes D _{1 to} D ₆ that are continuously conveyed for some reason, a white portion exists. Without, the resin sealing portion 2 is entirely black,
Almost no reflected light is incident on the light receiving portion of the mark sensor 6.

The signal of the mark sensor 6 is sent to the determination circuit, stored as a signal indicating a defective product, and when the conveyor belts 4 and 5 move to a predetermined position, the conveyor belt 4 receives a command signal from the determination circuit. , 5, the diode D ₃ is discharged as a defective product.

In FIG. 3A, guide plates 7 and 8 provided outside the conveyor belts 4 and 5 regulate both ends of the lead portion of the diode 1 to prevent the diode 1 from being displaced in the width direction. This is for ensuring that the mark sensor 6 can detect.

Next, the above series of operation timings will be described with reference to FIG.

First, the output waveform from the mark sensor 6 is as shown in, and the output waveform when the diode D ₁ passes directly under the mark sensor 6 is d ₁ and the output waveform when the diode D ₂ also passes is d ₂ , And so on, d ₄ , d ₅ , and d ₆ are similarly obtained.

The output waveform of the mark sensor 6 is such that when the diode 1 is located directly below the mark sensor 6, the reflected light is incident on the light receiving portion of the sensor 6 with the maximum light amount.
It becomes a sawtooth waveform with a substantially triangular shape.

On the other hand, when the diode 1 does not reach directly below the mark sensor 6, the output waveform becomes zero because there is no reflected light from the resin sealing portion 2.

Next, specifically describing the illustrated one, when the diode D ₃ passes directly under the mark sensor 6, the polarity indication mark 3 is missing in the resin sealing portion 2, so that the black portion is removed. The output from the mark sensor 6 is zero because there is only reflected light, and therefore, the output waveform does not have the same sawtooth waveforms d ₁ and d ₂ as described above.
A flat waveform d _0.

Next, since the polarity indication mark 3 is present in the resin sealing portion 2 of the subsequent diode D ₄ , the sawtooth waveform d ₄ appears in the output waveform. Similarly, the diode D ₅ ,
Sawtooth waveforms d ₅ and d ₆ are output corresponding to D ₆ .

FIG. 3B shows the waveform of a clock pulse for timing the waveform processing described later.

For generation of this clock pulse, a photo sensor (not shown) is arranged in the immediate vicinity of the conveyor belts 4 and 5, and for example, the concave portions 4a, 4a or 5a, 5a of the belts 4 and 5 are detected to detect the mark sensor 6. It is performed by a pulse generation circuit whose timing is adjusted so as to generate a predetermined pulse while there is no output.

That is, each of the diodes D _{1 to} D ₆ in FIG.
A clock pulse is generated when the mark sensor 6 is positioned in the gap (1), and is preset so that the timing relationship between the output pulse and the clock pulse shown in FIG.

Next, the output waveform of the mark memory circuit is as shown in FIG. This output waveform becomes "H" when the level of the output waveform from the mark sensor 6 is a certain level or more, for example, L ₁ or more, and becomes zero when the clock pulse falls.

By the way, in the output waveform of the mark memory circuit, the portion corresponding to the diode D ₃ has no output waveform corresponding to the L ₁ level of the output waveform of the mark sensor 6,
Rising waveforms such as d ₁ and d ₂ will not occur.

Also, the output waveforms of the mark memory circuit are d ₄ , d ₅ , and d _6.
Causes a rising waveform to be generated corresponding to d ₄ , d ₅ , and d ₆ of the output waveform.

Next, the output waveform from the mark memory circuit is output to the next memory shift circuit. In this memory shift circuit, after the clock pulse is output for a predetermined time, the diode D ₃ having no polarity display mark 3 is excluded as a defective product. A signal for doing so is output to the actuator.

That is, the output of the memory shift circuit of FIG.
When the clock pulse rises and when the output waveform of the mark memory circuit is "H", it becomes "H", and when the output waveform is "L", the output of the memory shift circuit also becomes "L". To set.

As a result, the output of the memory shift circuit corresponding to the diode D ₃ becomes “L”, that is, zero because the output waveform of the mark memory circuit is “L”, and is output to a predetermined actuator as a signal for eliminating this as a defective product. Output.

A circuit for realizing the above operation is schematically shown in FIG.

This circuit is composed of a mark sensor 6, a mark memory circuit 9 and a memory shift circuit 10. Then, first, the light emitted from the mark sensor 6 is applied to the polarity display mark 3 of the diode 1, and after receiving the reflected light thereof, it is electrically internally processed and a signal having a sawtooth-like waveform shown in the above output waveform. Is output to the next mark memory circuit 9.

On the other hand, a clock pulse is input to the mark memory circuit 9 via a clock pulse generation circuit (not shown). Then, in the mark memory circuit 9, as shown in FIG. 3B, when the output waveform of the mark sensor 6 becomes the L ₁ level, the state becomes “H”, and the trailing edge of the clock pulse is detected to be “L”. Generate a waveform that is
This output is sent to the memory shift circuit 10.

In addition, a clock pulse is input to the memory shift circuit 10, a rising edge of the clock pulse is detected, and a third pulse is detected.
Output to an actuator (not shown) the output of the memory shift circuit 10 of FIG. (B), the portion of the waveform d ₃ corresponding to the diode D ₃ is to be discharged as a defective product because it is "L".

Meanwhile, if the diode D ₃ to just before the fifth diagram unmarked as shown in (a) diode D ₄ with a bend in the lead portion 1a are mixed, the diode D ₃ is the conveyor belt 4 for the lead portion 1a of the bending , 5 on the next diode D ₄ is approached. In such a case, both the diode D ₃ having a bent lead portion and the diode D ₄ having no polarity indicating mark must be excluded as defective products. In particular, since the diode D ₄ has no polarity display mark, it must be reliably rejected as a defective product.

[Problems to be Solved by the Invention] Since the conventional mark inspection apparatus is configured as described above, a diode without a polarity display mark that is conveyed immediately after a diode with a bent lead portion is determined as a good product. However, there is a problem in that the reliability of the inspected product is reduced.

This phenomenon will be described in detail below.

That is, in FIG. 5 (b), the diode D ₃ is supposed to output the waveform corresponding to the mark detection at the position indicated by the broken line in the (d ₃ ) portion of the output waveform, but the bending of the lead portion 1a As a result, since the resin sealing portion 2 is displaced rearward, it is output at the position of d ₃ shown by the solid line. In that case, since the polarity display mark 3 is missing from the diode D ₄ , there is no output from the mark sensor 6.

Further, in FIG. 5 (b), the clock pulse corresponds to the movement interval of the conveyor belts 4 and 5, so that it is always output at the same time interval.

In the above case, the output of the mark memory circuit is as shown in the figure. The output of this mark memory circuit and the output of the mark memory circuit become "L" at the falling edge of CP2 of the clock pulse, but at the portion (d ₃ ) the mark sensor Since there is no 6 output, d ₃ in the mark memory circuit output is
It rises at the d ₃ portion of the output of the mark sensor 6 and becomes “L” at the fall of the clock pulse CP4.

The following memory shift circuit output is clock pulse CP3.
Of the mark memory circuit output is detected, and the d ₃ portion of the memory shift circuit output becomes "L".

At the rising time of the clock pulse CP4 is eliminated, the memory shift circuit output from the mark memory circuit output d ₄ is "H", "H" next to the d ₄ indicated by oblique lines, originally as a d ₄ is defective In order to do so, the "L" level signal should be sent to the actuator, and the "H" signal, that is, the signal for discriminating the non-defective product should be sent.
There is a problem in that unmarked products are mixed in the products to be inspected, which lowers reliability.

[Object of the Invention] The present invention has been made in order to solve the above problems, and is an electronic device in which a mark such as a polarity display mark is missing after an axial lead type electronic component having a bent lead portion. An object of the present invention is to provide a mark inspection device that can reliably exclude parts as defective even if they are supplied.

[Means for Solving Problems] The mark inspection apparatus of the present invention is an AN that takes the logical product of the inverted output of the clock memory circuit and the output of the mark memory circuit.
It has a D circuit, and is provided with a memory shift circuit for inputting the output of the AND circuit and the clock pulse from the clock pulse generating circuit.

[Operation] In the mark inspection device of the present invention, the AND of the inverted output of the clock memory circuit by the AND circuit and the output of the mark memory circuit is ANDed, and the output of this AND circuit and the clock pulse from the clock pulse generation circuit are input. Then, the memory shift circuit sends out a signal for eliminating defective mark products on the conveyor belt immediately after the electronic component having the bent lead portion.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG.

In FIG. 2, first, as in the conventional case, a mark sensor 6 for irradiating a mark on the surface of the axial lead type electronic component 1 such as a diode with light and generating a predetermined pulse according to the reflected light is provided. ing.

Further, it has a clock pulse generating circuit 11 for generating a clock pulse in synchronization with the moving interval of the conveyor belts 4 and 5 for transporting the electronic component 1 to the position right below the mark sensor 6 at equal intervals. When the clock pulse from the clock pulse generation circuit 11 is input and the output from the mark sensor 6 becomes a value more than a predetermined value, the state becomes "H", and the signal in the "L" state is generated by the falling of the clock pulse. A mark memory circuit 9 for outputting,
When the output of the mark sensor 6 and the clock pulse are input and the output of the mark sensor 6 is not present at the rising edge of the clock pulse, the state is “L”, and when the output of the mark sensor 6 is “H”. A clock memory circuit 12 for outputting a state signal, and this clock memory circuit 1
The AND circuit 13 that takes the logical product of the output of 2 and the output of the mark memory circuit 9 and the output of this AND circuit 13 and the clock pulse from the clock pulse generation circuit 11 are input to mark on the conveyor belts 4 and 5. The memory shift circuit 10 sends out a signal for removing defective products to the outside of the conveyor belt.

Further, the mark memory circuit 9 is provided with a one-shot circuit 9c to which the clock pulse from the well-known comparator 9a, reset circuit 9b and clock pulse generating circuit 11 is input.

Further, the clock memory circuit 12 has a flip-flop circuit 12a whose output side is an inverter circuit 14a.
Is connected to the input side of the AND circuit via.

Next, the operation of the mark inspection device configured as described above will be described first.
A description will be given with reference to FIGS.

First, as in the case described above, the lead portion 1a of the diode D ₃ is bent, and when passing directly below the mark sensor 6 while being close to the next diode D ₄ , the output waveform of the mark sensor 6 is as shown in FIG. 1 (b). The pulse of d ₃ shifts backward as shown in FIG.

Since the diode D ₄ has no mark, the waveform of d ₄ does not appear in the output waveform of the mark sensor 6.

Similarly to the above, the clock pulse is generated by passing through a predetermined portion of the conveyor belts 4 and 5 set in advance, for example, between the concave portions 4a and 5a at regular time intervals, and correspondingly generating pulses at equal intervals. Circuit 11
Done by

Therefore, when the output waveform of the mark sensor 6 and the falling edge of the clock pulse are input to the mark memory circuit 9,
In the mark memory circuit 9, when the output waveform of the mark sensor 6 becomes the L ₁ level, the mark memory circuit output d ₁ becomes “H”.

On the other hand, when the level of the output waveform of the mark sensor 6 becomes equal to or lower than L ₁ , the output d ₁ of the mark memory circuit becomes “L” due to the fall of the clock pulse CP1.

Similarly, the mark memory circuit output d ₂ is generated in the same manner.

Next, the output of the mark memory circuit becomes "L" due to the fall of the clock pulse CP2, and becomes "H" due to d ₃ of the output waveform of the mark sensor 6. That is, it appears as d ₃ (d ₄ ) of the mark memory circuit output.

The output of the mark memory circuit should originally be "L" due to the fall of CP3 in the clock pulse, but since the output waveform of the mark sensor 6 is being output, it remains in the "H" state. And becomes "L" at the trailing edge of CP4 of the subsequent clock pulse.

The mark memory circuit output d ₃ (d ₄ ) is shown in FIG. 1 (a).
Offset in the rearward due to the bending of the lead portion 1a of the diode D ₃ as shown in, moreover diode d ₄ diode D ₃ in order is unmarked, D ₄ with respect to one pulse d ₃ (d ₄ ) only occurs.

Next, the output waveform of the mark sensor 6 and the rising edge of the clock pulse are input to the clock memory circuit 12.

Therefore, when the output waveform of the mark sensor 6 is "L" when the clock pulse CP1 rises, the portion corresponding to d ₁ of the clock memory circuit output is "L". Further, the d ₂ portion corresponding to the clock pulse CP2 is also “L”.
To continue.

Then, since the output is d ₃ of the output waveform of the mark sensor 6 when the rise of CP3, also d ₃ of the clock memory circuit output to "H". The output d _{3 of the} clock memory circuit is brought to the “L” state by the rise of the clock pulse CP4.

The state in which the output d _{3 of the} clock memory circuit is “H” becomes a pulse signal for determining the diode D ₃ described later as a defective product.

Then, at the rising edge of the CP4 used to determine the diode D ₄ shown in FIG. 1 (a), the clock memory circuit output for the state of d ₃ of the mark memory circuit output (d ₄₎ is "H" D ₄ becomes “L”.

Next, FIG. 1 (b) shows an output obtained by inverting the output of the clock memory circuit through the inverter circuit 14, and shows an AND circuit which receives the output of the inverter circuit and the output of the mark memory circuit. 13 output.

At the end of the output waveform of the mark memory circuit output d ₃ (d ₄ ) and the inverter circuit output, the time of the pulse width of the clock pulse CP4 is the mark memory circuit output d ₃
(D ₄ ) is “H”, and the inverter circuit output d ₄ is “H”
Therefore, the AND circuit output becomes "H", but AN
On the output side of the D circuit 13, a well-known delay
The time circuit is connected and a process of shifting the AND circuit output backward by a predetermined time is performed as indicated by a broken line T.

Next, the AND circuit output and the rising edge of the clock pulse are input to the memory shift circuit 10 to obtain the memory shift circuit output. In this case, the clock pulse CP
At the rise of 1, the output of the AND circuit is "H" and thus the output of the memory shift circuit is also "H". When the output of CP3 is "L", the output of the memory shift circuit is "L".

Further, when the clock pulse CP4 rises, it also becomes "L", and when the next clock pulse CP5 rises, the AND circuit output is "H" and the memory shift circuit output also becomes "H".

By the above operation, the outputs d ₃ and d ₄ from the memory shift circuit 10 become signals for discharging both the diodes D ₃ and D ₄ as defective products and are sent to a predetermined actuator.

In addition, even if the polarity display mark 3 is not missing in the diode D ₄ and it is a good product with a mark, if the immediately preceding product is a defective diode D ₃ with a bent lead part, both are unsatisfactory. A good diode is also discharged as a good product, but in such a case it is probabilistically small, and it is more important to surely remove the one without the mark in order to improve the reliability of the inspected product. Is.

Further, in the above embodiment, the diode has been described as an example of an electronic component having a bent lead portion, but it can be widely applied to other axial lead type electronic components such as a resistor.

[Advantages of the Invention] Since the present invention is configured as described above, it is possible to reliably exclude the unmarked electronic component immediately after the axial lead type electronic component having a bent lead portion, and to improve the reliability of the inspected product. It has an excellent effect that it can greatly contribute to the improvement.

[Brief description of drawings]

1 (a) is a plan view for explaining the operation of the mark inspection apparatus of the present invention, FIG. 1 (b) is a waveform diagram showing the operation timing at that time, and FIG. 2 is the mark inspection of the present invention. Block diagram showing the main part of the apparatus, FIG. 3 (a)
Is a plan view showing a part of a conventional mark inspection apparatus for an axial lead type electronic component, FIG. 3 (b) is a waveform diagram showing the operation timing of the mark inspection apparatus, and FIG. 4 is a conventional mark inspection apparatus. Block diagram showing the main parts of the inspection device, No. 5
FIG. 5A is a plan view for explaining the inconvenience in the conventional mark inspection apparatus, and FIG. 5B is a waveform diagram showing the operation timing at that time. DESCRIPTION OF SYMBOLS 1 ... Diode 1a ... Lead part 2 ... Resin sealing part 3 ... Polarity display mark 4, 5 ... Conveyor belt 4a, 5a ... Recessed part 6 ... Mark sensor 9 ... Mark memory circuit 10 ... memory shift circuit 11 ... clock pulse generation circuit 12 ... clock memory circuit 13 ... AND circuit

Claims (1)

[Claims] 1. A mark sensor that irradiates a mark marked on the surface of an axial lead type electronic component with light and generates a pulse in accordance with the reflected light, and the electronic component are transferred to an area immediately below the mark sensor at equal intervals. A pulse generation circuit that generates a clock pulse in synchronization with the movement interval of the conveyor belt, and the output of the mark sensor and the clock pulse from the pulse generation circuit are input, and when the output of the mark sensor exceeds a predetermined value, " A mark memory circuit that outputs a signal in the "H" state and that is in the "L" state due to the falling edge of the clock pulse, and the output of the mark sensor and the clock pulse are input, and the mark sensor is input at the rising edge of the clock pulse. When there is no output of the mark sensor, it is in the "L" state, and when there is an output of the mark sensor, the signal of the "H" state is output. A lock memory circuit, an AND circuit that obtains a logical product of the inverted output of the clock memory circuit and the output of the mark memory circuit, and the output of this AND circuit and the clock pulse are input, and a bent lead portion is provided. A mark inspecting device, comprising: a memory shift circuit that sends out a signal for eliminating defective products on a conveyor belt immediately after an electronic component.