JPH0636636B2 - Digital trunk - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to digital trunks, and more specifically,
For example, the present invention relates to a digital trunk that connects two terminal stations having different data transmission rates such as a digital exchange and a PCM transmission apparatus and performs time slot conversion of a transmission / reception frame.

[Background of the Invention]

Conventionally, in a network of digital exchanges, a high data transmission rate of, for example, 8,192 Mb / s has been adopted in order to increase the signal multiplicity, reduce the size of the apparatus, and improve the economical efficiency. A PCM signal is transmitted by using a non-return-to-zero (NRZ) code system suitable for processing in a logic circuit.

On the other hand, in the PCM transmission device, which is adopted as a standard system in European countries and is widely spread around the world, the A-logarithmic companding law of 13-fold line approximation is adopted as companding characteristics, and each frame is 30 channels (first to fifteenth, seventeenth to thirty-first time slots) for call (voice), two for frame synchronization (zeroth time slot) and a control signal called "signaling" (sixteenth time slot). Channels (in the following description, these time slots other than those for communication are collectively referred to as “signal time slots”), and are configured with a total of 32 channels (32 time slots), and their transmission rates (bit rates)
When 64 Kb / s is the 0th-order group, the first-order group is 2,0
48 Mb / s, the secondary group is 8,448 Mb / s. The encoding method is HDB3 (High Density
The high density bipolar code called "ity Bipolar" is adopted to transmit the PCM signal.

For this reason, when connecting a digital exchange network (hereinafter referred to as a switch network) and a PCM transmission device, an interface (hereinafter referred to as a digital trunk) for interchanging PCM signals is interposed between them. In addition to the HDB3-NRZ signal conversion, processing such as signal time slot extraction / insertion and voice time slot speed conversion is performed.

FIG. 2 shows a frame structure of a PCM signal of the CEPT-1 primary group going from the PCM transmission device to the digital trunk. One frame is 125 μs, and the numbers are “0” to “31”.
Indicates a time slot number (TSNO.). In the 0th time slot, a control signal (signal 1) for synchronization or game alarm is inserted, and in the 16th time slot, a signaling signal and an inter-station signal when the inter-station signal system is the line individual signal system. When the system is the common line signaling system, a call or a signaling signal (signal 2) is inserted.

In the PCM transmission device, 16 multi-frames described above are continuously formed to form one multi-frame.

FIG. 3 shows a frame structure of a PCM signal having a transmission rate of 8,192 Mb / s from the exchange network to the digital trunk. One frame is 125 μs and consists of a total of 128 channels. The 0th to 3rd and the 64th to 67th
8 time slots (TS NO.) Are allocated as channels for control signals (control 1 and control 2) between the exchange and the digital trunk, and the remaining 120 time slots are allocated as channels for speech signals and signaling signals. .

FIG. 4 shows a PCM transmission device 1 and a switch network 1.
2 is a block diagram showing a configuration of a conventional digital trunk provided between the digital trunk and the digital camera.

In FIG. 4, 2A is a code conversion unit provided on the upstream line from the PCM transmission device 1 to the exchange network 11, and 2B is a code conversion unit provided on the downlink line from the exchange network 11 to the PCM transmission device 1. ,
Reference numeral 3 denotes a signal time slot extraction unit that extracts the content of a signal time slot (control signal such as signaling) in the upstream PCM signal frame, and 4A stores the control signal extracted from the signal time slot of the upstream PCM signal frame. A signal memory, 4B is a signal memory for storing a control signal to be inserted into a signal time slot of a downlink PCM signal frame, and 12 is a signal time slot inserting section for inserting a control signal into a signal time slot of a downlink PCM signal frame. Is. Also, 5A, 5B, 8A, 8B, 1
0A and 10B are address selectors, 6A is a transmission rate conversion unit for exchanging the transmission rate on the uplink from the rate on the PCM transmission apparatus 1 side to the rate on the exchange network 11 side, and 6B is the signal transmission rate on the downlink side on the exchange side. Transmission rate converters for converting the speeds of the above to the speeds on the PCM side, 7A and 7B are channel memory for uplink and downlink used for time slot replacement, 9
A and 9B are control memories for storing slot information for time slot replacement control, 13 is a loopback test unit, and 1 is a loopback test unit.
4 is a counter for designating addresses of the signal memories 4A and 4B, 15 is a microprocessor (MPU),
Reference numeral 16 is a control device of the exchange, 17 is a highway for connecting the inputs and outputs of a plurality of digital trunks to the exchange, 1
8 is the microprocessor 15 and the exchange controller 16
The link line connecting between and is shown.

The PCM transmission device 1 and the exchange network 1
The highway 17 between 1 and 8 is, for example, 8,192 Mb /
A digital trunk 19 having a transmission rate of s and a transmission rate of 2,048 Mb / s is connected in a four-circuit multiple manner to match the transmission rate.

In the conventional digital trunk 19, the upstream PCM signal shown in FIG. 2 transmitted from the PCM transmission device 1 is converted from the HDB3 code to the NRZ code in the code conversion unit 2A.
After being converted into a code, the signal time slot extraction unit 3 extracts the information of the signal time slots whose TSNO.s are "0" and "16". The counter 14 is TSNO.
8,192 Mb / based on "0" time slot
s clock counting operation, and the frame number and time slot number (T
The count value corresponding to SNO.) Is output as a memory address or a timing signal.

T extracted by the signal time slot extraction unit 3
The contents of the signal time slots of SNO. "0" and "16" are written in the signal memory 4A in the order of frame No. and TSNO. According to the address given from the counter 14 via the address selector 5A. The content of the signal time slot stored in the signal memory 4A is M
It is sequentially read by the PU 15 and is sent as control information to the control device 16 of the exchange via the link line 18.

TS NO. "1 to 15", "17 to 3" in the PCM signal
The information of the call time slot of "1" directly passes through the loopback test section 13 during normal operation, and is transmitted to the transmission rate conversion section 6
It was sent to A and quadrupled from 2,048Mb / s to 8,1
After the speed is converted to 92 Mb / s, it is sequentially written in the speech path memory 7A according to the address corresponding to the time slot number (TSNO.) Given from the counter 14 through the address selector 8A.

The MPU 15 has a highway 17 assigned by the control device 16.
The idle time slot number of the above 120 time slots is written in the control memory 9A in association with the address given through the address selector 10A.

The empty time slot number stored in the control memory 9A is read at the address corresponding to the TSNO. Designated by the counter 14 which is input through the address selector 10A, and the corresponding call time slot information is read through the address selector 8A. Is given to the speech path memory 7A. As a result, the channel memory 7
Call time slot information is randomly read from A, and the exchange network 1 is sent via the highway 17.
1 (random read).

On the other hand, from the exchange network 11 to the highway 17
The downward PCM signal shown in FIG. 3 sent to the digital trunk 19 via the telephone is sequentially stored in the speech channel memory 7B in the same manner as the above-described upward speech time slot is written in the speech channel memory 7A. , Then read at random, and the transmission rate conversion unit 6B causes
The speed is converted from 92 Mb / s to 2,048 Mb / s.

Of the time slot information, the control information to be set in the signal time slots whose TSNO.s in FIG. 2 are "0" and "16" is the frame given by the MPU 15 instructed by the control device 16 via the address selector 5B. It is written in the signal memory 4B in accordance with the address corresponding to the signal, is read by the address corresponding to the frame No. and slot No. given from the counter 14 via the address selector 5B, and is sent to the signal time slot inserting unit 12. .

The signal time slot insertion unit 12 uses the call time slots (TSNO. "1 to 15" and "17 to" 31 ").
In the period corresponding to, the output from the transmission rate converter 6B is selected and sent to the code converter 2B, and in the period corresponding to the signal time slot (TSNO. “0” and “16”), the signal memory 4B is selected. The control information output from the above is sent to the code conversion unit 2B.

The code conversion unit 2B converts the NRZ code PCM signal received from the signal time slot insertion unit 12 into an HDB3 code PCM signal and sends it to the PCM transmission apparatus 1.

The above-described operation is in the case of the line individual signal system, but in the case of the common line signal system, the signal time slot with TSNO. "16" is used for the data information for the common line or for the call, so that the call is performed. The channel memories 7A and 7B and the control memories 9A and 9B are configured to be able to process time slot information having a TSNO. Of "16", and the signal time slot inserting unit 12 has a TSNO. Of "16".
The time slot information of is configured to be able to pass. That is, the call memories 7A and 7B have an information storage capacity of 128 time slots.

The loopback test unit 13 is for checking the normality of the connection operation between the exchange network 11 and the digital trunk 19.

When the loopback test execution command is given from the control device 16 to the MPU 15, the loopback test unit operates under the control of the MPU, and the downlink P received from the transmission rate conversion unit 6B is received.
Information for one arbitrary time slot of the CM signal is temporarily stored, and the information is inserted into an arbitrary time slot of the upstream PCM signal and returned. On the side of the network 11 of the exchange, the normality of the connection state between the devices can be confirmed by checking the content of the downlink PCM signal transmitted by itself and the content of the received PCM signal returned by the return test section 13.

Here, the capacity required by each memory of the conventional digital trunk shown in FIG. 4 is calculated. One multiframe has TBNO. Of "0" and "1" for each frame.
Since it consists of 16 frames having two time slots of "6", the signal memories 4A and 4B each have 32w x 8 bits, and the channel memories 7A and 7B have 8, 1
The information amount of one frame (128 time slots) of 92 Mb / s is 128 w × 8 bits, and the control memories 9A and 9B each have 128 w × 7 bits as the address information amount of 128 parts, for a total capacity of 4,352 bits. Will be needed.

Further, in order to access the six independent memories, it is necessary to prepare six sets of control circuits such as address selectors. If a plurality of time slots are handled at the same time and a loopback test is performed, a plurality of sets of memory ICs and control circuits are required, and the number of parts increases, the cost is high, and the size cannot be reduced.

[Object of the Invention]

An object of the present invention is to provide a digital trunk having a time slot conversion function, which can reduce the number of parts, can be downsized at low cost.

[Outline of Invention]

To achieve the above object, a digital trunk according to the present invention comprises a first PCM signal frame having a first transmission rate received from a digital converter and a second PCM signal frame having a second transmission rate received from a PCM transmission device. A speech channel memory for temporarily storing information of each time slot of a PCM signal frame, a control memory for storing address information for accessing the speech channel memory, the control memory in a predetermined order, and The communication path memory includes address generating means for generating an address for periodically accessing the communication path memory, and a processor for communicating with a control device of the digital exchange, and the communication path memory receives the first (down) and second received signals. An uplink call area for storing call information and control information (signal) of the (uplink) PCM signal frame,
A downlink call area, an uplink signal area, and a downlink signal area are provided, and the control memory is provided with an uplink area and a downlink area for storing call information read addresses from the uplink call area and the downlink call area of the call path memory. A read / access for accessing the communication path memory and the control memory from the address generation means or the microprocessor at a predetermined frequency and timing determined by the relationship between the transmission rates of the first and second PCM signal frames.
It is characterized in that a write address is generated and the call information is read from the call path memory at the address read from the control memory.

According to the structure of the present invention, the communication path memory of the first PCM signal frame handled by the digital exchange and the time slot of the second PCM signal frame handled by the PCM transmission device are stored in the communication path memory according to the corresponding relationship. By controlling the access frequency and order of each area, it is possible to convert the time slot and the speed between the first and second signal frames with a simple configuration.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a digital trunk 27 according to the present invention connected between a PCM transmission device and a switching network 11.
FIG. 3 is a block configuration diagram showing an embodiment of FIG. In the figure,
20 is a channel memory, 21 and 23 are address selectors,
Reference numeral 22 is a control memory, 24 is a multiplexer, 25 is a demultiplexer, and 26 is an address creating unit. Other circuit elements, which are the same as those in FIG. 1, are designated by the same reference numerals.

FIG. 5 (a) is an allocation diagram of the storage area of the time slot information stored in the above-mentioned communication path memory 20, and stores the communication time slot information of the PCM signal for up / down correspondence in one memory. Areas (hereinafter, referred to as a call area) 50 and 52, and areas (hereinafter, referred to as a signal area) 51 and 53 for storing control time slot information of a PCM signal for uplink / downlink are provided.

FIG. 5B is an area allocation diagram of the control memory 22 for storing address information for controlling the reading of the time slot information stored in the speech path memory 20,
Uplink area 60 for storing address information for time slot information access of an upstream PCM signal frame from the PCM transmission device to the exchange, and an address for time slot information access of a downstream PCM signal frame from the exchange to the PCM transmission device It comprises a down area 61 for storing information.

In FIGS. 5A and 5B, the numerical value attached to the left side of the memory block indicates the number of bytes, and the numerical value attached to the right side indicates the memory address.

In this embodiment, the speech path memory 20 includes the upstream speech area 5
0 is 32w × 8bit, upstream signal area 51 is 32w × 8bi
t, the downlink communication area 52 is 128 w × 8 bits, the downlink signal area 53 is 32 w × 8 bits, and a total of 224 w × 8 bits (= 1,7
It has a storage capacity of 92 bits). In the control memory 22, the upstream area 60 is 128 w × 8 bits, and the downstream area 6 is
1 is 32w × 8bit, total 160w × 8pbit (= 128
It has a storage capacity of 0 bit).

FIG. 6 shows the allocation of the writing / reading timing of the time slot information to the speech path memory 20.

In this example, 1 of the CEPT method handled by the PCM transmission device 1 is used.
Each time slot of the next group frame is divided into 16 as shown by the timing numbers 0 to 15 in the middle part of FIG. 6, and within each timing period (244 ns), in the pre-allocated area as shown in the figure. A write or read operation is performed, whereby, as described later, (1) transmission rate conversion from 2,048 Mb / s to 8,192 Mb / s or vice versa, (2) signal time It is possible to perform extraction / insertion of control information in slots, and (3) loopback test of multiple time slots.

The details of the write / read operation of the speech path memory 20 performed based on the timing allocation shown in FIG. 6 will be described below with reference to the time chart shown in FIG.

First, the conversion of the PCM frame transmission speed will be described. The speed difference between the PCM signal transmission speed of 8,192 Mb / s on the exchange network side and the signal transmission speed of 2,048 Mb / s on the PCM transmission device side is 4 times. Therefore, it is necessary to allocate four time slots of a PCM signal of 8,192 Mb / s to one time slot of a PCM signal of 2,048 Mb / s.

Therefore, timing numbers 0 to 3 in the PCM signal of 8,192 Mb / s are 4N, 4 to 7 are 4N + 1, and 8 to 1
1 is allocated to 4N + 2 and 12 to 15 are allocated to 4N + 3,
The time slot is 8,192 Mb / s.

Call time slots (TSNO. "1-15" and "1"
7-31 "), regarding an upstream signal that performs speed conversion from 2,048 Mb / s to 8,192 Mb / s, within the processing period (3,906 ns) of one 2,048 Mb / s time slot. ), It is necessary to perform a write operation (processing of input from the PCM transmission device 1) to the upstream call area 50 once, and a read operation (output processing to the highway 17) from the call area 50 four times. In the example shown in FIG. 6, the write operation is performed at the timing number 0, and the read operation is performed at the timing numbers 1, 5, 9, and 13.

On the other hand, regarding downlink communication time slots,
Within the period of one 048 Mb / s time slot (3,
In 906 ns, it is necessary to perform the write operation (input processing from the highway 17) to the downlink call area 52 four times and the read operation (output processing to the PCM transmission device) once from the call area 52. In the example shown in FIG. 6, the write operation is performed at timing numbers 2, 6, 10, and 14, and the read operation is performed at timing number 3.

Next, the control information extraction / insertion operation in the signal time slot and the integration of the signal memory and the communication path memory according to the present invention will be described.

Signal time slot (TSNO. "0" and "16")
At the time of processing, in the line individual signaling system, control information is extracted / inserted in both time slots “0” and “16”, and in the common line signaling system, control information is extracted / inserted in time slot “0”. Then, in the time slot “16”, it is necessary to pass information (eg, hand over to the network 11).

Therefore, in the present embodiment, with respect to the upstream signal time slots (TSNO. "0" and "16") which are the inputs from the PCM transmission device, both of the above formulas have a timing number "" in order to pass information. 0 "for upstream call area 50
Further, for the information extraction, the write operation is performed in the upstream signal area 51 at the timing number “4”.

The information read operation from the upstream signal area 51 is performed only when there is a request from the MPU 15. In the embodiment, the timing number 15 (indicated by * in FIG. 6) is used, and this read operation can be executed in any time slot in one frame.

On the other hand, the downlink PCM that is output to the PCM transmission device
Regarding signal, TSNO. "0" in the line individual signal system
And “16”, and in the common line signaling method, it is necessary to insert control information in the time slot of TSNO.

Because of this insertion operation, in the present embodiment, in both of the above methods, the read operation of the downlink signal area 53 is performed at timing number 3, and in the case of the common line signaling method, TSN.
In the time slot of O. "16", in order to pass the information, the read operation of the downlink communication area 52 is performed at the same timing (timing number 3) as described above (shown by * 2 in FIG. 6). ).

The write operation to the downstream signal area 53 is performed by the MPU1.
In this embodiment, which is performed only at the time of a request from 5, the timing number is “8” (shown by * 1 in FIG. 6), and this write operation is executed in an arbitrary time slot in one frame. It is possible. The write and read operations other than the timing numbers 3 and 4 in the signal time slot process described above are the same as the write and read operations in the call time slot process described above.

Next, the operation of the digital trunk shown in FIG. 1 will be described with reference to FIGS. 5 (a), 5 (b), 6 and 7.

The 2,048 Mb / s PCM signal input from the PCM transmission device 1 to the digital trunk is transmitted to the code conversion unit 2A.
After the conversion from the HDB3 code to the NRZ signal,
It is input to the speech path memory 20 via the multiplexer 24.

In the processing of the call time slot, as shown in FIG. 7, TSNO. "1" to "15", "17" to "31".
The time slot information (in the figure, the case of TS NO. 5) is stored in the channel memory 20 according to the address signal given from the address creating unit 26 via the address selector 21 at the timing of the timing number “0”. Data is sequentially written in the upstream call area 50 (32 words) (sequential write).

On the other hand, the MPU 15 responds to a command from the control device 16 and outputs the upstream area 60 (128 words) of the control memory 22.
The read address of the upstream call area of the call path memory 20 is written in the. That is, the read address of the call area is written in the storage location in the up area 60 corresponding to the empty time slot number in the 128 time slots on the highway 17.

The read address is for each call time slot (TS
No. 1-15, 17-31) timing number is 1,
At the timings of 5, 9, and 13, the address generated by the address generating unit 26 is read by giving it to the control memory via the address selector 23, and the selector 21 is read.
Is supplied as a read address to the speech path memory 20 via the.

As a result, the content of the upstream call area 50 is read at any of the timing numbers 1, 5, 9, and 13 of the call time slots (FIG. 7 shows an example of reading at the timing number 13). Then (random read), the data is sent out of the exchange network via the demultiplexer 25 and the highway 17. In addition, MPU1
Since 5 designates one of the 128 time slots, the call information is read out at any one of the timing numbers 1, 5, 9, 13 and the remaining three are so-called silent PCM. Become a signal.

On the other hand, in the signal time slot process, the TS NO. Is "0" as in the above-described process of passing the call time slot.
And the contents of the time slot of "16" are written in the upstream call area 50 as the information for passage at the timing of the timing number "0", and further as the information for extraction at the timing of the timing number "4". Write in the signal area 51.

In this example, the PCM signal from the PCM transmission device is 16
Since one multi-frame is composed of the frames (frame Nos. 0 to 15), the signal of the time slot of TS NO. “16” corresponds to one multi-frame, that is, in the upstream signal area 51 of the speech path memory 20. 1 multiframe 16 time slots can be stored. Similarly, the TSNO. “0” time slot can also store 1 multi-frame 16 time slots,
A storage capacity of 32 time slots in total is prepared in the signal area 51.

In the signal area 51, when the time slots of TSNO. "0" and "16" of each frame are received, 1 is respectively received.
The writing process is performed once, and this is repeated 16 times to sequentially perform the writing operation.

In the address creating unit 26 that counts the frame NO. And TSNO. (0 to 15) output from the counter 14 for the above write operation, the TSNO. Is "0" or "16" and the timing number is "4". , The address corresponding to the signal area 51 is generated.

For example, in the case of the memory configuration shown in FIG. By generating an address having the relationship of (1) and supplying it to the speech path memory 20 via the address selector 21, the TS for one multi-frame is added to the upstream signal area 51.
The time slot information of NO. "0" and "16" is written.

The information written in the upstream signal area 51 in this way is the timing with the timing number "15" (with * 1)
, The address (ADDRES
S) is read to the data line (DATA2) and the link line 18
Is sent to the control device 16 via.

The call information of the PCM signal frame of 8,192 Mb / s output from the network 11 of the exchange to the highway 17 has the timing numbers "2", "6", "10",
At the timing of "14", the TSNO. Of the frame of 8,192 Mb / s output from the counter 14 is used as a write address and sequentially written in the downlink communication area 52 of the communication path memory 20 via the multiplexer 24.

To write the control information in the downlink signal area 53 of the communication path memory 20, the MPU 15 that receives an instruction from the control device 16
However, at the timing number 8 of the corresponding time slot,
The frame order is performed by supplying address and control information to the address line (ADDRESS) and the data line (DADA1), respectively.

The information thus stored in the downlink communication area 52 and the downlink signal area 53 is read as follows.

Call time slot (TS NO.0-15, 17-31)
Information of the signal time slot (TSNO.16) in the common line signaling method is output from the counter 14 at the timing of the timing number "3".
The read address of the downlink call area 52 is read from the downlink area 61 of the control memory 22 according to NO., And the read address is given to the call path memory 20 as an address so that the read address is read from the downlink call area 52 and coded via the demultiplexer 25. Send to the conversion unit 2B.

On the other hand, signal time slots (TSNO. "0" and "1"
6 ”: However, TSNO.“ 0 ”in case of common line signaling
(Only), the address generated by the address creating unit 26 corresponding to the frame No. output from the counter 14 at the timing of the timing number “3” is stored in the communication path memory 20 via the address selector 21. By giving it, it is read from the downlink signal area 53 and sent to the code conversion unit 2B via the demultiplexer 25. The code conversion unit 2B converts the NRZ code PCM signal read from the speech path memory 20 into an HDB3 code,
It is sent to the PCM transmission device 1.

Next, a loopback test having a simultaneous processing function for a plurality of time slots performed by the digital trunk 27 will be described.

By giving a command for the loopback test from the control device 16 to the MPU 15, the MPU 15 is controlled by the control memory 22.
The read address of the downlink call area to be given to the call path memory 20 is written in the uplink area 60 of FIG. Further, the read address is read at timings of timing numbers 1, 5, 9, and 13 which are read timings of the upstream communication area, and the downstream communication area of the communication path memory 20 is accessed based on the read address, so that the converter side The contents of the plurality of time slots of the PCM signal sent from the highway 17 to the highway 17 are read from the communication path memory 20 and inserted into the plurality of time slots of the PCM signal directed to the highway 17, thereby returning to the exchange network.

It should be noted that the MPU 15 is caused to write the read address of the upstream call area of the call path memory 20 in the downlink area 61 of the control memory 22, and the time slot information of the upstream call area 50 is read at the read timing (timing number 3) of the downlink call area. By reading, the P sent from the PCM transmission device 1
It is also possible to return any time slot of the CM signal to the PCM transmission device 1 again.

According to the above embodiment, the six memories (total capacity 4, 3,
The number and capacity of memories can be greatly reduced (2 memories, total capacity 3,272 bits) compared to the conventional time slot conversion type digital trunk that required 52 bits), and each memory is required. The number of control circuits can also be significantly reduced.

〔The invention's effect〕

As described above, according to the present invention, the number and capacity of memories for time slot conversion, and the number of control circuits required for each memory can be significantly reduced.
The digital trunk structure can be simplified, the cost can be reduced, and the size can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital trunk to which the present invention is applied, FIG. 2 is a block diagram of a PCM signal frame of CEPT system-primary group, and FIG. 3 is a transmission rate of 8,192 Mb / s. FIG. 4 is a block diagram showing an example of a conventional digital trunk, and FIGS. 5 (a) and 5 (b) are a channel memory used in the embodiment of the present invention, respectively. FIG. 6 is a time chart showing an example of read / write operation of the channel memory, FIG. 6 is an area allocation diagram of the control memory, FIG. 6 is an allocation diagram of read / write timing of the channel memory. 1 ... PCM transmission device, 2A, 2B ... Code conversion unit, 3 ...
Signal time slot extraction unit, 4A, 4B ... Signal memory,
5A, 5B, 8A, 8B, 10A, 10B, 21, 23
... Address selector, 6A, 6B ... Transmission speed conversion unit, 7
A, 7B, 20 ... Speech path memory, 9A, 9B ... Control memory, 11 ... Network of converter, 12 ... Signal time slot insertion section, 13 ... Loopback test section, 14 ... Counter,
15 ... MPU, 16 ... Control device, 17 ... Highway, 1
8 ... Link line, 19, 27 ... Digital trunk, 24
... multiplexer, 25 ... demultiplexer, 26 ... address creating section.

Claims (2)

[Claims] 1. A digital exchange (11) which communicates by a first PCM signal frame having a first transmission rate consisting of a plurality of call time slots for transmitting call information and a plurality of signal time slots for transmitting control information. And a plurality of call time slots for transmitting call information and at least one signal time slot for transmitting control information and having a second transmission rate different from the first transmission rate.
A digital trunk (27) connected to a PCM transmission device (1) communicating with a CM signal frame
And a first PCM signal frame received from the digital exchange and a second P signal received from the PCM transmission device.
A speech channel memory (20) for temporarily storing information of each time slot of the CM signal frame, a control memory (22) for storing address information for accessing the speech channel memory, and a predetermined memory. A processor for performing communication between address generation means (14, 26) for periodically generating addresses for accessing the control memory and the speech path memory in order, and the control device (16) of the digital exchange ( 15), and the call path memory (20) includes an uplink call area (50) for temporarily storing information on a call time slot of the received second PCM signal frame; Upstream signal area (51) for temporarily storing information of signal time slots of PCM signal frame
A downlink call area (52) for temporarily storing the received call information of the call time slot of the first PCM signal frame, and a control to be inserted in the signal time slot of the first PCM signal frame. And a downlink signal area (53) for temporarily storing information, wherein the control memory (22) uses the read address of the uplink call area (50) of the call path memory as the first PCM signal frame. Upstream area (60) for storing in association with each call time slot
And a downlink area (61) for storing the read address of the downlink call area (52) of the call path memory in association with the call time slot of the second PCM signal frame, and the address generating means. Alternatively, from the processor (15) to the upstream communication area (50) and the downstream communication area (52) at a predetermined frequency and timing determined according to the relationship between the first transmission rate and the second transmission rate. A write address of call information, a read address of address information from the upstream area (60) and the downstream area (61), the upstream signal area (51) and the downstream signal area (5)
3) A control information write address, an up signal area (51) and a call information read address from the down signal area (53) are periodically generated, and these addresses or the up area of the control memory (22) are generated. (60) and the downlink area (61) are used to access the communication path memory to determine the time slot between the first PCM signal frame and the second PCM signal frame. A digital trunk characterized by conversion. 2. The digital trunk according to claim 1, wherein the communication path memory (20) communicates with the PCM transmission device by a multi-frame in which a plurality of the second PCM signal frames are divided into blocks. 2.) A digital trunk characterized in that each of the upstream signal area (51) and the downstream signal area (53) has an information storage capacity corresponding to the number of signal time slots included in one multiframe.