JPH0638146B2 - Method and apparatus for controlling light emission timing - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emission timing control method and apparatus in an image pickup system, and more particularly to a light emission timing control method and apparatus suitable for a solid-state image pickup device such as a CCD camera.

[Prior Art] A CCD camera can be used to capture an instantaneous image of a subject as an electric signal. FIG. 9 shows a schematic configuration diagram of a conventional image pickup system of this type.

In this imaging system, when the moving body 91 reaches the image capturing position, the image is captured by the CCD camera 92 into the image processing device 93 as a still image. The sensor 94 detects that the moving body 91 has reached the image capturing position. Upon receiving the detection signal 95 from the sensor 94, the one-screen capture circuit in the image processing device 93 sends a light emission signal 97 to the strobe 96 to cause the strobe to emit light, and the CCD camera 92 composites one field or one frame. The signal 98 is captured in the internal memory as an image for one screen.

The CCD camera 92 receives vertical synchronization and horizontal synchronization signals VDo and HDo for external synchronization from the image processing device 93. However, if the CCD camera 92 is an internal synchronization type, CC
Vertical and horizontal synchronizing signals VDi, H in the D camera 92
Since Di is generated, an external synchronization signal is unnecessary. Hereinafter, VDo and VDi are collectively treated as VD, and HDo and HDi are collectively treated as HD.

In the imaging system of FIG. 9, there are the following two types of strobe 96 light emission methods.

Light emitting method-1) After receiving the detection signal 95, wait until the vertical synchronizing signal VD of the CCD camera 92 is received and output the light emitting signal 97.

Light emission method-2) Upon receiving the detection signal 95, the light emission signal 97 is immediately output.

[Problems to be Solved by the Invention] However, in such a conventional image pickup system, the synchronization signal of the CCD camera and the detection signal 9 of the sensor 94 are used.
Since it is asynchronous with 5, the light emission timing control method has the following problems.

That is, in the light emitting method-1), due to the waiting time T,
The light emission is delayed for the longest period of the vertical synchronization (about 16.7 mS), and the moving body at the speed v captures the image at the position displaced by the distance vT.

In the light emitting method-2), when the light emission timing happens to overlap with the period (about 10 μS) of charge transfer from the photo sensor unit of the CCD to the vertical transfer unit, the image of the field being transferred is not exposed, It becomes a black image.

The present invention has been made in view of such a conventional problem, and by waiting only for the minimum period of charge transfer without waiting for the strobe light emission timing as much as the waiting time, , The distance vT is reduced, and one field is prevented from becoming a black image.

[Means for Solving Problems] The present invention has been made in order to achieve such an object, and the light emission timing control method of the first invention responds to a still image of a subject in response to a capture signal. And a light emission timing control method in an imaging system for generating a light emission trigger pulse for instructing a light emission timing of a light emitting means, when the light emission trigger pulse is generated according to the capture signal, a light emission period by the light emission trigger pulse , Determines whether or not it overlaps with a predetermined light emission prohibition period, and if the overlap does not occur, generates the light emission trigger pulse in response to the generation of the acquisition signal, and if the overlap occurs, the After the capture signal is generated, the light emission trigger pulse is generated after waiting for the end of the light emission inhibition period.

A light emission timing control device of the second invention of the present application is a generation timing control device in an imaging system for generating a light emission trigger pulse for instructing a light emission timing of a light emitting means in accordance with a capture signal of a still image of a subject. A first pulse generating means for generating a first pulse having a pulse width nT, which includes a period and is synchronized with a reference clock having a period T; and a pulse width (n + 1) T synchronized with the reference clock in response to the acquisition signal. The second pulse generating means for generating a second pulse and both outputs of the first and second pulse generating means are received, and when the second pulse does not overlap with the first pulse, the second pulse is emitted as it is. When the second pulse overlaps the first pulse, the second pulse portion is output as a trigger pulse and extends from the first pulse. It is characterized in that comprises a pulse synthesizing means for outputting a light emitting trigger pulse.

In the first and second inventions of the present application, the light emission prohibition period is, for example, a charge transfer period of a CCD camera. [Operation] The light emission timing control method of the present invention is, in principle, the above conventional light emission method-2), That is, a method of outputting light immediately after receiving the detection signal is adopted, but only when the light emission timing overlaps the light emission prohibition period, by delaying the light emission timing until the end of the light emission prohibition period,
This eliminates exposure mistakes and minimizes image misalignment. The image shift according to the present invention occurs only when the timing of the image capture signal (light emission command) overlaps with the light emission prohibition period, and the delay time is at most about one horizontal synchronization period, so the image shift is allowed. It is within the range.

[Embodiment] An embodiment of the present invention will be described in detail below with reference to FIGS. 1 to 8.

FIG. 1 shows a block diagram of a one-screen capture circuit including a light emission timing control device according to the present invention. In this example,
An interlaced internal synchronization type / frame accumulation type CCD camera for capturing one frame will be described.

The relationship between the strobe light emission timing and the composite signal will be described with reference to FIG. 2 before the detailed description of the one-screen capture circuit of FIG.

The waveform 21 is the vertical synchronizing pulse VD, and the period between one VD pulse and the VD pulse immediately after is called one field. The waveform 22 is the shift gate pulse SG. This SG pulse is a pulse indicating the timing of transferring the charge accumulated in the photo sensor unit to the vertical transfer line, and is usually not output to the outside of the camera. The SG pulse is the time unique to each camera after the rise of the vertical sync pulse VD (15H = 15 x 63.5 = 952.5 µS in Fig. 2).
After that, it stands up.

The output timing of the composite signal from the CCD camera is divided into two cases (1) and (2) in FIG. 2 depending on whether the strobe (instantaneous light emitting means) emits light before or after the SG pulse. The marks 26 and 28 indicate the timing of light emission and the waveform 2
Reference numerals 7 and 29 denote composite signals.

Case (1): This corresponds to the case where the strobe fires before the SG pulse. In this case, S immediately after the strobe fires.
During the G pulse period, charge transfer for one field in one frame 24 is performed and then the composite signal 27 for that field is output. During the next SG pulse period, charge transfer for the other field is performed and then the composite signal for that field. The signal 27 is output.

Case (2): This corresponds to the case where the strobe emits light after the SG pulse, and in this case, it is effective as in case (1) within one frame 25 consisting of two fields following the field where the strobe emits light. A composite signal is output.

Referring back to FIG. 1 again, the configuration of the circuit shown in FIG. 1 will be described.

The 1-screen capture circuit of FIG. 1 is composed of a memory control section (A / D converter 12, memory 18, sync signal separation section 1 in the upper part of FIG. 1).
4, the address / write pulse generator 17, the gate 112, and the memory write controller 110), and the light emission timing control device portion (delay pulse light emitter 3) of the present invention at the bottom of FIG.
Pulse generator 4 with pulse width nT, pulse width (n + 1) T
Pulse generator 5 and pulse synthesizer 7). The delayed pulse generator 3 and the pulse generator 4 are the same as the first embodiment of the present invention.
It constitutes a pulse generating means. The pulse generator 5 constitutes the second pulse generating means of the present invention.

The delay pulse generator 3 includes a set / reset flip-flop (SR F / F) 113 and a D-type flip-flop (DF / F / F).
F) 114 and m-ary synchronous counter 115. SR F / F11
3 receives the VD pulse 15 at its S input terminal and the carry output of the counter 115 at its R input terminal. The DF / F 114 receives the Q output of the SR F / F 113 at the D input terminal and the clock 127 at the clock input terminal. Counter 1
The 15 receives the Q output of the DF / F 114 at the enable (en) terminal and the clear (CLR) terminal, and receives the clock 127 at the clock input terminal. The delay pulse generator 3 delays the VD pulse 15 by a predetermined time in synchronization with the clock 127.
The D'pulse 116 is output. That is, the delay pulse generator 3 outputs the time (mT ₀ + α) from the generation of the VD pulse 15.
Later, the VD 'pulse 116 is generated. Here, m is an integer of 2 or more, T ₀ is the period of the clock 127, and α is a time error smaller than T ₀ . However, when it is desired to obtain a delay time of m = 1, the m-ary synchronization counter 115 may be deleted and the Q output of the DF / F 114 may be directly input to the R input terminal of the SR F / F 113.

The pulse generator 4 comprises an SR F / F 117, a DF / F 118 and an n-sync counter 119. SR F / F117 has V at the S input
The D'pulse 116 is received, and the carry output of the counter 119 is received at the R input terminal. DF / F 118 is SR F / F 117 at D input terminal
And the clock 126 is received at the clock input terminal. The counter 119 receives the Q output of the DF / F 118 at the enable terminal and the clear terminal, and receives the clock 126 at the clock input terminal. The Q output of the DF / F 118 is used as the inhibition pulse 120 having a pulse width nT. Here, T is the period of the clock 126, and n is an integer of 2 or more. However, n = 1
If you want to obtain the prohibited pulse with the pulse width T, the n-ary synchronous counter 119 is deleted and the Q output of DF / F 118 is directly S-
You may make it input into the R input terminal of RF / F117.

The pulse generator 5 includes SR F / F 121, DF / F 122 and (n
+1) It consists of a base synchronization counter 123. SR F / F121 is S
The input terminal receives the image capturing pulse 124, and the R input terminal receives the carry output of the counter 119. The image capture pulse 124 is
This is a signal that the CPU in the image processing apparatus receives and outputs the detection signal 95 (FIG. 9). DF / F 122 has SR at D input
Receives the Q output of F / F 121 and outputs the clock 12 to the clock input terminal.
Take 6. The counter 123 receives the Q output of the DF / F 122 at the enable terminal and the clear terminal, and receives the clock 126 at the clock input terminal. The Q output of the DF / F 122 is used as a pulse 125 having a pulse width (n + 1) T. here,
n is an integer of 1 or more.

The pulse synthesizer 7 comprises an AND gate 128 having an inverting input terminal and a non-inverting input terminal, receives an inhibit pulse 120 at its inverting input terminal, and receives a pulse 125 at its non-inverting input terminal. AN
The output of the D gate 128 is used as a strobe light emission trigger pulse (hereinafter, simply referred to as strobe light emission pulse) 129.

Next, the respective operations of the delay pulse generator 3 and the pulse generators 4 and 5 will be described with reference to FIGS. 3A to 5B.

First, reference will be made to the delay pulse generator 3 of FIG. 3A and the operation timing diagram of FIG. 3B. VD pulse 15 is SR
When applied to the S input terminal of the F / F 113, the Q output of the SR F / F 113 rises as shown in the waveform. Then the clock
The first pulse of 127 causes DF / F 1 as shown in the waveform.
14 Q output rises. This Q output enables the m-ary synchronous counter 115 (which has already been cleared), so that this counter 115 thereafter counts the clock 127. When the counter 115 counts (m-1) clock pulses, the carry signal, that is, the VD 'pulse 116
Is output. This VD 'pulse 116 causes SR F / F113
Is reset and the next clock pulse causes the DF / F 114
Q output returns low. As a result, the counter 115 is disabled and cleared. In this way
The delay pulse generator 3 generates the VD ′ pulse 116 after a time (mT ₀ + α) from the generation of the VD pulse 15.

Next, refer to FIGS. 4A and 4B. SR F / F 117 is V
It is set by the D'pulse 116 and the Q output rises as shown in the waveform. Then, the first pulse of the clock 126 causes the Q output of the DF / F 118 (inhibit pulse 120) to rise. As a result, the n-ary synchronous counter 119 causes the clock 126 to
Counting is started, and (n-1) clock pulses are received to generate a carry output as shown in the waveform. This carry output resets the SR F / F 117 and returns the waveform to low. As a result, the next clock pulse
The inhibit pulse 120, the Q output of the DF / F 118, returns low, disabling and clearing the counter 119.
In this way, the pulse generator 4 has the VD 'pulse 116
In response to this, an inhibit pulse 120 having a pulse width nT synchronized with the clock 126 is generated.

The pulse width t _n of the inhibition pulse 120 is, as shown in FIG.
It is set in correspondence with a period (prohibition period) that extends before and after the SG pulse and in which there is a possibility of exposure error when the strobe is emitted. The pulse width t _n can be determined by the above nT.
Further, the delay time t _d is set so that the position of the inhibition pulse 120 appears at a position that completely covers the SG pulse. The delay time t _d can be determined by the above time (mt ₀ + α).

Further, referring to FIGS. 5A and 5B, the configuration and operation of the pulse generator 5 are similar to those of the pulse generator 4. The difference is that the SR F / F 121 receives the image capture signal 124 and the synchronous counter 123 is (n + 1) -ary, so that the pulse generator 5 receives the image capture pulse. , A pulse 125 having a pulse width (n + 1) T synchronized with the clock 126 is generated. The clock 126 and the clock 127 may be the same or different. The cycle of the clock 126 is set to 10 μS or more required for the strobe trigger. The horizontal synchronizing signal HD itself may be used for both clocks 126 and 127.

Forbidden pulse 120 with pulse width nT and pulse width (n + 1)
The pulse 125 of T is combined by the pulse combiner 7 into a strobe light emission pulse 129. Gate 128 of pulse synthesizer 7
Expressing the logic of as a Boolean algebra, (129) ＝ (▲
▼) ・ (125)

Pulse width (n +) according to image acquisition pulse 124 from CPU
1) Various timings can be considered between the T pulse (125 and the SG pulse. In FIG. 7, taking n = 3 as an example, the pulse width (n +
The relationship between the pulse 125 of 1) and the stroboscopic light emission pulse 129 is shown.

As can be seen from FIG. 7, the stroboscopic light emission pulse 129 is
It is not output during the period of the pulse width nT of the inhibition pulse 120. The pulse width of the strobe light emission pulse 129 is T at the minimum. From this, as described above, the period T of the clock 126 is
Is set to about 10 μS or more, which is necessary for a trigger pulse for strobe emission. Since the prohibition pulse 120 and the pulse 125 are synchronized with the same clock 126, and the difference in pulse width is T, one strobe light emission pulse 129 with a pulse width of T or more is always one according to the pulse 125. Only happens. If the pulse 125 occurs before the prohibition pulse 120 (1) to (5), the flash emission pulse 129 is the pulse 125.
It occurs at the same timing as, and the strobe also fires at this timing. The same applies when pulse 125 occurs after inhibit pulse 120 (9). Only when (6) to (8) the pulse 125 is output at the timing overlapping with the prohibition pulse 120, the rise of the strobe light emission pulse 129 is delayed from the rise of the pulse 125 to the end of the period of the prohibition pulse 120. This delay is at most the pulse width nT of the inhibit pulse 120. It can be seen that the time nT is sufficiently about 1H, which is significantly improved as compared with the conventional maximum vertical synchronization period.

Returning to FIG. 1 again, the operation of the entire circuit of FIG. 1 will be described.

The composite signal 11 is converted into digital data 13 by the A / D converter 12. In addition, the sync separation unit 14
Then, the VD signal 15 and the HD signal 16 are separated from the composite signal 11. Address / write pulse generator 1
7 receives the VD signal 15 and the HD signal 16, and generates a memory write pulse 19 for each address 131 and one address of the memory for writing the data 13. Gate 112
Passes a write pulse to the memory 18 only when turned on by the memory write enable signal 111 from the memory write control unit 110. The memory write control unit 110 is V
Upon receiving D15, the inhibition pulse 120 and the strobe light emission pulse 129, the memory write enable signal 111 is generated during the period 24 'or 25' in accordance with the strobe light emission timing (see FIG. 2).

A state transition diagram of the operation of the memory write control unit 110 is shown in FIG.

State 0 is an initial state in which the memory write enable signal 111 is not output. In this state, strobe flash pulse 12
When 9 is received, the state is changed to 1 and the enable signal 111 is started to be output. In this state 1, the state branches to the state 2 or the state 4 depending on whether the inhibition pulse 120 or the VD pulse 15 is received next. This corresponds to the case where the light emission described above with reference to FIG. 2 occurs before or after the SG pulse.

When the inhibition pulse 120 is generated subsequent to the strobe light emission pulse 129, the state 1 shifts to the state 2 corresponding to the case (1) in FIG. In state 2, enable signal 11 continues.
1 is generated and the composite signal of one field is output. When the VD pulse 15 is received again in the state 2, the state 3 is entered. Also in the state 3, the enable signal 111 is continuously generated and the composite signal of the other field is output. When the next VD pulse 15 is received in the state 3, the state returns to the initial state 0 and the enable signal 111 is stopped.

In the state 1, when the VD pulse 15 is received instead of the inhibition pulse 120, it corresponds to the case (2) in FIG. 2, and in this case, the VD pulse 15 is received and the state moves to the state 4.
In the state 4, the enable signal 111 is continuously generated,
One composite signal is output. When the VD pulse 15 is further received, the state 5 is entered. The enable signal 111 is continuously output even in the period of the state 5, and the composite signal of the other field is output. Next, when the VD pulse 15 is received, the state returns to the initial state 0 and the enable signal 111 is stopped.

Although the preferred embodiments of the present invention have been described above, various modifications can be made without departing from the gist of the present invention. For example, in the above-described embodiment, the one in which the still image of the moving body is captured has been described, but the present invention can also be applied to the application of capturing the still image of the changing form of the fixed body. Similarly, although the CCD camera has been described in the above embodiments, the present invention can be applied to any camera using a solid-state imaging device whose emission timing is limited. Also, the light emission trigger pulse controls the light emission timing of the instantaneous light emitting means,
The light of the continuous light emitting means may be output in synchronization with the light emission trigger pulse by using a shielding means such as a shutter. Further, the counter used in the pulse generator can be configured by connecting a predetermined number of DF / Fs in series.

[Effects of the Invention] As described above, according to the light emission timing control method of the present invention, the light emission timing for exposure of a subject is skillfully controlled, so that the misalignment of the image can be suppressed to the minimum without the exposure error. You can Further, the light emission timing device of the present invention can be configured by a simple logic circuit, and can be easily added to the conventional device.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a single-screen capture device to which the present invention is applied, FIG. 2 is a timing diagram for explaining the relationship between a light emission point and an output video signal of a camera, and FIGS. 3A and 3B are respectively. 1 is a configuration diagram and an operation timing diagram of the delay pulse generator 3 of FIG. 1, FIGS. 4A and 4B are configuration diagrams and operation timing diagrams of the pulse generator 4 of FIG. 1, and 5A.
5 and FIG. 5B are configuration diagrams and operation timing diagrams of the pulse generator 5 of FIG. 1, FIG. 6 is a timing diagram for explaining the time relationship between the SG pulse and the light emission prohibition period, and FIG.
FIG. 8 is a timing chart for explaining the time relationship between the light emission trigger pulse 129 and the inhibition pulse 120. FIG. 8 is a state transition diagram of the operation of the memory writing control unit 110 in FIG. 1, and FIG. It is a schematic block diagram of a system. 3 ... Delayed pulse generator 4 ... Pulse generator with pulse width nT 5 ... Pulse generator with pulse width (n + 1) T 7 ... Pulse synthesizer

Claims (4)

[Claims] 1. An imaging device for capturing a still image of a subject,
Generates a light emission trigger pulse for instructing the light emission timing of the instantaneous light emission means in an image pickup system including a subject sensor that detects a subject entering an image capturing position asynchronously with the operation of the image pickup device and outputs a detection signal. In the light emission timing control method, the light emission is controlled when the detection signal is received as a capture signal indicating a capture timing of a still image of the imaging device, and the light emission trigger pulse is generated according to the capture signal. It is determined whether or not the light emission period by the trigger pulse overlaps with a predetermined light emission prohibition period for the imaging device. If the overlap does not occur, the light emission trigger pulse is generated in response to the generation of the capture signal. However, if the overlap occurs, after the capture signal is generated, the emission trigger pulse is issued after waiting for the emission inhibition period to end. A light emission timing control method characterized by the following. 2. The light emission timing control method according to claim 1, wherein the image pickup device has a CCD camera, and the light emission inhibition period is a charge transfer period of the CCD camera. 3. An imaging device for capturing a still image of a subject,
A light-emission trigger pulse for instructing the light-emission timing of the instantaneous light-emission means is emitted in an image-capturing system including a subject sensor that detects a subject entering an image capturing position asynchronously with the operation of the image-capturing device and outputs a detection signal. In the light emission timing control device, a capture signal output means for outputting a capture signal for instructing a capture timing of a still image of the image pickup device according to the detection signal, and a predetermined light emission inhibition for the image pickup device A first pulse generating means for generating a first pulse having a pulse width nT (n is an integer of 1 or more) synchronized with a reference clock having a period T and including at least a period; A second pulse generating means for generating a second pulse having a synchronized pulse width (n + 1) T and both outputs of the first and second pulse generating means, When the second pulse does not overlap with the first pulse, the second pulse is output as it is as the light emission trigger pulse, and when the second pulse overlaps with the first pulse, the second pulse is out of the first pulse. And a pulse synthesizing means for outputting the second pulse portion as the light emission trigger pulse. 4. The light emission timing control device according to claim 3, wherein the image pickup device has a CCD camera, and the light emission inhibition period is a charge transfer period of the CCD camera.