JPH0638425B2 - Bipolar transistor manufacturing method - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a bipolar transistor.

2. Description of the Related Art Trends in semiconductor devices include high-density integration, high speed, and high frequency. The maximum oscillation frequency is one of the basic performance factors when considering higher frequencies in bipolar transistors.
There is max. max is generally expressed by the following formula.

(Max) ² = _T / (8πRbCbc) (1) Here, _T is the maximum cutoff frequency, and the term involving the base-emitter capacitance Cbe is included, and _T decreases as Cbe increases. Rb is a base resistance, and Cbc is a base-collector capacitance. Therefore, reduction of Cbc is a requirement for higher frequency in bipolar transistors. In a collector-top type transistor in which the collector is on the upper side, Cbc is structurally minimum and max increases, but
On the contrary, Cbc increases due to the stray capacitance, and as a result, _T decreases.

Recently, as a high frequency device, a heterojunction bipolar transistor using a gallium arsenide system having an electron mobility faster than that of silicon has been attracting attention. In a heterojunction bipolar transistor, a semiconductor having a forbidden band width larger than that of a base semiconductor is used for an emitter, and a heterojunction is formed between the emitter and the base. As a result, carrier injection from the base side to the emitter side is reduced, and there is an advantage that a sufficient current amplification factor can be obtained even if the base is thin and has a high concentration for high frequency. The conventional collector top type heterojunction bipolar transistor is
Cbc is reduced by reducing the carriers in the emitter layer below the external base region extracted from the intrinsic base region immediately below the collector region by ion implantation to insulate the carriers and eliminating the junction capacitance in that region. Further, since the crystallinity of the external base region is deteriorated and the resistance is increased by the ion implantation, impurities are further ion-implanted into the external base region to increase carriers and reduce the resistance. An example thereof is shown in FIG.

An emitter contact region 2 containing a high concentration of an n-type impurity on a semiconductor substrate 1, an emitter made of a semiconductor having a forbidden band width larger than a region for forming a heterojunction, and containing an n-type impurity. A region 3, an intrinsic base region 4 containing a high concentration of p-type impurities, a collector region 5 containing an n-type impurity, and a collector contact region 6 containing a high concentration of n-type impurities are formed in order to reduce resistance. Of the p-type impurity ion-implanted into the outer base region 12, and the emitter layer immediately below the outer base region 12 has the insulating region 11 in which carriers are reduced by ion implantation.
Is formed, and an element isolation region 13 insulated by ion implantation is formed in the periphery. Further, an emitter electrode 7, a base electrode 8 and a collector electrode 9 which are in ohmic contact with each other are formed on the emitter contact region 2, the external base region 12 and the collector contact region 6. For example, IEEE Electron Device Letters vol.EDL-7,32 (1986).

However, in the above structure, since the emitter contact region for leading out the emitter electrode exists below the insulating region, the external base region and the emitter contact still remain immediately below the external base region. There is stray capacitance, such as a parallel plate capacitor with regions as electrodes. Further, when the p-type impurities ion-implanted into the external base region are diffused downward, there is a drawback that Cbc increases. Therefore, there is a structural limit to the reduction of Cbc, which is a problem in increasing the frequency of the transistor.

The present invention greatly improves the above problems, and eliminates the stray capacitance immediately below the external base region, thereby improving the Cbc.
It is an object of the present invention to provide a method for manufacturing a bipolar transistor that minimizes the above structure.

Means for Solving the Problems In order to solve the above problems, a method for manufacturing a bipolar transistor according to the present invention includes a semi-insulating substrate, an emitter contact layer serving as at least an emitter contact region from the substrate side, and an emitter serving as the emitter region. A layer, a base layer serving as an external base region and an intrinsic base region, and a collector layer serving as a collector region; a step of forming a first mask on the multilayer film; Using the mask described above to insulate the emitter contact layer and the periphery of the emitter layer by ion implantation from the surface of the multilayer film to form the emitter contact region and the emitter region, and to cover a part of the first mask. Step of forming the second mask, and removing the portion of the first mask not covered by the second mask And a step of insulating the periphery of the base layer by ion implantation from the surface of the multilayer film using the second mask to form an external base region and an intrinsic base region, and removing the second mask. Then, the method includes the step of using the rest of the first mask as a third mask, and the step of removing the periphery of the collector layer using the third mask to form a collector region.

In the method of manufacturing the bipolar transistor having the above-described structure, the third mask that determines the collector region is formed by self-alignment between the first mask that determines the emitter contact region and the emitter region and the second mask that determines the external base region. Therefore, the emitter contact region and the emitter region can be formed without effectively overlapping with the external base region, and a transistor can be formed in which Cbc, which greatly contributes to high frequency, is minimized structurally.

Embodiment One embodiment of the present invention will be described below with reference to FIG.

1 to 4 are configuration diagrams showing a method for manufacturing a gallium arsenide-based npn-type bipolar transistor according to an embodiment of the present invention. 1 (a), 2 (a), 3 (a), and 4 (a) are configuration diagrams when the transistor is viewed from above, FIG. 1 (b), and FIG. 2 (b). ), Fig. 3 (b) and Fig. 4 (b) are Fig. 1
Sectional view taken along the line AA 'in (a), FIG. 1 (c), and FIG.
(c), FIG. 3 (c) and FIG. 4 (c) are sectional views taken along the line BB 'in FIG. 1 (a). First, on a semi-insulating substrate 21 made of gallium arsenide, an emitter contact layer 22 serving as an emitter contact region containing a high concentration of an n-type impurity, an emitter layer 23 serving as an emitter region containing an n-type impurity,
The base layer 24 containing a high concentration of p-type impurities, which serves as an external base region and an intrinsic base region, the collector layer 25 containing an n-type impurity, which serves as a collector region, and the n-type impurity serving as a collector contact region, are highly doped. The collector contact layer 26 containing a high concentration is sequentially formed by film growth, and the first mask 41 is formed on the collector contact layer 26.
Are formed using a silicon oxide film or the like, and oxygen ions or the like are deeply implanted from the surface to the periphery of the emitter contact layer 22 and the emitter layer 23 to form the first insulating region 31. Then, in order to reduce the external base resistance, beryllium or the like is injected to form the external base layer 32 (FIGS. 1 (a), (b),
(c)). Next, a second mask 42 is formed using aluminum or the like so as to be elongated so as to straddle the first mask 41, and a portion of the first mask 41 not covered with the second mask 42 is dry-processed. Remove by etching. Then, oxygen ions are shallowly implanted from the surface to at least the periphery of the base layer 24 to form the second insulating region 33 (FIGS. 2A, 2B, and 2C). Furthermore, the second mask 4
2 is removed, and the remaining portion of the first mask 41 is used as the third mask 43. Using this third mask 43, the periphery of the collector layer 25 and the collector contact layer 26 is removed by wet etching (FIGS. 3 (a), (b),
(c)). As described above, the first mask 41 forms the emitter contact region and the emitter region from the emitter contact layer 22 and the emitter layer 23, and the second mask 42.
And the external base regions are independently formed from the external base layer 32, and the first mask 41 and the second mask 42 are formed.
The collector region is formed from the collector layer 26 by the third mask 43 formed by self-alignment. Finally,
After recovering the crystallinity of the ion-implanted part by heat treatment,
The emitter electrode 2 is formed on the emitter contact region 22.
7. A base electrode 28 is formed on the external base region 32 and a collector electrode 29 is formed on the collector contact region 26 to complete the npn-type bipolar transistor of this embodiment (FIGS. 4 (a) and 4 (b)). , (c)).

The emitter electrode and the base electrode in the above manufacturing method can be arranged in various combinations depending on the shapes of the first mask and the second mask. Further, since the first insulating region is formed at a position deeper than the base layer,
There is no particular need to perform ion implantation for reducing the external base resistance.

The above manufacturing method can also be used for a heterojunction bipolar transistor having more excellent high frequency characteristics. In this case, a semiconductor having a band gap larger than that of the semiconductor used for the base layer at the time of film growth may be used for the emitter layer. . Further, it can be applied to a pnp type transistor.

EFFECTS OF THE INVENTION As described above, the method for manufacturing a bipolar transistor having the configuration of the present invention uses self-alignment between the first mask that determines the emitter contact region and the emitter region and the second mask that determines the external base region. Since the third mask that determines the collector region is formed, the emitter contact region and the emitter region can be formed without effectively overlapping with each other, and Cbc, which greatly contributes to high frequency, can be minimized structurally. A transistor can be formed. In addition, since both the first insulating region and the second insulating region also serve as element isolation, it is possible to fabricate a transistor with a smaller number of steps as compared with the conventional manufacturing method.

[Brief description of drawings]

1 to 4 are configuration diagrams showing a method of manufacturing a transistor in one embodiment of the present invention, and FIG. 5 is a sectional view showing a configuration of a conventional transistor. 21 ... Semi-insulating substrate, 22 ... Emitter contact layer, 23 ... Emitter layer, 24 ... Base layer, 25 ...
Collector layer, 26 ... Collector contact layer, 27 ...
Emitter electrode, 28 ... Base electrode, 29 ... Collector electrode, 31 ... First insulating region, 32 ... External base layer,
33 ... second insulating region, 41 ... first mask, 42 ...
… Second mask, 43 …… Third mask.

Claims (3)

[Claims] 1. A semi-insulating substrate, an emitter contact layer serving as at least an emitter contact region from the substrate side, an emitter layer serving as an emitter region, a base layer serving as an external base region and an intrinsic base region, and a collector region. Forming a multilayer film with the collector layer, forming a first mask on the multilayer film, and using the first mask to surround the emitter contact layer and the emitter layer with the multilayer film. Insulating by ion implantation from the surface to form an emitter contact region and an emitter region, and a second mask covering a part of the first mask and a part other than the first mask following the part. Using the second mask, a step of forming a mask of, a step of removing a portion of the first mask that is not covered by the second mask, The step of insulating the periphery of the base layer by ion implantation from the surface of the multilayer film to form the external base region and the intrinsic base region, removing the second mask, and removing the remainder of the first mask by the third process. A method of manufacturing a bipolar transistor, comprising a step of forming a mask and a step of removing the periphery of the collector layer by using the third mask to form a collector region. 2. The method of manufacturing a bipolar transistor according to claim 1, further comprising the step of using a semiconductor having a larger forbidden band width than a semiconductor used for the base layer for the emitter layer. 3. The bipolar transistor according to claim 2, further comprising the step of implanting ions from the surface of the multilayer film to the periphery of the base layer using the first mask to reduce the resistance of the external base region. Manufacturing method.