JPH0638593B2 - Reset signal discrimination circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for discriminating between a reset signal generated when power is turned on in a communication device or the like and an abnormality alarm signal generated by a watchdog timer circuit when an abnormality occurs. is there.

(Prior Art) FIG. 2 is a circuit diagram showing a first conventional example of a reset signal discrimination circuit used in communication equipment and the like, and FIG. 3 is a waveform diagram for explaining the operation thereof. In FIGS. 2 and 3, 1 is an OR circuit, and a differential pulse generated by the time constant of the capacitor C and the resistor R when the power is turned on is input to the one input 1a as a reset signal RST via the buffer 2. The output signal of the watchdog timer circuit 3 including the oscillation circuit 3a, the frequency dividing circuit 3b and the counter 3c is input to the other input 1b of the OR circuit 1.
This operation will be described with reference to the waveform diagram of FIG. 3. The pulse signal A from the oscillation circuit 3a using a crystal oscillator or the like that oscillates at a predetermined frequency is divided into 1 / n by the frequency dividing circuit 3b, and the pulse signal B is obtained. The pulse signal B is output by the counter C after counting by a predetermined number, and the abnormality alarm signal C is output.
Is entered. Output signal O from output 1c of OR circuit 1
S1, that is, the reset signal RST or the abnormality alarm signal C is input to the control unit 4, and the control unit 4 monitors the reset signal RST and the abnormality alarm signal C.

As is well known, the watchdog timer circuit 3 is provided to notify that an abnormality has occurred in the device. In the normal state, the watchdog timer circuit 3 is output from the control unit 4 at a predetermined cycle after the power is turned on. The output of the abnormality alarm signal C is suppressed by inputting the timer reset signal TRS to the counter 3c, an abnormality occurs in the device, and there is no input even if the timer reset signal TRS is input to the counter 3c for a predetermined time. As shown in FIG. 3, the abnormality is notified by outputting the abnormality alarm signal C to the OR circuit 1.

FIG. 4 is a circuit diagram showing a second conventional example. In this example, a random access memory (hereinafter, simply referred to as R
AM) 5 is added, and when the reset signal RST is input to the control unit 4 via the OR circuit 1 when the power is turned on, the data related to the reset signal RST is written in the RAM 5 to reset the reset signal RST and the abnormal alarm signal C. Was being determined.

(Problems to be Solved by the Invention) However, according to the first example, the reset signal RST when the power is turned on and the abnormality alarm signal C output from the watchdog timer circuit 3 when an abnormality occurs in the device Since and are input to the control unit 4 via the OR circuit 1, there is a problem that the control unit 4 cannot determine whether the reset signal RST or the abnormality alarm signal C is input. Further, according to the second example, it is possible to distinguish between the reset signal RTS and the abnormality warning signal C,
There has been a problem that the runaway on the software occurs and the contents of the RAM 5 are rewritten, and as a result it becomes impossible to determine.

In view of the above problems, an object of the present invention is to provide a reset signal discriminating circuit capable of accurately discriminating a reset signal and an abnormal alarm signal without being affected by software runaway or the like.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides an abnormality when an abnormality occurs in a reset signal generator and a device that generate a reset signal when power is turned on. A watchdog timer circuit that generates an alarm signal, a guard circuit that is activated by the reset signal and remains in a stopped state until the next reset signal is input once, and a reset state by the reset signal that outputs the guard circuit Inputs the reset signal and the abnormal alarm signal that are in the set state in synchronization with the input signal. If the state holding circuit is in the reset state, the input signal is determined as the reset signal. A control unit for discriminating as an alarm signal and for controlling so that the guard circuit produces an output after discriminating a reset signal. Equipped with.

(Operation) According to the present invention, when the power is turned on, a reset signal is generated and input to the control unit, and the reset signal causes the guard circuit to be activated and the state holding circuit to be reset. On the other hand, the control unit monitors the state holding circuit and can recognize that the input signal is the reset signal by recognizing that the state holding circuit is in the reset state. After the reset signal is discriminated, the state holding circuit is set by the output of the guard circuit, and this state is held until the next reset signal is generated. Therefore, the control unit can determine the input signal in the set state as the abnormality alarm signal from the watchdog timer circuit.

(Embodiment) FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which the same configuration as that of the conventional one is denoted by the same reference numeral. That is, 1
Is an OR circuit, 2 is a buffer, 3 is a watchdog timer circuit composed of an oscillation circuit 3a, a frequency dividing circuit 3b, and a counter 3c. Further, 10 is a flip-flop (hereinafter, simply FF), 11 is a three-state buffer, 12
Is a bidirectional buffer, 13 is a guard circuit, and 14 is a control unit.

FF10 is a reset signal RST generated when the power is turned on.
Is input to the reset terminal R to enter the reset state, and the output signal OS2 from the output terminal Q is set to the low level "0".
Is output to the three-state buffer circuit 11. In addition, the output signal of the bidirectional buffer circuit 12 is input to the input terminal D at a high level "1" and the output signal of the guard circuit 13 is input to the clock terminal CLK to set the output signal OS2 to a high level "1". Is output from the output terminal Q to the three-state buffer 11.

The three-state buffer 11 has an FF at the input terminal 11a.
10 by inputting the output signal OS2 and the control signal from the control unit 14 to the control terminal 11b.
The output signal OS3 is output to the bidirectional buffer 12 from c.

The bidirectional buffer 12 inputs the output signal OS3 of the three-state buffer 11 to the input terminal 12a, and the control unit 14
By inputting a control signal from the output control terminal 12b to the control unit 14, the bidirectional output terminal 12c outputs the input / output signal IOS to the control unit 14, and the output terminal 12d outputs the output signal OS4 to the input terminal D of the FF10. .

The guard circuit 13 is activated by inputting the reset signal RST generated when the power is turned on to the set terminal 13a, and when the control signal from the control unit 14 is input to the input terminal 13b, the clock signal clk becomes higher than the output terminal 13c. The level "1" is output to the clock terminal CLK of the FF 10, and after the output, the state is stopped until the next reset signal RST is input to the set terminal 13a.

The control unit 14 outputs the output signal OS1 of the OR circuit 1 to the input terminal 14a, that is, the reset signal RS generated when the power is turned on.
When an abnormality occurs in T or the device, the abnormality alarm signal C output from the counter 3c of the watchdog timer circuit 3 is input, and the reset signal RST and the abnormality alarm signal C are discriminated. If the device is in a normal state after the power is turned on from the output terminal 14b, the timer reset signal TRS is output to the counter 3c at predetermined intervals to suppress the output of the abnormality alarm signal C. Further, the output terminal 14c outputs the control signal CTL1 to the control terminal 11b of the three-state buffer 11, the output terminal 14d outputs the control signal CTL2 to the output control terminal 12b of the bidirectional buffer 12, and the output terminal 14c.
By outputting the control signal CTL 3 from the e to the input terminal 13b of the guard circuit 13 at a predetermined interval, the output of each circuit is controlled and the input / output signal IOS from the bidirectional terminal 12c of the bidirectional buffer 12 is input. It is input to the output terminal 14f, and the output level of the bidirectional terminal 12c is input / output terminal IO.
Controlled by S.

Next, the operation of the above configuration will be described with reference to the waveform chart of FIG. In the figure, i indicates the input mode, θ indicates the output mode, and Z indicates the output high impedance state.

First, when the power supply of the device is turned on, the differential pulse generated by the time constant of the capacitor C and the resistor R is input to the input terminal 1a of the OR circuit 1 as the reset signal RST via the buffer 2 and then from the output terminal 1c. Main input signal OS1 is input to the input terminal 14a of the control unit 14, and the reset signal RST is input to the reset terminal R of the FF 10 and the set terminal 13a of the guard circuit 13. As a result, the FF 10 is reset and outputs the output signal OS2 from the output terminal Q as a low level "0". Also,
When the output signal OS1 is input from the input terminal 14a, the control unit 14 outputs the control signal CTL1 from the output terminal 14c to the control terminal 11b of the three-state buffer 11 and the control signal CTL2 from the output terminal 14d. 12 is output to the output control terminal 12b to output the output signal OS of the FF10 of low level "0".
2 as the input / output signal IOS shown in FIG.
4f and recognizes that the signal input to the input terminal 14a is the reset signal RST by this input.

Next, the control unit 14 controls the level of the bidirectional output terminal 12c of the bidirectional buffer 12 to the high level "1" by the input / output signal IOS. As a result, the output signal OS4 of high level "1" is input from the output terminal 12d to the input terminal D of the FF10. Further, the control section 14 outputs the control signal CTL2 to the output control terminal 12b of the bidirectional buffer 12 at a higher level "1" than the output terminal 14d, and at the same time, outputs the output terminal 14
By outputting the control signal CTL3 having a level "1" higher than e to the guard circuit 13b, the clock signal clk is output from the output terminal 13c of the guard circuit 13 to the clock terminal CLK of the FF10, and the FF10 enters the set state and the output signal OS2 Is output from the output terminal Q as a high level "1". Further, the guard circuit 13 is in a stopped state after outputting the clock signal clk, and is held in the stopped state until the next reset signal RST is input to the set terminal 13a. Therefore, the output signal OS2 of the FF10 is also the next reset signal RS.
High level "1" until T is input to reset terminal R
Will be fixed at.

Further, the control unit 14 outputs the timer reset signal TRS from the output terminal 14b to the counter 3c of the watchdog timer circuit 3 at a predetermined interval after the power is turned on, and the abnormality warning signal C is output.
The occurrence of is suppressed. Here, when an abnormality occurs in the device and the timer reset signal TRS is not output from the control unit 14, the abnormality alarm signal C is input from the counter 3c to the input terminal 1b of the OR circuit 1 and output from the output terminal 1c of the OR circuit 1. The signal OS1 is input to the input terminal 14a of the control unit 14. In response to this input, the control unit 14 outputs the control signal CTL1 from the output terminal 14c to the control terminal 11b of the three-state buffer 11 and the output control terminal 12b of the bidirectional buffer 12 from the output terminal 14d. Output signal OS of FF10 that is "1"
2 is input as the input / output signal IOS via the input / output terminal 14f. By this input, it is recognized that the signal input to the input terminal 14a is the abnormality alarm signal C.

According to this embodiment, the set state of the FF10 can be fixed until the next reset signal RST is input by activating the guard circuit 13 only when the power is turned on, and the output signal OS2 indicating the state of the FF10 is output. By determining whether it is a high level or a low level, the control unit 14 can accurately determine whether the signal input to the input terminal 14a is a reset signal or an abnormality alarm signal.

(Effects of the Invention) Since the present invention is configured as described above, it has the effects described below.

Since the circuit for discriminating between the reset signal and the abnormality alarm signal is composed of hardware, even if a software runaway occurs, the discrimination processing is not affected at all, and the discrimination can be made accurately.

Further, since the guard circuit, the logic circuit, the bidirectional buffer circuit, and the three-state buffer circuit constitute the state holding circuit that provides the information for making the determination, the number of parts and the manufacturing process are reduced, and a small and inexpensive device is provided. Can be provided.

In addition, when the reset signal is input, all the internal memory of the control unit is cleared, but when the abnormal alarm signal is input, a part of the internal memory is maintained. It is also possible to do.

Further, since the output signal OS2 serving as a reference for determination is automatically set and either the reset signal RST or the abnormality alarm signal C is selected and output using the reference value, the output serving as a reference for determination in advance. It is not necessary to set the signal OS2.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram showing a conventional example of FIG. 3, FIG. 3 is a waveform diagram for explaining the operation of FIG. 2, and FIG. 4 is a circuit diagram showing a second conventional example.
FIG. 5 is a waveform diagram for explaining the operation of FIG. In the figure, 1 ... OR circuit, 2 ... buffer, 3 ... watchdog timer circuit, 3a ... oscillation circuit, 3b ... frequency dividing circuit, 3c ... counter, 10 ... flip-flop (FF), 11 …… Three-state buffer, 12 ……
Bidirectional buffer, 13 ... Guard circuit, 14 ... Control section.

Claims (1)

[Claims] 1. A reset signal generator that generates a reset signal when power is turned on, a watchdog timer circuit that generates an abnormality alarm signal to notify the abnormality when an abnormality occurs in the device, and the reset signal. In a reset signal determination circuit configured by inputting the abnormality alarm signal, determining the discrimination of the input signal, and outputting a control signal, the reset signal determination circuit is activated by the reset signal and outputs once, A guard circuit that is in a stopped state until the reset signal is input, and a state holding circuit that holds either the reset state or the set state are provided.The state holding circuit is reset by inputting the reset signal to the reset terminal. It becomes a set state by outputting a low level signal and inputting a signal to the data terminal. An input D flip-flop circuit, a three-state buffer circuit which inputs the low or high level signal and the control signal, and outputs a signal according to the state of the input signal, and an output signal from the three-state buffer circuit. And a bidirectional buffer circuit which inputs the control signal and outputs a signal depending on the state of the input signal. The control section resets the input signal when the state of the state holding circuit is the reset state. The reset signal determining circuit is characterized by determining that the input signal is an abnormality alarm signal when the state holding circuit is in the set state.