JPH063876B2 - Programmable logic array - Google Patents

Description

The present invention relates to a semiconductor integrated circuit.

[Conventional technology]

Conventionally, the structure of a programmable logic array (hereinafter abbreviated as PLA) used in a semiconductor integrated circuit is, as shown in FIG. 4, inputs and outputs (45, 47) and (47, 49) of AND matrix 46 and OR matrix 48, respectively. ) Was orthogonal.

[Problems to be solved by the invention]

The conventional PLA described above changes its shape in a two-dimensional direction when the scale of the circuit changes depending on the number of inputs c, the number of product terms d, the number of outputs e, and the like. As a result, when laying out a plurality of PLAs on a chip, there are drawbacks that gaps are likely to occur, it is difficult to increase the density, and the wiring of input / output signal lines and power supply lines is complicated.

[Means for solving problems]

According to the present invention, a first M comprising a plurality of linearly arranged MOSFETs having commonly connected gate electrodes.
A unit row is formed by sequentially arranging a second MOSFET row and a second load element having a structure similar to that of the OSFET row, the first load element, and the first MOSFET row in the vertical direction as a unit row. PL characterized by arranging a plurality of columns in one direction
A is obtained.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a unit column in one embodiment of the present invention, (a) is a plan view and (b) is an equivalent circuit diagram. In the figure, 1 is the first M
2 shows an OSFET column, 2 is a common gate electrode made of polysilicon, 3 and 4 are contact holes, 5 is a common source electrode made of a diffusion layer, and 6 is one M which constitutes a MOSFET column.
The drain electrode of OSFET is shown. Reference numeral 7 is a first load element, 8 is a common source electrode, 9 is a drain electrode of MOSFET, and 10 is a common gate electrode made of polysilicon. Reference numeral 11 denotes a second MOSFET row, 12 is a common gate electrode made of polysilicon, 13 is a common source electrode, and 14 is one MOSFE forming the MOSFET row.
The drain electrode of T is shown. Reference numeral 15 is a second load element, 16 is a common source electrode, 17 is a drain electrode of MOSFET, and 18 is a common gate electrode made of polysilicon. The plan view of FIG. 1 (a) shows the structure of the integrated circuit up to the MOSFET part, and does not include the wiring part made of metal. However, contact holes for connecting the diffusion layer to the metal and the polysilicon to the metal are drawn in all possible locations. PLA using the unit sequence shown here
FIG. 2 shows an example in which the above is constructed. FIG. 2 shows one set of PLA circuits constructed by arranging three sets of unit columns shown in FIG. 1 in the horizontal direction and wiring between the elements. In FIG. 2, 19 is an AND matrix part of PLA, 20 is a first load element, 21 is an OR matrix, and 22 is a second load element. 23 is an input polysilicon line, 24 is an AND
NMOSFETs that form a logic circuit in a matrix, 2
Reference numeral 5 is a product term line made of aluminum of the first layer for connecting the drain electrodes of the respective NMOSFETs, 26 is a through hole for connecting aluminum of the first layer and aluminum of the second layer, and 27 is a product term line made of aluminum of the second layer. , 28 is a power supply terminal, 29 is a PMO
A grounded load element of SFET, 30 is a product term line 27 to an input polysilicon line 31 of an OR matrix
Connection point, 32 is an NMOSFET forming a logic circuit in an OR matrix, 33 is an output line made of aluminum for the first layer connecting the drain electrodes of the NMOSFETs, 34 is an output line 35 made of aluminum for the second layer and the first layer A through hole for connecting to aluminum is shown. It should be noted that FIG. 2 is intended to show the electrical connection relationship, and the MOSFETs, some contacts, and through holes that are distant from the signal path are omitted.

FIG. 3 is a diagram showing an arrangement example of a plurality of PLA, 36 is an input line 37 to 39 is an AND matrix, 40 is a product term line,
41 to 43 are OR matrices, and 44 is an output line. In the figure, three sets of PLAs are arranged side by side, these being the first
It is realized by applying two layers of aluminum wiring on the unit row shown in the figure arranged in the horizontal direction.

In the above example, the AND and OR matrix parts are NMO.
Although the pseudo-NMOS circuit in which S and the load element are PMOS has been described, it is possible to configure the entire circuit by only the NMOS or the PMOS, and a dynamic type circuit configuration in which a clock signal is connected to the gate of the load element. It is also possible to do so.

〔The invention's effect〕

As described above, according to the present invention, a PLA having a uniform height can be realized by constructing a PLA by arranging unit rows in which MOSFET rows are arranged in the vertical direction in the horizontal direction.
When designing an LSI using A, the layout is simplified and the design period is shortened. Also, as shown in FIG. 3, the problem of the gap between PLAs is such that the number of inputs f, i,
1, even if the number of product term lines g, j, m and the number of outputs h, k, n are different, they can be arranged with almost no gap, and the area occupied on the integrated circuit chip can be saved. Furthermore, the positions of the power lines and clock lines are standardized, so each PLA
Wiring between them becomes easy.

Further, in developing an integrated circuit chip, it is also possible to use a master slice method in which unit columns according to the present invention are arranged in advance and wiring is carried out with aluminum to a necessary portion according to a circuit function, The effect of shortening the development period can also be expected.

[Brief description of drawings]

FIG. 1 is a diagram showing a unit array of an embodiment of the present invention, (a) is a plan view, and (b) is an equivalent circuit diagram. FIG. 2 is a PLA circuit diagram of an embodiment of the present invention, FIG. 3 is an embodiment in which a plurality of PLAs are arranged, and FIG. 4 is a diagram showing a conventional PLA. 1 ... First MOSFET row, 2, 10, 12, 18 ...
… Common gate electrode made of polysilicon, 5, 13 …… M
Common source electrode of OSFET array, 6, 14 ... MOSF
ET column drain electrode, 7 ... first load element, 8, 1
6 ... Common source electrode of load element, 9, 17 ... Load element drain electrode, 11 ... Second MOSFET array, 15
…… Second load element, 19 …… AND matrix, 2
0, 22 ... Load element, 21 ... OR matrix, 36
...... Input line, 37-39 …… AND matrix, 40 ・ ・ ・
... product term line, 41-43 ... OR matrix, 44 ... output line, 45 ... input line, 46 ... AND matrix, 47
... product term line, 48 ... OR matrix, 49 ... output line.

Claims (2)

[Claims] 1. A first MOS comprising a plurality of linearly arranged MOSFETs having commonly connected gate electrodes.
The FET row, the first load element, the second MOSFET row having the same structure as the first MOSFET row, and the second load element are arranged in order in the vertical direction as a unit row, A plurality of unit columns are arranged side by side in the lateral direction, an AND matrix is formed by the first MOSFET rows in the plurality of rows, an OR matrix is formed by the second MOSFET rows in the plurality of rows, and the AND matrix is formed. The first load element is connected to the product term line of
A programmable logic array, wherein the second load element is connected to an output line of the matrix. 2. A programmable logic array according to claim 1, wherein said MOSFET array has two polysilicon lines as respective gate electrodes and commonly connected source electrodes.