JPH063888B2 - AIS detection circuit - Google Patents

Description

The present invention relates to a bipolar communication device, and more particularly to an AIS detection circuit having a guard against a 1-bit error.

[Conventional technology]

An AIS (Alarm Indication Signal) is an all "1" data signal sent to a low-order group device when a high-order group device fails in bipolar transmission.
The low-order group device has a function of distinguishing it from a normal data signal, recognizes a fault of the high-order group device when AIS is detected, and outputs alarms of all the low-order group devices which may be caused thereby. With the function to prohibit.

A conventional AIS detection circuit is shown in FIG. In the figure,
1 is a B / U conversion circuit for converting bipolar data a into unipolar data b and c, 2 is a logical OR of + (plus) side unipolar data b and-(minus) side unipolar data c, and outputs an OR signal d The OR circuit 3, the activity detection circuit 3 which detects the presence or absence of the activity from the OR signal d and outputs the signal e indicating the presence or absence of the activity, 4 the clock extraction circuit which extracts the clock f from the OR signal d, and 5 the OR signal d A retiming circuit for retiming with the clock f and outputting the signal g, 6 is a retiming circuit for retiming the signal g and outputting the signal h, and 7 is signals g and h
An OR circuit that takes a logical OR with and output an OR signal i, 8
Is an activity detection circuit that detects the presence or absence of activity from the OR signal i and outputs a signal j that indicates the presence or absence, and 9 is a NAND circuit that takes the NAND of the signals e and j and outputs the AIS detection signal k.

The operation for detecting the AIS from the bipolar data a in the conventional circuit thus configured will be described with reference to.

A / B bipolar data a is converted to R by the B / U conversion circuit 1.
It is converted to a Z signal and both the + and-side signals b and c (the fourth
Signal d (Fig. 4 (d)) obtained by logical OR of Fig. (B) and (c))
(See Fig. 4 (e)). The activity detection circuit 3 is composed of, for example, a monostable multivibrator, the cycle of the signal d which is a pulse signal is shorter than the cycle of the monostable multivibrator, and the activity detection is performed even if one pulse is missing in the signal d. The output signal e of the circuit 3 is maintained at the "H" level (see FIG. 4 (e)). The “H” level of the signal e means that there is activity.

There should be no activity when the OR signal d is converted to the NRZ signal. This is because the OR signal d is re-timed by the clock f (see FIG. 4 (a)) to obtain the signal g (see FIG. 4).
(see (f)), retiming the signal g again to output a signal h (see FIG. 4 (g)), and an OR signal i (FIG. 4 (h) obtained by ORing the signals g and h). )) Is input to the activity detection circuit 8 to determine the signal j (see FIG. 4 (i)). The signal j in this case is maintained at the "H" level, which means that there is no activity.

When the AIS data has an error of only one bit as shown by the broken line pulse in FIGS. 4 (b) and (d), the error does not cause the signals e and j to be at the “L” level, that is, the AIS.
Not be affected by. This is shown in Fig. 4 (b),
Even if one pulse is missing as indicated by the broken line in (d), A
This means that the IS detection operation is not affected, and as can be seen from the time chart of FIG. 4, the signals e and j are not affected by the 1-bit error.

In such an operation, the signal k becomes "L" level, which means that the input data a is not normal data but A
Indicates that it is IS data.

[Problems to be Solved by the Invention]

In the conventional AIS detection circuit described above, AIS is 1
Since it has a guard circuit for making a bit error, and sees whether it is AIS or not by logical OR in the OR circuit 7 after shifting the data d by 1 bit, a signal in which "1" and "0" alternate Even if "1010 ..."
There was a drawback that it was recognized as S.

This is shown in FIG. In FIG. 5, the same signals as those in FIG. 4 are given the same symbols. For example, the + side unipolar data b is shown in FIG. 5 (b), and the-side unipolar data c is shown in FIG. 5 (c).

[Means for Solving the Problems]

In order to eliminate such a defect, the AIS detection circuit according to the present invention sequentially judges two consecutive bits of the input signal, so that when the input signal is all 1, the all 1 is also obtained.
The AIS judging means for judging the AIS even when only one bit of the input signal is an error, and 1 from the continuous bit string of the input signal.
When a signal 010 ... Is detected, a non-AIS judging means for suppressing the AIS detection output from the AIS judging means is provided.

[Action]

In the AIS detection circuit according to the present invention, when a signal of "1010 ..." Alternating "1" and "0" is input, the signal is detected and AIS detection is prohibited.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the AIS detection circuit according to the present invention. In the figure, 10 is an exclusive OR circuit that takes an exclusive OR of the signals g and h, 11 is a "1" fixed detection circuit that outputs "H" level data when "1" fixed data is input, Reference numeral 12 is a "1" fixed detection circuit that outputs "L" level data when "1" fixed data is input. The retiming circuits 5 and 6, the OR circuit 7, and the "1" fixed detection circuit 11 are AIS. The retiming circuits 5 and 6, the exclusive OR circuit 10 and the "1" fixed detection circuit 12 constitute non-AIS determination means. In FIG. 1, the same or corresponding parts as those in FIG. 3 are designated by the same reference numerals.

The data a input in bipolar is converted into unipolar data b and c by the B / U conversion circuit 1 (see FIGS. 2 (b) and 2 (c)), and the logical OR is immediately taken by the OR circuit 2 and the OR circuit. 2 outputs an ORed signal d (see FIG. 2 (d)). This signal d is an RZ signal at this stage. The clock f (see FIG. 2 (a)) extracted from the signal d is retimed to obtain the signal g (see FIG. 2 (e)), and the signal g is retimed again to obtain the signal h (second). Figure (f)) is obtained. The signals g and h are input to the OR circuit 7 and the exclusive OR circuit 10, respectively, and the OR signal and the exclusive OR signal are taken, and the signal i
(See FIG. 2 (g)) and signal l (see FIG. 2 (h)) are obtained.

Next, the "1" fixation of the signal i is detected by the "1" fixation detection circuit 11 to obtain the signal m (see FIG. 2 (i)). As shown in FIG. 2 (i), the level of the signal m is fixed at "1" and becomes "H". As the element at which the level of the signal m becomes “H”,
True "1", 1-bit error "1",
Three types of "1010 ..." can be considered. In order to exclude the term from these three types, the "1" fixed detection circuit 12 detects the "1" fixed of the signal l. As shown in FIG. 2 (j), the level of the output signal n of the circuit 12 is fixed at "1" and is "L", and only when "1010 ..." is the element for the signal n to be at "L" level. is there. Therefore, the signal m
Is the AIS detection signal k (see FIG. 2 (k)) desired except for the condition that the signal n becomes "L" level from the condition that becomes "H" level.

That is, the AIS detection signal k of the circuit shown in FIG. 1 is the all "1" or 1 when the input bipolar data a is true.
When the bit error is all "1", it becomes "L" level, indicating that the input data is AIS data. However, when the input bipolar data a is "1010 ...", the signal k is "H". This indicates that the above input data is not AIS data.

The broken line pulse in FIG. 2 (b) indicates that there is 1-bit error data.

〔The invention's effect〕

As described above, the present invention is provided with the non-AIS determination means that does not determine "1010 ..." Data as AIS.
Since the S detection can be prohibited, the "1010" is not impaired without impairing the AIS detection function when the original AIS data or AIS data with 1-bit error is input.
... "This has the effect of eliminating the problem of erroneously recognizing data as AIS.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an AIS detection circuit according to the present invention, FIG. 2 is a time chart for explaining the operation of the circuit of FIG. 1, and FIG. 3 is a circuit showing a conventional AIS detection circuit. FIG. 4, FIG. 5 and FIG. 5 are time charts for explaining the operation of the circuit of FIG. 1 ... B / U conversion circuit, 2, 7 ... OR circuit, 4 ... Clock extraction circuit, 5, 6 ... Retiming circuit, 9 ... NAND circuit, 10 ... Exclusive OR circuit, 11, 12 ... "1" fixed detection circuit.

Claims (1)

[Claims] 1. A detection circuit of an AIS which is sent for the purpose of prohibiting a failure of a low-order group device which is always caused when a failure of the high-order group device occurs by transmitting failure information of the high-order group device to a low-order group device. , AIS determining means for determining as AIS even when the input signal is all 1's, and when only 1 bit of the all 1 signal is error by sequentially determining 2 consecutive bits of the input signal, and the input signal When a 1010 signal is detected from a continuous bit string of AIS, the AIS from the AIS judging means
An AIS detection circuit comprising: a non-AIS determination means for suppressing a detection output.