JPH063899B2 - Clock synchronization circuit - Google Patents

Description

The present invention relates to a clock synchronization circuit, and more particularly to a clock synchronization circuit during demodulation of digital data transmission.

[Conventional technology]

Although a tank circuit or the like is exclusively used for clock synchronization of digital data transmission, the same clock as that of the transmission side is required for reproducing the transmission data on the reception side at the time of synchronization. Therefore, it is common to transmit reference data for clock synchronization for a certain period of time before transmitting data so that the same clock is reproduced on the receiving side.

[Problems to be solved by the invention]

In the above-described conventional clock synchronization, the reference data for clock synchronization is transmitted for a fixed time, and the data is transmitted only after the clock is prepared on the receiving side.
The time for the transmitting side to send the reference data for clock synchronization is a dead time from the viewpoint of information transmission. Therefore, the shorter the time, the better. That is, conventionally, there is a problem that useless reference data is transmitted.

An object of the present invention is to provide a clock synchronization circuit that enables clock synchronization without receiving reference data from the transmitting side, which is also called useless information.

[Means for solving problems]

The clock synchronization circuit of the present invention includes an interpolation filter that restores the signal waveform by inputting a discrete signal obtained by sampling the transmission waveform of data transmitted at the interval T _b at the interval T _s , and extracting from the restored signal waveform. A clock control circuit for outputting demodulated data by punching out the restored signal waveform with the clock signal, and N sampled at the interval T _s.
A storage circuit that stores the discrete signals and outputs the stored values in reverse order; and a switch that changes the connection of the input of the interpolation filter from the input of the discrete signal to the output of the storage circuit, A first step of connecting a switch to the input of the discrete signal, inputting the N discrete signals to the interpolation filter, clock synchronization, and at the same time inputting the N discrete signals to the storage circuit. And a second step of connecting the switch to the output of the storage circuit, inputting N stored discrete signals to the interpolation filter in reverse order, and outputting a clock-synchronized demodulated signal. .

[Action]

FIG. 1 is a block diagram for explaining the configuration of the present invention. Initially, the switch 4 is tilted to the 41 side, and the terminal 100
When a sample value of T _s interval is input, the input sample value is stored in the memory circuit 3. The sampled value is input to the successive interpolation filter 1, and the signal waveform before sampling is reproduced at the output terminal 300 thereof. This signal waveform is added to the clock control circuit 2 so that the clock is gradually synchronized. This output is output from the terminal 400,
The transmitted data cannot be faithfully reproduced because they are initially out of phase. After the clock control circuit 2 inputs N sample values sufficient to complete clock synchronization, the switch 4 is switched to the terminal 42 side,
The interpolation filter 1 receives the values output from the storage circuit 3 in the reverse order of the time when they are stored. At this time, sample values whose time series are reversed are input to the interpolation filter 1. In order to maintain the clock synchronization state before switching the switch at the reverse time, the interpolation filter is also operated at the reverse time. As a result, the clock is synchronized even after the reverse time. Also,
After synchronization, clock control is performed in the same manner as the synchronization control for forward time. However, the phase error amount when the time is reversed is that the relationship between the lead and the delay obtained in the forward time (first step) is inverted, and the lead phase error until now becomes the lag phase error and the lag phase. The error advances and becomes a phase error. Therefore, when the sample value series in the interpolation filter 1 becomes an inverse series of the value immediately before the switch 4, the phase may be shifted so that it becomes the same value as the value obtained immediately before. The control circuit 5 outputs an instruction for changing the interpolation filter 1 into an inverse time interpolation filter and an instruction for alignment.

As described above, the state before the switch 4 is switched is referred to as a first step, and the state after the switch 4 is switched is referred to as a second step. First
Complete clock synchronization during the steps. At this time, the signal output from the interpolation filter is a signal in the process of synchronization, and a signal which is clock-synchronized with all data from the beginning cannot be obtained. Therefore, even after the switching to the second step, by interpolating the data again while maintaining the synchronization state, the clock-synchronized data can be obtained from the beginning to the end of the data.

〔Example〕

Next, the present invention will be described in detail with reference to FIGS.

FIG. 2 is a block diagram showing an embodiment of the clock synchronizing circuit of the present invention. As a configuration of the interpolation filter 1 used in this embodiment, there is an interpolation filter described in Japanese Patent Application No. 60-002388.

FIG. 3 is a block diagram showing an example of the interpolation filter in FIG. 2, and FIG. 4 is a block diagram showing an example of the basic interpolation filter in FIG.

In FIG. 3, the interpolation filter 1 is an input circuit 60 for distributing the input multilevel digital sample value of the terminal 200 to each value.
And the basic interpolation filters 50 to 57 shown in FIG. 4, and a synthesizing circuit 70 for synthesizing the outputs of the basic interpolation filters 50 to 57. The clock control circuit 2 may be of various types such as the clock phase control circuit described in Japanese Patent Application No. 58-057529.

The interpolation filter 1 has a binary counter 86 as shown in FIG.
Is being counted up and interpolated. This filter can be used as a reverse time interpolation filter by adding a signal to the terminal 600, down-counting, and reversing the relationship between the shift register 87 and the ROM 88 by the selection circuit 84. The control circuit 5 starts with a pulse synchronized with the output obtained from the clock control circuit 2 after the pulse generator 61 for shifting each shift register 87 of the basic interpolation filter and the switch 4 are switched to the 42 side. , After counting the interval T _b / 2,
It is composed of a counter 62 and a clock 63 for switching the binary counter 86 of the interpolation filter from counting up to counting down.

Next, FIG. 5 is a timing chart showing the operation in FIG. In FIG. 5, the symbol S _m indicates the m-th output data, and the symbol a _N indicates the N-th sample value. Also, the value of the shift register in the interpolation filter (here, 6 taps) and the value of the counter count of the interpolation filter are shown. In the figure, the sample value a _N is input, the output data S _m is output, and then switching is performed. As shown in the figure, since there are two shift register inputs by up / down of the binary counter, the pulse generator 61 (shown in FIG. 2) shifts four more to replace all six taps. . Also, the binary counter 86 (shown in FIG. 4) has an interval T _b.
After / 2, the up counter is switched to the down counter. By this operation, output data S _m , S _m−1 , ... And clock-synchronized data are sequentially obtained from the next output.

〔The invention's effect〕

As described above, the clock synchronization circuit of the present invention has an effect of enabling clock synchronization even if the reference data for clock synchronization added before the normal data is removed.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining the configuration of the present invention, FIG. 2 is a block diagram showing an embodiment of a clock synchronization circuit of the present invention, and FIG. 3 shows an example of an interpolation filter in FIG. A block diagram, FIG. 4 is a block diagram showing an example of the basic interpolation filter in FIG. 3, and FIG. 5 is a timing chart showing the operation at the time of switching in FIG. 1 ... Interpolation filter, 2 ... Clock control circuit, 3 ... Storage circuit, 4 ... Switch, 5 ... Control circuit, 50 ... 57 ... Basic interpolation filter, 60 ... Input circuit, 61 ... Pulse generator,
62 ... Counter, 63 ... Clock, 70 ... Synthesis circuit, 8
4 ... Selection circuit, 86 ... Binary counter, 87 ... Shift register, 88 ... ROM.

Claims (1)

[Claims] 1. An interpolation filter for restoring a signal waveform by inputting a discrete signal obtained by sampling a signal waveform of data transmitted at an interval T _b at an interval T _s , and a clock signal extracted from the restored signal waveform. In a clock synchronization circuit composed of a clock control circuit that outputs demodulated data by punching out the restored signal waveform at N, the N discrete signals sampled at the interval T _s are stored and stored. A storage circuit that outputs values in reverse order, and a switch that changes the input of the interpolation filter from the input of the discrete signal to the output of the storage circuit, the switch connected to the input of the discrete signal, A first input of the N discrete signals to the interpolation filter for clock synchronization and a simultaneous input of the N discrete signals to the storage circuit;
And a second step of connecting the switch to the output of the storage circuit, inputting N stored discrete signals to the interpolation filter in reverse order, and outputting a clock-synchronized demodulated signal. A clock synchronization circuit comprising: