JPH0640245B2 - Thin film transistor matrix circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention is intended to prevent a control signal from being mixed into a display electrode by a parasitic TFT formed on a gate electrode and a gate bus line in a thin film transistor matrix by a simplified process. In addition, by electrically separating the parasitic TFT and the pixel electrode, it is possible to realize a thin film transistor matrix in which a control signal is not mixed into the pixel electrode.

TECHNICAL FIELD The present invention relates to a structure of a thin film transistor matrix by a simplified process.

A liquid crystal display with a built-in thin film transistor matrix is capable of color display as good as that of a CRT, and is therefore being developed for applications such as wall-mounted televisions and flat color OA terminals. This active matrix type liquid crystal panel needs to reduce a mask in a process of forming a thin film transistor (TFT), and a TFT structure of a simplified process has been proposed.
There is an adverse effect on the characteristics such as mixing of signals through T. Therefore, it is desired to realize a thin film transistor having excellent characteristics with a simplified process.

[Conventional technology]

Various techniques have been developed today as a method for manufacturing an active matrix element of an active matrix liquid crystal device. For example, single crystal silicon or polycrystalline silicon MOS
A device using an FET, amorphous silicon, a cadmium selenium thin film transistor, or the like is known. However, in order to form these active matrix elements, generally, complicated steps involving many photolithography steps are required, which is disadvantageous in terms of manufacturing and cost.

Therefore, a method of manufacturing a thin film transistor matrix circuit by a simplified process in which the manufacturing process is simplified has been proposed, and an example thereof is given in the following document.

"AN IMPROVED DESIGN OF ACTIVE MATRIX LCD REQUIRIN
G ONLY TWO PHOTOLITHOGRAPHIC STEPS "1985 INTENATION
AL DISPLAY RESEARCH CONFERENCE.

In this document, a top gate type (staggered type) TFT is used.
Stuff is mentioned.

FIG. 8 is a plan view of one pixel area of a conventional TFT matrix circuit, and FIG. 7 is a sectional view taken along the line aa 'in FIG.

In the figure, 1 is a drain bus line made of ITO, 2 is a pixel electrode made of ITO, and 3 is hydrogenated amorphous silicon (a-SiH-n ⁺ ) doped with phosphorus.
Layers 4 are hydrogenated amorphous silicon (a-SiH) layers,
Reference numeral 5 is a silicon oxide (SiO ₂ ) layer, 6 is an aluminum gate bus line, 7 is a source electrode, and 12 is a glass substrate.

This TFT matrix circuit can be formed by a two-mask process, and the amorphous silicon active layer (a-SiH) 4 is patterned by the same mask as the mask used when the uppermost gate bus line 6 is manufactured. Can be manufactured.

[Problems to be solved by the invention]

The manufacturing process of the TFT matrix circuit shown in FIGS. 7 and 8 is simplified, but the following problems occur.

That is, as described above, the active layer 4 of amorphous silicon is used.
Has a structure that remains in a most entangled manner over the entire lower surface of the gate bus line 6, as shown in the equivalent circuit of FIG.
A parasitic TFT 9 is formed in addition to the address TFT 8.

This parasitic TFT 9 will be located between the pixel electrode 2 and the drain bus 1 ′ adjacent thereto.

In this circuit, in addition to mixing a data signal from the adjacent drain bus line 1'through the parasitic TFT 9 at the time of address, the gate electrode of the parasitic TFT 9 and the address TFT 8 are also included.
Due to the capacitive coupling between the
There arises a problem of mixing with the source electrode 7 (that is, the pixel electrode 2) of the FT 8. Of these, the signal mixing through the capacitance between the gate and source electrodes of the latter has a large effect because the capacitance of the parasitic TFT 9 is large.

For this reason, it becomes difficult to accurately control the effective value voltage applied to the liquid crystal cell 10 by the data voltage (potential of the data bus at the time of addressing), which becomes a serious problem especially when performing gradation display.

[Means for solving problems]

The object of the present invention is to solve the above problems when a TFT matrix is manufactured by a conventional simple method. According to the present invention, the object is to provide a thin film transistor (TFT) provided for each pixel and a gate of the TFT. In a thin film transistor matrix circuit having a gate bus line connected to an electrode and a drain bus line connected to a drain electrode of the TFT, and driving the pixel electrode by the TFT, the gate bus line and the upper part of the gate electrode (or A semiconductor layer that overlaps with the gate bus line and the gate electrode is provided in the lower part), and the semiconductor layer region that does not overlap with the drain bus line is formed by the drain electrode of the pixel TFT, the adjacent drain bus line (or the adjacent drain bus line and drain). The first region in contact with the electrode) and the drain of the pixel TFT Divided into a second region that contacts only the electrode (or drain electrode and drain bus line),
The thin film transistor matrix circuit is characterized in that a source electrode is provided in the second region and the source electrode and the pixel electrode are connected.

[Action]

In the TFT matrix circuit of the present invention, the address TFT and the parasitic TFT are separated from each other around the drain electrode, so that the address TFT 8 and the parasitic TFT 9 are electrically separated as shown in the equivalent circuit of FIG. Source electrode 7 of address TFT 8 through parasitic TFT 9
Signals are not mixed into the (pixel electrode 2), and good display quality can be obtained.

〔Example〕

 The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a plan view of one pixel area of a TFT matrix circuit according to the first embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line 1'-1 'in FIG. 1, and FIG. 3 shows an equivalent circuit. .

A method of manufacturing the TFT matrix circuit of the present invention will be described with reference to FIGS. 1 and 2.

First, as a first step, ITO is formed as a transparent conductive film on the glass substrate 12 by vapor deposition or the like to a thickness of 500 to 2000 Å, and a mixed gas of silane gas (SiH ₄ ), H ₂ gas, and PH ₃ gas is formed thereon. (P) -doped hydrogenated amorphous silicon film (a-SiH-
n ⁺ ) is formed to a thickness of 100 to 500Å.

Next, using the first mask, the drain bus line 1,
1 ', the drain electrode 11, the pixel electrode 2, and the source electrode 7 are left, and the others are removed by etching.

Next, as a second step, a mixed gas of SiH ₄ gas and H ₂ gas is used, and an amorphous silicon semiconductor layer (a-SiH) 4 is formed to a thickness of 100 to 1000Å by a plasma CVD method. Further, aluminum is vapor-deposited thereon to a thickness of 2000 Å to 1 μm, and the gate bus line 6 and the gate electrode 13 are patterned and formed using the second mask, and aluminum other than the gate bus line 6 and the gate electrode 13 is formed. The layer and the a-SiH-n ⁺ layer are removed by etching.

The a-SiH-n ⁺ layer is inserted to maintain good ohmic contact.

In the present invention, as shown in FIG. 1, a portion of the semiconductor layer existing under the gate bus line 6 and the gate electrode 13 and not overlapping the drain bus lines 1 and 1 '(first
The hatched portion in the figure) is completely replaced by the drain electrode 11 in the parasitic TFT portion and the address TFT portion.
It is a divided structure.

The channel of the address TFT is formed between the drain electrode 11 and the source electrode 7, and as shown in the equivalent circuit of FIG. 3, the address TFT 8 is a parasitic TFT.
9 is electrically separated, and in this configuration, the parasitic TFT 9
Therefore, no signal is mixed into the pixel electrode 2 of the address TFT.

4 to 6 are plan views of a TFT matrix circuit according to another embodiment of the present invention, and the manufacturing method and the equivalent circuit are the same as those in the embodiment of FIG.

In the embodiment shown in FIG. 5, the gate bus line 6 has a pattern including a gate electrode, and in the embodiment shown in FIG. 6, the drain bus lines 1 and 1'have a pattern including a drain electrode.

〔The invention's effect〕

As described above, according to the present invention, even if the TFT matrix circuit by the simplified process is adopted, the address TFT and the parasitic TFT are electrically separated,
There is an advantage that signals are not mixed into the address TFT through the parasitic TFT, accurate voltage control can be performed on the liquid crystal cell, high-quality gradation display is possible, and the display panel is easily manufactured.

[Brief description of drawings]

FIG. 1 is a plan view of a TFT matrix circuit according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the line 1--1'-1 'in FIG. 1, and FIG. 3 is an equivalent circuit diagram of the TFT shown in FIG. 4 to 6 are plan views of a TFT matrix circuit according to another embodiment of the present invention, FIG. 7 is a sectional view taken along the line aa 'in FIG. 8, and FIG. 8 is a plan view of a conventional TFT Mahelix circuit. Figure,
FIG. 9 shows an equivalent circuit diagram of the TFT shown in FIG. In the figure, 1 and 1'is a drain bus line, 2 is a pixel electrode, 3 is an a-SiH-n ⁺ layer, 4 is a semiconductor layer (a-SiH), 5
Is a SiO ₂ layer, 6 is a gate bus line, 7 is a source electrode, 8 is an address TFT, 9 is a parasitic TFT, 10 is a liquid crystal cell, 11 is a drain electrode, 12 is a glass substrate, 13
Indicates a gate electrode.

Claims (1)

[Claims] 1. A thin film transistor (TF) provided for each pixel.
T), a gate bus line (6) connected to the gate electrode (13) of the TFT, and a drain bus line (1) connected to the drain electrode (11) of the TFT. In the thin film transistor matrix circuit for driving the electrode (2), a semiconductor layer overlapping with the gate bus line and the gate electrode is provided on (or under) the gate bus line (6) and the gate electrode (13), and a drain bus line is formed. The semiconductor layer region that does not overlap is defined as the drain electrode (1
According to 1), the first region in contact with the adjacent drain bus line (1, 1 ′) (or the adjacent drain bus line and drain electrode) and the drain electrode (11) (or the drain electrode and drain bus) of the pixel TFT. line)
And a source electrode (7) is provided in the second region. The source electrode (7) and the pixel electrode
A thin film transistor matrix circuit characterized in that (2) is connected.