JPH0640283B2 - Programmable controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller, and more particularly, to a function capable of adjusting a timer time of a watchdog timer for monitoring whether or not the system operation of a microprocessor is normal. A programmable controller provided.

<< Prior Art and its Problems >> In the conventional programmable controller, depending on whether or not the round-trip execution time of a user instruction (for example, user step 0 to END instruction) corresponding to the ladder diagram exceeds a certain value, It is general to perform monitoring with a watchdog timer as described above.

And normally, the watchdog timer used here is
The timer time is set to a fixed value of 130 mS corresponding to the execution time of arithmetic instructions, transfer instructions, etc., which requires a relatively long execution time, and only when the system operation of the microprocessor is normal. The system program includes processing for issuing a reset output to the watchdog timer.

Further, when an abnormality occurs in the system operation, the time-up output from the watchdog timer is used to forcibly reset the microprocessor.

However, in such a conventional case, when many instructions with a long execution time are used in a program,
Even if many large instructions can be inserted in terms of program capacity, the round-trip execution time when the system operation is normal may exceed the timer time of the watchdog timer.

In this way, when the round-trip execution time exceeds the timer time of the watchdog timer (for example, 130 mS), the watchdog timer cannot be reset before the set time even if the system operation is normal. , There was a problem that an instruction with a long execution time could be put into a program only within a range commensurate with the watchdog timer time.

<Object of the Invention> The present invention has been made in view of the above problems, and an object of the present invention is to systematically set the timer time of a watchdog timer so that a large number of instructions with a long execution time can be used in a program. It is to be adjustable.

<< Structure and Effect of the Invention >> In order to achieve the above object, the present invention relates to a programmable controller that cyclically performs an input update process, a user program execution process, an output change process, a system service process, etc. by a microprocessor; A watchdog timer that starts a predetermined fixed time in response to a start signal given from the microprocessor and resets the microprocessor when the time is completed; and a fixed time shorter than the set time of the watchdog timer is repeated. A timed interrupt timer for timing and interrupting the microprocessor each time the timing is completed; a watchdog timer restarted in response to a predetermined timer extension instruction being decoded during execution of the user program. Start and at the same time extend the timer And a timer time changing means for storing the extension number information attached to each time; When the microprocessor refers to the stored extension number information each time the fixed-time interrupt timer interrupts, it means a timer extension The timer extension means restarts the watchdog timer each time an interrupt is made until the interrupt count reaches the extension count, and resets the timer time to the normal time when the extension count is reached. It is characterized by being provided.

With such a configuration, even when a large number of instructions such as arithmetic instructions and transfer instructions having a relatively long execution time are included in the program, after a predetermined timer extension instruction corresponding to the instructions is given, , The watchdog timer is reset when the system operation is normal.

As a result, the user can freely set the timer time of the desired user program regarding the timer time of the watchdog timer.

<< Description of Embodiments >> FIG. 1 is a block diagram showing an overall schematic configuration of a programmable controller to which the present invention is applied.

In this programmable controller, the microprocessor (MPU) 1 becomes the center of overall control. The system program memory 2 stores a system program executed by the microprocessor 1, and the working memory 3 is used by the microprocessor 1 as a temporary storage area for various variable data.

An input / output circuit (input circuit and output circuit) including a user program memory 4 in which a sequence control program arbitrarily set by the user is stored, an input interface to which an external input signal is applied and an output interface for transmitting an external output signal 5) and input / output circuit 5
I / O serving as a buffer memory for input / output data
And a memory 6.

Further, in addition to such a basic configuration, a watchdog counter 8 and a timed interrupt counter 9 having a common oscillation circuit 7 are provided, and a combination of the oscillation circuit 7 and the watchdog counter 8 constitutes a watchdog timer. In addition, a combination of the oscillation circuit 7 and the fixed-time interrupt counter 9 constitutes a fixed-time interrupt timer.

Here, the watchdog timer starts counting a preset fixed time in response to an activation signal given from the microprocessor 1 to the watchdog timer 8,
The microprocessor 1 is reset when the timing is completed.

The timed interrupt timer repeatedly counts a fixed time shorter than the set time of the watchdog timer, and interrupts the microprocessor 1 each time the timing is completed.

As is well known, in the operation of executing a user program in this type of programmable controller, user instructions (for example, corresponding to a ladder diagram) are sequentially read from the user program memory 4 and stored in the I / O memory 6 according to each user instruction. That is, referring to the input / output data being processed, the arithmetic processing is performed, and the designated output data of the I / O memory 6 is updated according to the processing result.

Further, in a time zone different from the execution of the series of user programs, the input data given to the input circuit are collectively written in the processing area of the I / O memory 6 (input update), and the I / O memory 6 is also updated. The operation (output update) of collectively transferring the output data of the predetermined area to the output circuit is performed.

In still another time zone, the system service program stored in the system program memory 2 is read out as needed to perform various operations (system service) such as input / output monitoring and user program modification.

In this way, by executing the system program stored in the system program memory 2 by the microprocessor 1, input update processing, user program execution processing, output update processing, system service processing, etc. are cyclically performed. .

In the programmable controller described above, the present invention further functions as timer time changing means and timer extending means by executing an extension instruction to be described later, and performs timer time changing processing and timer extending processing,
As described below with reference to the flow chart, the timer time of the watchdog timer can be systematically adjusted.

As shown in the flowchart of the entire system of FIG. 2, the step (2) following the initial processing of the step (201)
In 02), the system service program stored in the system program memory 2 is read out as needed, and system service processing such as modification of the user program is performed.

Next, in step (203), the input update of transferring the input data given to the input / output circuit 5 to the I / O memory 6 is performed, and in the following step (204), the execution mode flag F is set to execute the user program. If the mode is other than the mode, the process returns to the system service process of step (202), and step (20
2) to (204) are repeated.

Here, in the case of the execution mode, the process proceeds to step (205), and instruction execution processing is sequentially executed as shown in the flowchart of FIG.

In FIG. 3, in the first step (301), the program counter PC is cleared, and in the following step (30
In 2), a reset pulse is issued from the microprocessor 1 to the watchdog counter 8, so that the watchdog counter 8 is restarted (reset) before the completion of counting.

In the next step (303), the RST counter is cleared, and in the following step (304), the user instruction designated by the program counter PC is read from the user program memory 4 and temporarily stored in the working memory 3.

In the following step (305), the step (304)
It is determined whether or not the read instruction of is the END instruction. E here
If it is not an ND instruction, that instruction is executed by interpreter processing in steps (306) to (309).

First, in step (306), it is determined whether or not the instruction is an instruction to extend the timer time of the watchdog timer (herein, it is represented by an operation code "WDT" and an operand "n" as shown in FIG. 5), and an extension instruction is issued. If so, in the subsequent step (307), the extension number (operand "n") given to the timer extension instruction is set in the RST number counter, and in the following step (308), the watchdog counter 8 is counted before completion. restart.

If the result of determination in step (306) is not an extension instruction, the process proceeds to step (309), and another instruction is executed.

Next, in step (310), the program counter PC is incremented, and the flow returns to the instruction reading in step (304). After that, steps (304) to (310) are repeatedly executed unless it is the END instruction at step (305).

On the other hand, the fixed-time interrupt counter 9 counts the number of pulses of the oscillation circuit 7 corresponding to a fixed time (for example, 100 mS) shorter than the count-up time (normally 130 mS) of the watchdog counter 8. The count-up output from 9 is constantly added to the microprocessor 1 as an interrupt signal. Then, as shown in the flowchart of FIG. 4, the timer extension process of step (401) and subsequent steps is performed each time the interrupt occurs.

First, if it is determined in step (401) that the value of the RST number counter is not zero, step (40)
In 2), restart the watchdog counter 8 at the timing based on the time-up output of the scheduled interrupt counter 9,
In the subsequent step (403), the RST number counter is decremented, and the timer extension process ends.

If the value of the RST counter is zero in step (401), the timer extension process is not performed.

When it is determined in step (305) shown in FIG. 3 that the instruction reading has been completed, the following step (311)
Then, the watchdog counter 8 is restarted before the completion of counting.

When the instruction execution process of step (205) in the main process shown in the flowchart of FIG. 2 is performed in this way, the process proceeds to the following step (206), and the I / O memory 6
Output data is transferred to the input / output circuit 5, and the output is updated as an external output signal. When this output is updated, the process returns to the system service process of step (202).

As described above, in this embodiment, in order to deal with the case where an element that increases the round-trip execution time on the user program (the total amount of these when there are many operation instructions and transfer instructions) is added,
By writing a predetermined timer extension instruction [WDT / n] in the user program memory 4 in advance as shown in FIG. The watchdog counter 8 can be restarted n times each time an interrupt is generated by the time-up output of the built-in counter 9 to substantially extend the watchdog timer.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall schematic configuration of a programmable controller to which the present invention is applied, FIG. 2, and FIG.
4 and 5 are flowcharts showing the software configuration of a system to which the present invention is applied, and FIG. 5 is a sequence ladder diagram showing an example of a user program in a programmable controller to which the present invention is applied. 1 ... Microprocessor 2 ... System program memory 3 ... Working memory 4 ... User program memory 5 ... I / O circuit 6 ... I / O memory 7 ... Oscillation circuit 8 ... Watchdog counter 9 ... Scheduled time Interrupt counter

Claims (1)

[Claims] 1. A programmable program for cyclically performing input update processing, user program execution processing, output change processing, system service processing, etc. by a microprocessor.
A controller; a watchdog timer that starts a predetermined fixed time in response to a start signal given from the microprocessor and resets the microprocessor when the time is completed; and a time shorter than a set time of the watchdog timer A timed interrupt timer that repeatedly counts a fixed time and interrupts the microprocessor each time the timing is completed; and in response to a predetermined timer extension instruction being decoded during execution of the user program, the watch. A timer time changing means for restarting the dog timer and at the same time storing the extension number information attached to the timer extension instruction; each time the microprocessor interrupts with the fixed-time interrupt timer, the stored extension number Refer to the information, and if this means timer extension, then interrupt A timer extending means for restarting the watchdog timer at each interruption until the number reaches the extension number, and for returning the timer time to the normal time when the extension number is reached, Programmable controller.