JPH0640561B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION [Outline] In a three-dimensional semiconductor device having a four-layer structure, MISF having source / drain regions formed by diffusing or injecting a p-type impurity into a semiconductor substrate and a fourth semiconductor crystal layer.
A layer in which ET is provided and a MISFET having a source / drain region formed by diffusing or injecting n-type impurities into the second and third semiconductor crystal layers is provided, and boron in a p-type impurity is diffused and implanted. Reduce heat treatment.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a three-dimensionally (three-dimensionally) stacked SOI structure among semiconductor devices.

Semiconductor integrated circuits (ICs) have been miniaturized and highly integrated in two-dimensional (planar) areas such as LSIs and VLSIs. However, if they are highly integrated, they have the advantage of improving circuit characteristics such as high-speed operation. Because it is big. However, there is a limit to miniaturization, and as a means for further increasing the degree of integration, a three-dimensional semiconductor device (three-dimensional LSI) in which ICs are three-dimensionally stacked is currently under study.

The basis of such a three-dimensional LSI is the SOI (Si
A semiconductor device (transistor) having a licon on insulator structure, in which a non-single crystalline semiconductor layer is deposited on an insulating film, crystallized by beam annealing, and the device is formed on the crystal layer. , Thus, two layers through the insulating film,
This is a structure in which three layers and a semiconductor crystal layer are stacked.

However, it is desirable from the standpoint of yield and quality that such a three-dimensional semiconductor device is constructed so as not to adversely affect the semiconductor elements provided in the upper and lower layers.

[Prior Art] FIG. 2 shows a cross-sectional view of a three-dimensional CMOS semiconductor device stacked in four layers as a conventional example, in which 1 is an n-type silicon substrate and 2 is a p-well region. A p-channel semiconductor element 3 and an n-channel semiconductor element 4 are provided on the substrate 1 to form a CMOS inverter cell.

In addition, the p-channel semiconductor element 5 is formed on the second layer through the insulating film.
And an n-channel semiconductor element 6 are provided, and a CM
It constitutes an OS inverter cell, and p is also formed in the third layer.
The channel semiconductor element 7 and the n-channel semiconductor element 8 are provided, and the p-channel semiconductor element 9 and the n-channel semiconductor element 8 are also provided in the fourth layer.
A channel semiconductor element 10 is provided, both of which are CMOS
FIG. 2 shows a semiconductor device which constitutes an inverter cell and in which CMOS inverter cells are three-dimensionally integrated.

In addition, 11 is a field oxide film and other insulating films, and 12 is a connection wiring between elements. Further, FIG. 3 shows a CMOS
In the inverter circuit diagram, the power supply symbols VDD and Vss in the figure and the second
It corresponds to VDD and Vss shown in the figure.

[Problems to be Solved by the Invention] Incidentally, in the case of forming a semiconductor device having an SOI structure as described above, a non-single crystalline semiconductor layer (such as a polycrystalline silicon film) is formed on an insulating film, as is well known. The semiconductor substrate (semiconductor crystal layer) that was crystallized by beam annealing and beam annealing was used as the substrate. (Grain Boun
dary) exists. That is, such a semiconductor crystal layer is an aggregate of large crystal grains, and is formed so that the crystal grain boundaries do not adversely affect the semiconductor crystal layer as much as possible.

However, when forming a semiconductor element, high-temperature heat treatment such as annealing at the time of ion implantation and formation of a gate oxide film cannot be avoided, and the heat treatment causes accelerated diffusion through grain boundaries. There is a problem of degrading device characteristics. For example, in a semiconductor device having a channel region with a channel length of 3 μm, the heat treatment temperature and time are 1050 in total.
The limit is about 20 minutes at ℃. Further, in heat treatment at a higher temperature for a longer time than that, the quality of the device is deteriorated due to the accelerated diffusion through the crystal grain boundary, and the device is difficult to be formed, so that the yield is reduced.

On the other hand, as the impurity material diffused or ion-implanted into the semiconductor layer, boron (B) is usually used as the p-type doping material, and arsenic (As) or phosphorus (P) is used as the n-type doping material. The diffusion coefficient of boron is extremely larger than the diffusion coefficients of arsenic and phosphorus, and therefore, the amount of impurities that precipitate at the grain boundaries is high.

Therefore, if the precipitation of boron is suppressed, the semiconductor device having the SOI structure can be improved in quality, and the present invention takes this point into consideration to improve the yield and improve the quality of the three-dimensional semiconductor. It proposes the structure of the device.

[Means for Solving Problems] The purpose is to provide a second layer, a third layer and a fourth layer on a semiconductor substrate.
In a semiconductor device having a four-layer structure in which semiconductor crystal layers of four layers are stacked, a semiconductor element for diffusing or injecting p-type impurities into the semiconductor substrate and the semiconductor crystal layer of the fourth layer to form source / drain regions is provided, The n-type impurities are diffused or injected into the second and third semiconductor crystal layers to form the source / source.
This is achieved by a semiconductor device provided with a semiconductor element forming a drain region.

For example, a p-channel MIS semiconductor element is provided on the semiconductor substrate and the fourth semiconductor crystal layer, and an n-channel MIS semiconductor element is provided on the second and third semiconductor crystal layers.

[Operation] That is, in the semiconductor device according to the present invention, when the recrystallized Si film is used, a semiconductor element for forming source / drain regions is formed in the uppermost layer by diffusing or implanting boron having a large diffusion coefficient. .

Then, since the number of heat treatments after the boron is contained is reduced, the quality of the semiconductor device having a three-dimensional structure is improved.

[Examples] Hereinafter, examples will be described in detail with reference to the drawings.

FIG. 1 is a sectional view of a three-dimensional MIS type semiconductor device according to the present invention, in which 1 is an n-type silicon substrate and 13 and 14 are n-types.
In the p-channel semiconductor device provided on the silicon substrate 1, the n-channel semiconductor devices 23 and 24 are provided on the second semiconductor crystal layer II and formed on the silicon substrate 1 and the second semiconductor crystal layer II. A semiconductor element, that is, a p-channel semiconductor element 13 and an n-channel semiconductor element 23, and a CMOS
An inverter cell is formed, and the p-channel semiconductor element 14 and the n-channel semiconductor element 24 form a CMOS inverter cell.

Similarly, the third semiconductor crystal layer III is provided with n-channel semiconductor elements 33, 34, and the fourth semiconductor crystal layer iv is provided with p-channel semiconductor elements 43, 44. III and the semiconductor element formed in the fourth semiconductor crystal layer iv, that is, the n-channel semiconductor element 33 and the p-channel semiconductor element 43 constitute a CMOS inverter cell, and
The n-channel semiconductor element 34 and the p-channel semiconductor element 44 form a CMOS inverter cell above and below. In addition, 11 is an insulating film and 12 is a connection wiring.

Then, each of these MOS semiconductor elements undergoes heat treatment by implanting impurity ions in order to form source / drain regions, and heat treatment for oxidation in order to form a gate oxide film. Therefore, each time one layer of MOS semiconductor element is formed, it is heated at a high temperature (for example, around 1000 ° C.) for several minutes or several tens of minutes.

Then, when this three-dimensional semiconductor device is completed,
The heat treatment for the semiconductor elements formed in the third and fourth semiconductor crystal layers is added to the semiconductor element formed in the second semiconductor crystal layer II, and the third semiconductor crystal layer III is also added.
The heat treatment for the semiconductor element formed in the fourth semiconductor crystal layer is added to the semiconductor element formed in. Then, with each heat treatment, boron (p-type impurities) and arsenic (n-type impurities) diffuse more rapidly through the crystal grain boundaries. However, the semiconductor device formed in the fourth semiconductor crystal layer iv is only subjected to the heat treatment of the device itself.

Thus, the structure according to the present invention is the second semiconductor crystal layer.
Since an n-channel semiconductor element is formed in II and the third semiconductor crystal layer III, arsenic is diffused or implanted into the source / drain regions to form n-type regions. Further, since the p-channel semiconductor element is formed in the fourth semiconductor crystal layer iv, the source / drain regions are made into p-type regions by diffusing or implanting boron.

Therefore, the fourth semiconductor crystal layer iv diffuses or implants boron having a large diffusion coefficient, and the second semiconductor crystal layer II and the third semiconductor crystal layer III diffuse arsenic having a small diffusion coefficient. Upon implantation, a region having a region in which boron having a large diffusion coefficient is diffused or implanted (fourth
The semiconductor element provided in the semiconductor crystal layer iv) has a structure in which the heat treatment is reduced, and the amount of impurities diffused through the grain boundaries is reduced as a whole. Therefore, the yield and quality of the structure of the three-dimensional semiconductor device according to the present invention are improved.

It should be noted that here, the source / drain regions are formed by diffusing or implanting boron having a large diffusion coefficient also in the n-type silicon substrate 1, but since the silicon substrate has no crystal grain boundary, it is increased through the grain boundary. Does not cause rapid diffusion. Further, the channel region of each semiconductor element has a smaller amount of impurities such as boron and arsenic than the source / drain regions, and even if diffused, a short circuit between the source and drain may occur. Therefore, as described above, there is no influence as much as the source / drain region having a large impurity content,
Therefore, the yield and quality are improved.

Moreover, the beam annealing of the substrate is also a high temperature heat treatment,
Since this is an extremely short-time treatment, there is no fear of causing diffusion of impurities.

Also in the conventional structure, a three-dimensional structure is known in which a p-channel semiconductor element and an n-channel semiconductor element are provided on the upper and lower sides and electrodes are connected on the upper and lower sides. However, like the structure according to the present invention, each layer has The channel type of the semiconductor element to be provided is not specified.

[Effects of the Invention] As is clear from the above description, the structure according to the present invention has a great effect of improving the yield and quality.

[Brief description of drawings]

FIG. 1 is a sectional view of a three-dimensional MIS type semiconductor device according to the present invention, FIG. 2 is a sectional view of a conventional three-dimensional MIS type semiconductor device, and FIG. 3 is a CMOS inverter circuit diagram. In the figure, 1 is an n-type silicon substrate, II is a second semiconductor crystal layer, III is a third semiconductor crystal layer, iv is a fourth semiconductor crystal layer, 13, 14, 43 and 44 are p-channel semiconductor elements, 23, 24, 33 and 34 are n-channel semiconductor elements, 11 is an insulating film, and 12 is a connection wiring.

Claims (2)

[Claims] 1. A second layer, a third layer and a fourth layer on a semiconductor substrate.
A semiconductor device having a three-dimensional structure in which four layers of semiconductor crystal layers are stacked, having source / drain regions formed by diffusing or injecting p-type impurities into the semiconductor substrate and the fourth semiconductor crystal layer. A semiconductor device comprising a MISFET and a MISFET having a source / drain region formed by diffusing or injecting n-type impurities into the semiconductor crystal layers of the second and third layers. 2. A p-channel MISFET is provided on the semiconductor substrate and the fourth semiconductor crystal layer, and an n-channel MISFET is provided on the second and third semiconductor crystal layers. The semiconductor device according to item 1.