JPH0646279B2 - Method of manufacturing thin film transistor array - Google Patents

Description

TECHNICAL FIELD The present invention relates to a thin film transistor array used in an active matrix type liquid crystal display or the like, and a method for manufacturing the same.

[Prior Art] A thin film transistor (hereinafter, referred to as TFT) array is used for an active matrix type liquid crystal display or the like. In the TET array described above, insulation failure occurring in an overlap portion between a gate wiring and an upper electrode is reduced. Therefore, it has been proposed that the gate wiring is formed of Ta (tantalum) and the Ta anodic oxide film obtained by anodizing the Ta gate wiring is used as a part of the interlayer insulating film between the gate wiring and the upper electrode.

FIG. 6 shows a plan view when the TFT array having the above structure is used for an active matrix type liquid crystal display. In the figure, 1 is an insulating substrate made of glass or the like, 2 is a Ta gate wiring formed on the insulating substrate 1, and 4 is a Ta anodic oxide film formed by anodizing the Ta gate wiring 2. Is. Reference numeral 5 is a source electrode, 6 is a drain electrode, 7 is a source wiring, and 8 is a pixel electrode, which are collectively referred to as an upper electrode.

FIG. 7 shows an example of a manufacturing process for forming the Ta gate wiring 2 and the Ta anodic oxide film.
A description will be given below with reference to FIG.

(A) A Ta thin film 9 is formed on the insulating substrate 1, and the Ta thin film 9 is formed.
A photoresist 10 is applied on the thin film 9, and the photoresist is exposed and developed in the shape of a gate wiring.

(B) The Ta thin film is etched by using the photoresist as a mask to form the Ta gate wiring 2.

(C) Peel off the photoresist.

(D) The Ta gate wiring 2 is anodized to form a Ta anodic oxide film 4.

[Problems to be Solved] When the Ta gate wiring is anodized, the film thickness of the Ta gate wiring becomes thin, and as a result, the resistance value of the gate wiring increases.
This increase in the resistance value causes a delay in ON / OFF signals to the gate of the TFT connected to the gate wiring, which causes a disadvantage in the circuit operation. Attempts have been made to increase the film thickness of Ta in order to reduce the resistance value of the gate wiring, but if the film thickness is large, the upper electrode may be disconnected due to the step at the peripheral portion of the Ta gate wiring, which lowers the manufacturing yield. Bring Therefore, in the above-mentioned conventional configuration, the Ta film thickness cannot be increased, and as a result, the resistance value of the Ta gate wiring becomes high, causing a serious problem in circuit operation.

An object of the present invention is to provide a method of manufacturing a thin film transistor array capable of reducing the resistance value of Ta gate wiring without increasing insulation failure.

[Means for Solving the Problems] A method of manufacturing a thin film transistor array according to the present invention is
A step of applying a photoresist to a Ta (tantalum) thin film formed on a translucent insulating substrate, exposing the photoresist to the shape of Ta gate wiring, and developing the photoresist; and masking the developed photoresist. As described above, a step of etching the Ta thin film to form a Ta gate wiring, a step of irradiating ultraviolet rays from the back surface of the insulating substrate to expose and redevelop the peripheral portion of the developed photoresist, and the redevelopment. The portion of the Ta wiring not covered with the formed photoresist is anodized at a first formation voltage and then the T
a step of forming a Ta anodic oxide film on the peripheral portion of the gate wiring.

In addition, a step of removing the redeveloped photoresist, and anodizing the Ta gate wiring at a second formation voltage lower than the first formation voltage to expose the Ta gate wiring except the peripheral portion thereof. Also, the step of forming a Ta anodic oxide film may be added to the above steps.

[Examples] Examples will be described below with reference to the drawings.

Example 1 In FIG. 1, 1 is an insulating substrate having a light-transmitting property such as glass, 2 is a Ta gate wiring, 3 is a peripheral portion of the Ta gate wiring, 4 is a Ta anodic oxide film, and 5 is a source electrode. , 6 is a drain electrode, 7 is a source wiring, 8 is a pixel electrode 9,
These form the upper electrode.

The locations where insulation failure occurs in the overlapping portion of the Ta gate wiring 2 and the upper electrode are overwhelmingly concentrated in the wiring peripheral portion 3 of the Ta gate wiring 2. Therefore, as shown in the figure, even if the Ta anodic oxide film 4 is formed only on the wiring peripheral portion 3 of the Ta gate wiring 2, it is possible to sufficiently exert the effect as a countermeasure against insulation failure. In this example, since the Ta anodic oxide film 4 is formed only on the wiring peripheral portion 3 in this way, the film thickness of the Ta gate wiring 2 other than the wiring peripheral portion 3 does not become thin, and the resistance value of the Ta gate wiring 2 is It hardly increases. Therefore, it is possible to significantly reduce the problem in circuit operation due to the increase in the resistance value of the Ta gate wiring.

FIGS. 2A to 2D show steps for obtaining the Ta gate wiring and the Ta anodic oxide film for obtaining the above-described structure, and the manufacturing steps will be described below with reference to the same figure.

(A) A Ta thin film 9 having a thickness of 250 nanometers is formed on an insulating substrate 1 having a light-transmitting property by a sputtering method, a photoresist 10 is applied on the Ta thin film 9, and the Ta thin film 9 is used as a gate wiring. Expose and develop into shape.

(B) The Ta thin film 9 is dry-etched with a CF ₄ gas to form the Ta gate wiring 2. Next, the back surface of the insulating substrate 1 is irradiated with ultraviolet light 11. At this time, the peripheral portion of the photoresist 10 is exposed by diffraction or reflection of the ultraviolet light 11, but the Ta gate wiring 2 except the peripheral portion.
Thus, the ultraviolet light is blocked, so that the photoresist is not exposed.

(C) The exposed portion of the peripheral portion of the photoresist 10 is developed to expose the wiring peripheral portion 3 of the Ta gate wiring 2.

(D) The wiring peripheral portion 3 of the Ta gate wiring 2 not covered with the photoresist 10 is anodized in a 1% citric acid aqueous solution to form a Ta anodic oxide film 4, and the photoresist is peeled off. The formation voltage at this time is 150 V, and the Ta anodic oxide film 4 having a thickness of 300 nm can be obtained.

Since the Ta anodic oxide film 4 obtained by the above steps is formed only on the wiring peripheral portion 3 of the Ta gate wiring 2, the resistance value of the Ta gate wiring 2 hardly increases. In addition,
The photoresist may be formed by a normal mask process without using the above method. This is because a Ta anodic oxide film having a certain width based on a predetermined design rule is formed on the peripheral portion of the wiring and anodized. It is preferable to use the above method because it leads to a decrease in the line width of the Ta gate wiring which is not formed and the degree of decrease in the resistance value becomes small.

Example 2 The step (e) of FIG. 3 is added after the steps of FIGS. 2 (a)-(d) of Example 1.

(E) The Ta gate wiring 2 is anodized at a formation voltage of 50 V, and the Ta anodic oxide film 4 is formed on a portion other than the wiring peripheral portion 3. At this time, the Ta anodic oxide film 4 newly formed
Has a thickness of 100 nanometers, and the Ta gate wiring 2 has a thickness of 200 nanometers. The film thickness of the Ta anodic oxide film 4 at the wiring peripheral portion 3 does not increase.

According to this example, the newly formed Ta anodic oxide film 4 can be flattened with the Ta anodic oxide film 4 formed on the wiring peripheral portion 3, and the yield can be improved in the subsequent thin film transistor array forming process. Can be expected.

Third Embodiment FIG. 4 is a plan view showing a third embodiment.

In this example, as shown in the figure, the Ta gate wiring 2 and the upper electrode are overlapped with each other, or the Ta gate wiring 2 is entirely or peripherally formed by the Ta anodic oxide film 4. In the upper electrode, the source electrode 6, the drain electrode 7 and the source wiring 8 and the Ta gate wiring 2 overlap each other, the Ta gate wiring 2 is entirely covered with the Ta anodic oxide film 4, and the pixel electrode 9 In the overlapping portion of the Ta gate wiring 2 and the Ta gate wiring 2, the peripheral portion of the Ta gate wiring 2 is covered with the Ta anodic oxide film 4. In addition,
In order to obtain the above structure, the Ta gate wiring 2 other than the portion to be anodized may be masked with a photoresist and anodized.

In this example, since the anodic oxide film 4 is formed only in the overlapping portion of the Ta gate wiring 2 and the upper electrode 5, the resistance value of the Ta gate wiring 2 can be reduced without increasing insulation failure. Therefore, it is possible to significantly reduce the problem in circuit operation due to the increase in the resistance value of the Ta wiring.

Fourth Embodiment FIG. 5 is a plan view showing a fourth embodiment.

In this example, as shown in the figure, only the peripheral portion of the Ta gate line 2 where the Ta gate line 2 and the upper electrode overlap each other is formed by the Ta anodic oxide film 4. The same effect as can be obtained.

EFFECTS OF THE INVENTION According to the present invention, the peripheral portion of the photoresist is exposed by UV back exposure and redeveloped, and the Ta anode is provided on the peripheral portion of the Ta gate line not covered by the redeveloped photoresist. Since the oxide film is formed, it is possible to reduce the resistance value of the Ta gate wiring without increasing insulation failure.

Further, when the Ta gate wiring is anodized at a formation voltage lower than the formation voltage for forming the Ta anodic oxide film on the peripheral portion of the Ta gate wiring, the thickness of the Ta anodic oxide film formed on the peripheral portion is smaller than that of the Ta anodic oxide film. The film thickness of the Ta anodic oxide film formed other than the peripheral portion can be reduced, the same effect as described above can be obtained, and the Ta anodic oxide film can be flattened, so that the manufacturing yield can be improved. It is possible to improve.

[Brief description of drawings]

FIG. 1 is a plan view showing the first embodiment, and FIG. 2 is FIG.
II-II manufacturing process sectional view, FIG. 3 is a sectional view showing the second embodiment, FIG. 4 is a plan view showing the third embodiment, and FIG. 5 is a fourth embodiment. FIG. 6 is a plan view showing a conventional structure, and FIG. 7 is a process sectional view taken along the line VII-VII in FIG. 6 showing a conventional manufacturing method. 1 ... Insulating substrate 2 ... Ta gate wiring 3 ... Edge 4 ... Ta anodic oxide film 10 ... Photoresist

Claims (2)

[Claims] 1. A Ta formed on a translucent insulating substrate.
A step of applying a photoresist to a (tantalum) thin film, exposing this photoresist to the shape of a Ta gate wiring, and developing it; and using the developed photoresist as a mask
A step of etching the thin film to form a Ta gate wiring; a step of irradiating the back surface of the insulating substrate with ultraviolet rays to expose and redevelop the peripheral portion of the developed photoresist; And a step of forming a Ta anodic oxide film on the peripheral portion of the Ta gate wiring by anodizing the Ta wiring not covered with the resist. 2. Ta formed on a transparent insulating substrate
A step of applying a photoresist to a (tantalum) thin film, exposing this photoresist to the shape of a Ta gate wiring, and developing it; and using the developed photoresist as a mask
A step of etching the thin film to form a Ta gate wiring; a step of irradiating the back surface of the insulating substrate with ultraviolet rays to expose and redevelop the peripheral portion of the developed photoresist; A step of anodizing the Ta wiring not covered with the resist to form a Ta anodic oxide film at the peripheral portion of the Ta gate wiring at a first formation voltage, and peeling the redeveloped photoresist. And a step of anodizing the Ta gate wiring at a second formation voltage lower than the first formation voltage to form a Ta anodic oxide film on a portion other than the peripheral portion of the Ta gate wiring. A method of manufacturing a thin film transistor array, comprising: