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JPH0646346B2 - Active matrix substrate - Google Patents
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JPH0646346B2 - Active matrix substrate - Google Patents

Active matrix substrate

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Publication number
JPH0646346B2
JPH0646346B2 JP60085242A JP8524285A JPH0646346B2 JP H0646346 B2 JPH0646346 B2 JP H0646346B2 JP 60085242 A JP60085242 A JP 60085242A JP 8524285 A JP8524285 A JP 8524285A JP H0646346 B2 JPH0646346 B2 JP H0646346B2
Authority
JP
Japan
Prior art keywords
picture element
active matrix
matrix substrate
line
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60085242A
Other languages
Japanese (ja)
Other versions
JPS61243486A (en
Inventor
一郎 山下
守 竹田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60085242A priority Critical patent/JPH0646346B2/en
Publication of JPS61243486A publication Critical patent/JPS61243486A/en
Publication of JPH0646346B2 publication Critical patent/JPH0646346B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) この発明はアクティブマトリクス方式の液晶ディスプレ
イ等に用いられるアクティブマトリクス基板に関する。
TECHNICAL FIELD The present invention relates to an active matrix substrate used for an active matrix type liquid crystal display or the like.

(従来の技術) 従来、この目的に使われるトランジスタアレイとして
は、例えば特願昭59−47623号(特開昭60−1
9236号公報)に示されるような構成が一般的であ
る。すなわち第2図に示した如く走査線X1〜XMへゲー
ト電極を、信号線Y1〜YNへソース電極を接続した薄膜
トランジスタ(以後TFTと呼ぶ)(11)を備え、そのドレ
イン電極は絵素電極(26)に接続されている。そしてこの
絵素電極(26)と対向アース電極との間には液晶(13)が挿
入され、独立した絵素(14)を構成する。ここで液晶(13)
は等価的にコンデンサとして働くが、場合によってはこ
れに並列に補助コンデンサが追加される事もある。
(Prior Art) Conventionally, as a transistor array used for this purpose, for example, Japanese Patent Application No. 59-47623 (Japanese Patent Application Laid-Open No. 60-1).
9236) is generally used. That is, as shown in FIG. 2, a thin film transistor (hereinafter referred to as a TFT) (11) having gate electrodes connected to the scanning lines X 1 to X M and source electrodes connected to the signal lines Y 1 to Y N is provided, and its drain electrode is It is connected to the pixel electrode (26). A liquid crystal (13) is inserted between the picture element electrode (26) and the counter earth electrode to form an independent picture element (14). Liquid crystal here (13)
Acts equivalently as a capacitor, but in some cases an auxiliary capacitor may be added in parallel with it.

斯かる構成のトランジスタアレイは以下の如く動作す
る。即ち走査線X1、X2、X3、…XMには第3図に示す
ような選択パルスP1、P2、P3…PMがそれぞれ印加さ
れるのであって、例えば走査線X1が選択状態(他のす
べての走査線は非選択)のとき、これに接続される一連
のTFT(11)のソース・ドレイン間が導通となり、それに
接続された各絵素(14)に対応する信号線の電圧が印加さ
れる。前記走査線X1が非選択に切り換わると、上記TFT
(11)は非導通となるので、上記絵素(14)に印加された電
圧は次のフレームで走査線X1が再び選択されるまでの
間、前回の値を保持する。このようにTFTアレイを用い
た液晶ディスプレイは必要な信号電圧を正確かつ独立に
各絵素に伝達することが出来るのでクロストークがなく
コントラスト比の大きい表示が可能となり注目を集めて
いる。
The transistor array having such a configuration operates as follows. That is, the selection pulses P 1 , P 2 , P 3 ... P M as shown in FIG. 3 are applied to the scanning lines X 1 , X 2 , X 3 , ... X M , respectively. When 1 is in the selected state (all other scan lines are unselected), the series of TFTs (11) connected to this becomes conductive between the source and drain, and corresponds to each picture element (14) connected to it. The voltage of the signal line to be applied is applied. When the scan line X 1 is switched to non-selection, the TFT
Since (11) becomes non-conductive, the voltage applied to the picture element (14) retains the previous value until the scanning line X 1 is selected again in the next frame. In this way, a liquid crystal display using a TFT array is capable of accurately and independently transmitting a required signal voltage to each picture element, so that it is possible to display with a high contrast ratio without crosstalk, which is drawing attention.

(発明が解決しようとする問題点) ところがこのような構成では走査線、信号線の本数が増
えると、すべてのTFT(11)を良品として作り込む事が極
めて困難となる。特に、TFT(11)は第4図にその断面構
造の一例を示すように、ゲート(21)とソース(22)・ドレ
イン(23)との間が少なくとも絶縁膜(24)を介して積層さ
れているため、ピンホールその他工程上のトラブルによ
ってゲート(21)・ソース(22)間、あるいはゲート(21)・
ドレイン(23)間が短絡してしまう恐れがある。特に、ゲ
ート(21)・ソース(23)間の短絡は、これにつながる走査
線X1〜XMと信号線Y1〜YM上のすべてのTFT(11)の動
作異常を招き、いわゆる線欠陥という重大不良をもたら
す。またドレイン電極や絵素電極がフォトリソグラフィ
の不良等により、ゲート電極やソース電極と短絡する
と、その液晶セルは正規の電圧を保持しなくなり点欠陥
をもたらす。
(Problems to be Solved by the Invention) However, in such a configuration, if the number of scanning lines and signal lines increases, it becomes extremely difficult to manufacture all the TFTs (11) as non-defective products. In particular, the TFT (11) is laminated between the gate (21) and the source (22) / drain (23) at least with the insulating film (24) interposed, as shown in FIG. Therefore, due to pinholes and other process troubles, the gate (21) and source (22) or the gate (21)
There is a risk of a short circuit between the drains (23). In particular, the gate (21) and source (23) short-circuit between the leads to abnormal operation of all of the TFT on the scan line X 1 to X M and the signal lines Y 1 to Y M connected thereto (11), a so-called line It causes serious defects such as defects. Further, when the drain electrode or the pixel electrode is short-circuited with the gate electrode or the source electrode due to defective photolithography or the like, the liquid crystal cell does not hold a regular voltage and causes a point defect.

本発明は上記問題点に鑑みて発明したもので、いくつか
のスイッチ素子が不良であっても、線欠陥や点欠陥に基
づく絵素欠陥が発生するようなことがない、アクティブ
マトリクス基板を提供する事を目的としている。
The present invention has been made in view of the above problems, and provides an active matrix substrate that does not cause a pixel defect based on a line defect or a point defect even if some switching elements are defective. The purpose is to do.

(問題点を解決するための手段) 即ち本発明は、各絵素(絵素Aとする)と信号線を結合
する第1のスイッチ素子と、絵素Aとこの絵素Aに隣接
する隣接絵素Bとを結合する第2のスイッチ素子を備
え、第1および第2のスイッチ素子を同一の走査線で制
御するように構成したことを特徴とするものである。
(Means for Solving the Problems) That is, according to the present invention, a first switch element that connects each picture element (referred to as picture element A) to a signal line, a picture element A, and an adjacency adjacent to the picture element A. It is characterized in that a second switch element that is connected to the picture element B is provided, and the first and second switch elements are controlled by the same scanning line.

(作用) 上記の構成により本発明では、第1のスイッチ素子が絵
素A及び絵素Bに同時に信号線からの情報を伝達する。
絵素Aに注目してみれば、絵素Aは必ず信号線からの充
電経路を2つ持っていることになる。従って充電経路を
構成スイッチ素子がたまたま不良であっても、この不良
のスイッチ素子を走査線及び絵素から切り離せば残りの
充電経路でもって絵素Aの動作が確保され、絵素欠陥と
なるのを防ぐことが出来る。
(Operation) With the above configuration, in the present invention, the first switch element simultaneously transmits information from the signal line to the picture elements A and B.
Focusing on the picture element A, the picture element A always has two charging paths from the signal line. Therefore, even if the switching element that constitutes the charging path happens to be defective, if the defective switching element is separated from the scanning line and the picture element, the operation of the picture element A is ensured by the remaining charging path, resulting in a picture element defect. Can be prevented.

処で上記のような冗長回路を追加する方法として、従来
例の構成に単にトランジスタを全く並列に追加する事も
考えられるが、これでは点又は線欠陥が発生してもどち
らのトランジスタが不良であるかを判別することが困難
で修復し難い。また1つの絵素当たり2本の走査線と2
つのトランジスタを設けて2つのトランジスタを別々の
走査線で制御する構成も考えられるが、この場合は絵素
の有効面積比(開口率)を大幅に低下させることにな
り、望ましくない。
As a method of adding the redundant circuit as described above, it is conceivable that transistors are simply added in parallel to the configuration of the conventional example, but in this case, even if a dot or line defect occurs, either transistor is defective. It is difficult to determine if there is and difficult to repair. Two scan lines and two per pixel
A configuration in which one transistor is provided and two transistors are controlled by different scanning lines is also conceivable, but in this case, the effective area ratio (aperture ratio) of the picture element is significantly reduced, which is not desirable.

(実施例) 以下、本発明の実施例を図面に基づいて説明する。この
実施例において用いるトランジスタは、例えば第4図に
断面構造を示したものなどとくに制約なく、MOSトラ
ンジスタや薄膜トランジスタ等を用いることが出来る。
さらに走査線に印加する選択パルスは従来例と同様、第
3図に示したものを用いる事が出来る。さて第1図の絵
素Ci,jへの上記Yjからの充電経路はトランジスタ(11a)
による直接経路と、トランジスタ(11c)、(11d)による間
接経路の2つがある。前者は走査線Xiで、後者は走査線
Xi-1で制御される。両者が正常に動作するときは、あと
で選択される方、つまり直接経路を通って充電される電
圧Vi,jが絵素Ci,jの動作を支配する。これはとりもなお
さず従来と同じ動作であり、トランジスタ(11b)(11c)の
存在は絵素Ci,jの正常動作に影響していないことを意味
する。
(Example) Hereinafter, the Example of this invention is described based on drawing. The transistor used in this embodiment is not particularly limited, for example, the one whose sectional structure is shown in FIG. 4, and a MOS transistor or a thin film transistor can be used.
Further, as the selection pulse applied to the scanning line, the one shown in FIG. 3 can be used as in the conventional example. Now, the charging path from Y j to the picture element C i, j in Fig. 1 is the transistor (11a).
There are two direct routes, and an indirect route by transistors (11c) and (11d). The former is scan line X i , the latter is scan line
It is controlled by X i-1 . When both operate normally, the one selected later, that is, the voltage V i, j charged through the direct path, controls the operation of the pixel C i, j . This means that the operation is the same as before, and the existence of the transistors (11b) and (11c) does not affect the normal operation of the picture elements C i, j .

次にトランジスタ(11a)が不良である場合は、トランジ
スタ(11a)とトランジスタ(11b)を同時に絵素Ci,jおよび
走査線Xiまたは信号線Yjから切り離す。このようにすれ
ば絵素Ci,jは、本来より1つの前のタイミングで走査線
Xi-1が選択されるタイミングで間接経路を通して電圧V
i-1,jなる電圧の充電を受け、これを1フレームにわた
って保持することになる。従ってこの場合絵素Ci,jは隣
接絵素Ci-1,jと同じ信号で動作し、トランジスタ(11a)
が不良のときでも絵素欠陥に至らずにすむ。基板上のト
ランジスタが不良になる確率をPとすれば、従来例では
絵素欠陥の発生確率もPに近い。しかし本発明に係るこ
の実施例の場合は、特定の絵素に関係する2つのトラン
ジスタが同時に不良にならない限り絵素欠陥には至ら
ず、絵素欠陥の発生確率はP×Pのオーダーになる。P
は1に比してはるかに小さいのが一般的であるから、基
板の歩留り向上効果の著しい事は容易に理解されよう。
Next, when the transistor (11a) is defective, the transistor (11a) and the transistor (11b) are simultaneously disconnected from the pixel C i, j and the scanning line X i or the signal line Y j . In this way, the picture element C i, j is scanned by the scanning line one timing before the original.
Voltage V through the indirect path when X i-1 is selected
It is charged with the voltage i-1, j and held for one frame. Therefore, in this case, the picture element C i, j operates with the same signal as the adjacent picture element C i-1, j, and the transistor (11a)
Even if the pixel is defective, it does not lead to a pixel defect. If the probability that a transistor on a substrate becomes defective is P, the probability of occurrence of pixel defects is close to P in the conventional example. However, in the case of this embodiment according to the present invention, a pixel defect does not occur unless two transistors related to a specific pixel become defective at the same time, and the occurrence probability of the pixel defect is on the order of P × P. . P
Is generally much smaller than 1, so it is easy to understand that the yield improvement effect of the substrate is remarkable.

(発明の効果) 以上詳述したように、本発明は簡単な構成であり、かつ
構成要素であるいくつかのスイッチ素子が不良であって
も線欠陥や点欠陥の如き絵素欠陥を発生するようなこと
がなくアクティブマトリクス基板の歩留りを大幅に改善
することができ、その実用的価値は大きいものである。
(Effects of the Invention) As described in detail above, the present invention has a simple configuration and causes pixel defects such as line defects and point defects even if some of the switch elements, which are constituent elements, are defective. Without such a situation, the yield of the active matrix substrate can be significantly improved, and its practical value is great.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明によるアクティブマトリクス基板の回路
図、第2図は従来例の回路図、第3図は走査線に印加す
る電圧波形図、第4図は薄膜トランジスタの断面図であ
る。 (11)、(11a〜d)……トランジスタ、(13)……液晶、
(14)……絵素、(22)……ソース、(23)……ドレイン、(2
5)……半導体膜、(26)……絵素電極。
FIG. 1 is a circuit diagram of an active matrix substrate according to the present invention, FIG. 2 is a circuit diagram of a conventional example, FIG. 3 is a voltage waveform diagram applied to a scanning line, and FIG. 4 is a sectional view of a thin film transistor. (11), (11a-d) …… transistor, (13) …… liquid crystal,
(14) …… Picture element, (22) …… Source, (23) …… Drain, (2
5) …… Semiconductor film, (26) …… Pixel electrode.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】複数の走査線Xと信号線Y、および各走査
線Xと信号線Yの交差点に対応して各1個設けた絵素電
極Aと、走査線Xで制御される第1および第2のスイッ
チ素子とを備え、第1のスイッチ素子は信号線Yと絵素
電極Aとを結合し、第2のスイッチ素子は前記絵素電極
Aと隣接絵素電極Bとを結合したことを特徴とするアク
ティブマトリクス基板。
1. A plurality of scanning lines X and signal lines Y, one pixel electrode A provided at each intersection of each scanning line X and signal line Y, and a first pixel line controlled by the scanning line X. And a second switch element, the first switch element connecting the signal line Y and the picture element electrode A, and the second switch element connecting the picture element electrode A and the adjacent picture element electrode B. An active matrix substrate characterized by the above.
【請求項2】前記第1および第2のスイッチ素子の端子
部が前記走査線、信号線または絵素電極から分離可能と
したことを特徴とする特許請求の範囲第1項に記載のア
クティブマトリクス基板。
2. The active matrix according to claim 1, wherein the terminal portions of the first and second switch elements are separable from the scanning lines, signal lines or picture element electrodes. substrate.
【請求項3】前記第1および第2のスイッチ素子をMO
Sトランジスタにより形成したことを特徴とする特許請
求の範囲第1項に記載のアクティブマトリクス基板。
3. The first and second switch elements are MO
The active matrix substrate according to claim 1, wherein the active matrix substrate is formed by an S transistor.
【請求項4】前記第1および第2のスイッチ素子を薄膜
トランジスタにより形成したことを特徴とする特許請求
の範囲第1項に記載のアクティブマトリクス基板。
4. The active matrix substrate according to claim 1, wherein the first and second switch elements are formed by thin film transistors.
JP60085242A 1985-04-19 1985-04-19 Active matrix substrate Expired - Lifetime JPH0646346B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60085242A JPH0646346B2 (en) 1985-04-19 1985-04-19 Active matrix substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60085242A JPH0646346B2 (en) 1985-04-19 1985-04-19 Active matrix substrate

Publications (2)

Publication Number Publication Date
JPS61243486A JPS61243486A (en) 1986-10-29
JPH0646346B2 true JPH0646346B2 (en) 1994-06-15

Family

ID=13853093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60085242A Expired - Lifetime JPH0646346B2 (en) 1985-04-19 1985-04-19 Active matrix substrate

Country Status (1)

Country Link
JP (1) JPH0646346B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58143377A (en) * 1982-02-22 1983-08-25 セイコーインスツルメンツ株式会社 Liquid display panel
JPS58144888A (en) * 1982-02-23 1983-08-29 セイコーインスツルメンツ株式会社 Matrix type liquid crystal display

Also Published As

Publication number Publication date
JPS61243486A (en) 1986-10-29

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