JPH0646392B2 - Data transfer device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a channel program execution control system in a data transfer device. In particular, it relates to a processing method for responding to a command repeat or command retry request from an input / output device.

[Description of Prior Art]

Conventionally, this type of processing device has a channel command word (hereinafter abbreviated as CCW) to be executed by a command repeat or command retry request that is set in advance when receiving a command repeat or command retry request from an input / output device. The channel command word from the main memory is loaded by the stored main memory address of
After exchanging and editing the optimum information necessary for executing the data transfer of this channel command word, (hereinafter, a series of processing including loading, exchanging, and editing of the above channel command word is described as "CCW fetch"). The data transfer is started by giving the information after execution of the "CCW fetch" to the data transfer unit in the channel control device and the corresponding channel.

Generally, this "CCW fetch" is performed by the microprogram in the channel controller, but this cannot be completed immediately in a short time. Especially, the main memory address in the channel command word is described by the theoretical address. , In a device having a channel DAT function for performing data transfer after conversion to an absolute address by the channel control device,
Command overrun when performing data transfer operations with a relatively high-speed I / O device such as tape, disk, or drum (command code sent from the channel to the I / O device by the mechanical speed of the I / O device This is a cause of many occurrences of data overrun (a phenomenon in which data transfer between a channel and an input / output device is too late in time).

Generally, one micro program exists in the channel control device and controls a plurality of subordinate channels. Therefore, when controlling one channel, the control request from another channel to the micro program is made to wait. However, since the "CCW fetch" is performed again by the command repeat request or the command retry request from the input / output device, the processing time of the microprogram becomes long, and the control request of another channel which is not under control is made to wait. It was a cause of increasing command overrun and data overrun of other channels.

[Object of the Invention]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned drawbacks of the prior art, in which when a data transfer designated by a channel command word is started, "CCW fetched" information is provided in a retry information area provided in a scratch pad memory in a channel controller. The purpose is to prevent command overruns and data overruns.

In particular, when a command repeat or command retry request from the input / output device is accepted, the data transfer is restarted by the information stored in the retry information area, thereby requesting the command repeat or command retry. In order to prevent command overrun and data overrun in data transfer with the channel being controlled as much as possible, in addition, the processing by microprogram command repeat or command retry request is completed in a short time. The purpose is to reduce command overruns and data overruns on other channels by starting control of other channels immediately.

[Characteristics of the Invention]

Multiple channels that can execute command repeat or command retry functions according to requests from input / output devices,
In a data transfer device comprising a channel control device for controlling this channel, storage means provided corresponding to the channel in the channel control device, and the channel control device includes at least a command code, a control flag, and a transfer byte number. When the data transfer designated by the channel command word including the main memory address information is started, the information contained in the channel command word and the absolute address information of the data area in the main memory converted from this information are stored in the storage means. And a means for restarting data transfer according to the information stored in the storage means when the channel control device receives the command repeat or command retry request from the input / output device. To do.

[Explanation of Examples]

Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a data transfer device according to an embodiment of the present invention. In this embodiment, the central processing unit 12 is provided on the output side of the main storage control unit 11 connected to the main storage unit 10.
And a channel control device (hereinafter abbreviated as CHC) 13 are connected. The channel control device 13 has an I channel for each of the plurality of channels (hereinafter abbreviated as CHU) 14.
It is composed of a plurality of input / output devices (hereinafter abbreviated as I / O) 16 connected via an I / O interface 15. The central processing unit 12 and the channel control unit 13 can access the main storage unit 10 via the main storage control unit 11, and the central processing unit 12 and the channel control unit 13 can communicate with each other via the main storage control unit 11. Is. The channel controller 13 can control a plurality of channels 14, and the channel 14 can perform a data transfer operation with a plurality of input / output devices 16 via an I / O interface 15.

FIG. 2 is a block diagram of the channel controller 13. In this channel control device 13, a channel control unit (hereinafter abbreviated as CMU) 21 and a data transfer unit (hereinafter abbreviated as CDU) 22 are connected on the output side of a memory access unit (hereinafter abbreviated as MAC) 20. The outputs of the channel control unit 21 and the data transfer unit 22 are connected to the input of a channel connection unit (hereinafter abbreviated as CPC) 23. The channel connection unit 23
A plurality of channels 14 are connected to the output of. The memory access unit 20 includes a channel control unit 21 and a data transfer unit 22.
In response to a request from the main storage device 10, the main storage device 10 is accessed and communication with the central processing unit 12 is performed. The channel control unit 21 is controlled by a microprogram and controls communication with the central processing unit 12.
It controls the execution of the channel program, decodes the request from the input / output device 16, and gives information necessary for data transfer to the data transfer unit 22 and channel 14 to instruct the operation.
The data transfer unit 22 uses the information provided from the channel control unit 21 to control the main memory controller 11 and the memory access unit 2.
0, data transfer between the main storage device 10 and the channel 14 is performed via the channel connection unit 23. The channel 14 uses the information provided by the channel controller 21 to input / output device 16
And the data transfer unit 22 and the input / output device 1 via the channel connection unit 23 and the I / O interface 15.
Data transfer between 6 is performed.

FIGS. 3 (a) and 3 (b) show the channel command word (CCW) of the channel program and this (CCW) as the main storage device 10.
The data after "CCW fetch", which has been loaded from, converted into the optimum data necessary for causing the data transfer unit 22 and the channel 14 to execute the data transfer, and edited, is shown. That is, the command code (CMD) 30 and the control flag (FLG) 31 to the command flag (CFLG) 35; the transfer byte number (BC) 32 to the transfer byte number (BC) 3
6; Transfer byte number (BC) 32 and main memory logical address 3
3 (EDA) to convert and edit the main memory absolute address (ADA) 37 and page table address (PTA) 38, respectively.

The number of pages (PGCT) 34 and the page table address (PTA) 38 in the figure are used to reconvert the main memory absolute address (ADA) 37 when the page of the main memory is updated during data transfer.

Command flag (CFLG) 35, transfer byte count (BC) 3
6 is given to the data transfer unit 22 and the channel 14, and the main memory absolute address (ADA) 37 is given to the data transfer unit 22 to serve as control information for data transfer.

The information shown in FIG. 3 (b) is the information stored in the retry information area 44 described later.

When a so-called chain command or chain data is most likely to be executed next in the execution of a channel program, the "CCW fetch" that is most likely to be executed next is performed in advance is called "CCW prefetch".

The "CCW prefetch" and "CCW fetch" are performed by the microprogram of the channel control unit 21,
The processing time becomes long, and particularly the processing time for converting the main memory logical address 33 into the main memory absolute address 37 becomes long.

FIG. 4 shows the contents of the scratch pad memory (hereinafter abbreviated as SPM) 21a built in the channel controller 21.
This scratch pad memory (SPM) is composed of a channel (CH) area 40 corresponding to each channel and a common area 41. This channel (CH) area 40 corresponds to the maximum number of channels 14 connectable to the channel controller 13 (24 channels). Min) prepared. Each channel area 40 is composed of a control information area 42, a prefetch information area 43, and a retry information area 44 as shown in the enlarged view on the right side. The control information area 42 stores information necessary for controlling the channel corresponding to the microprogram, and the prefetch information area 43 includes “CCW prefetch” and “CCW fetch”.
Later information is stored.

The retry information area 44 is one of the features of the present invention, and stores information after "CCW fetch" required by the input / output device 16 for command repeat or command retry request.

FIG. 5 shows that the microprogram in the channel control unit 21 uses the information after the "CCW prefetch" or "CCW fetch" in the prefetch information area 43 to transfer the data to the data transfer unit 22,
7 is a flowchart of a routine for instructing data transfer to the channel 14, and by storing all the contents of the prefetch information area 43 in the retry information area 44 after the instruction is completed, it is necessary for a command repeat or command retry request from the input / output device 16. Store and put information that becomes.

FIG. 6 shows a command repeat in which the microprogram in the channel controller 21 decodes the request code from the input / output device 16 and requests the repetition of the same channel command word.
Command retry requesting the retry of the same channel command word (Both command repeat and command retry are requested at the input / output device while the channel command word chained in the chain data is being executed. It is a flowchart for performing processing for checking whether it is a request and responding when it is the request. If it is a command repeat or command retry request, "CCW fetch" again
The data transfer unit 22 and the channel 14 are instructed to transfer data based on the contents of the retry information area 44 without performing any processing.

Here, the reason for restarting from the first channel command word of the chain data when a command repeat or command retry request is accepted during execution of a channel command word chained by chain data will be described.

A plurality of channel command words chained by the chain data are equivalent to one channel command word when viewed from the input / output device. Chain data uses the command in the first channel command word of the chain data, and the area of multiple main memory specified in the multiple channel command words chained by the chain data that includes this first channel command word. This is a function to transfer data between the input and output devices. In both the command repeat and the command retry, the input / output device receives the command corresponding to the data transfer currently being executed from the channel again and re-executes it, so that the channel command word at the beginning of the chain data is naturally restarted.

The minimum required to execute command repeat or command retry is the address of the channel command word being executed if it is not chained with chain data, or the channel command at the beginning of chain data if it is chained with chain data. Is the address of a word.
When a command repeat or command retry request is received from the I / O device, the channel information word at the beginning of the data transfer is restarted.
The data transfer unit 22 and the channel 14 are instructed to transfer data according to the contents of No. 4, but the second and subsequent channel command words are the addresses of the channel command words held in the same manner as in normal execution. Is fetched from the main memory, the logical address in the channel command word is converted into an absolute address, and the data is transferred.
However, for the second and subsequent channel command words, that channel command word can be fetched before it is actually needed, and the logical address in the channel command word can be converted and placed as an absolute address, so command overrun, data over Runs can be reduced.

Search-type commands are equivalent to write-type commands when viewed from the channel controller. Regarding command repeat and command retry, search commands are executed in the same manner as write commands.

The TIC command is invisible to the I / O device. The channel controller performs an unconditional branch of the channel program by the TIC command, and continues the channel program by the channel command word of the branch destination. Therefore, since the input / output device does not request the command repeat and the command retry for the TIC command, no special consideration is required.

[Explanation of effects]

As described above, according to the present invention, the scratch pad memory of the channel controller holds the information contained in the channel command necessary for channel control and the absolute address information of the data area in the main memory converted from this information. Therefore, data can be transferred in response to a command repeat or command retry request from the input / output device, the processing time of the microprogram can be shortened, and the command overrun and the data overrun can be easily reduced in the channel control device. There is.

[Brief description of drawings]

FIG. 1 is a system configuration block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram of the channel control device. FIG. 3 (a) is a channel command word format diagram. FIG. 3 (b) is a data format diagram after the completion of the channel command word fetch. FIG. 4 is a format diagram of a scratch pad memory (SPM) in the channel controller. FIG. 5 is a flow chart when the microprogram stores information in the retry information area. FIG. 6 is a flowchart of a process in which the microprogram responds to a command repeat or command retry request from the input / output device. 10 ... Main memory unit (MEM), 11 ... Main memory control unit (MCU), 12 ... Central processing unit (CPU), 13
...... Channel control unit (CHC), 14 ...... Channel (CHU), 15 ...... I / O interface, 16 ......
Input / output device (I / O), 20 ... Memory access unit (M
AC), 21 ... Channel control unit (CMU), 21a ...
... Scratch pad memory (SPM), 22 ... Data transfer unit (CDU), 23 ... Channel connection unit (CP)
C), 30 ... Command code, 31 ... Control flag, 32
...... Number of transfer bytes, 33 …… Main memory logical address, 34
...... Page number, 35 ...... Command flag, 36 ...... Transfer byte number, 37 ...... Main memory absolute address, 38 ...... Page table address, 40 ...... Channel (CH) area, 4
1 ... common area, 42 ... control information area, 43 ...
Pre-take information area, 44 ... Retry information area.

Continuation of the front page (56) Reference JP-A-58-40644 (JP, A) JP-A-54-51741 (JP, A) JP-A-51-23044 (JP, A) JP-A-48-20446 (JP , A) JP-A-54-133852 (JP, A) JP-A-55-124826 (JP, A) Masami Yamatani, "Introduction to Virtual Computer System for Illustrated Computer Series", Ohmsha, October 10, 1978. Issued, PP. 97-100

Claims (1)

[Claims] 1. A data transfer device comprising a plurality of channels for executing a command repeat or command retry request from an input / output device, and a channel control device for controlling the channels, wherein the channel is provided in the channel control device. Storage means provided corresponding to the channel control device, when the channel control device starts data transfer specified by a channel command word including at least a command code, a control flag, a transfer byte number and main memory address information, the channel Means for storing in the storage means the information contained in the command word and the absolute address information of the data area in the main memory converted from this information; and the channel controller requesting the command repeat or command retry from the input / output device. When it is accepted, it is stored in the storage means. And a means for resuming data transfer according to information.