JPH0646515B2 - Sense amplifier circuit - Google Patents

Description

The present invention relates to a sense amplifier circuit suitable for a memory circuit composed of MISFETs.

[Prior art]

In the dynamic memory circuit by MOSFET,
A circuit based on a flip-flop circuit is usually used as a so-called sense amplifier circuit for amplifying a minute potential difference read from a memory cell. An example of such a circuit is shown in FIG. 2 (for example, Nikkei Electronics 1
Pp. 110-133, Jan. 8, 979).

In the sense amplifier circuit shown in FIG. 2, the clock terminal 19 and the clock terminal 2 are provided immediately before the amplification operation.
Due to the potentials of the clock 1 and the clock 2 applied to 0, the MOSFET 3 is in the cutoff state.
And 5 are conductive. Therefore, the potentials of the input 1 and the input 2 applied to the input terminals 15 and 16 are transmitted to the output terminals 17 and 18 as the output 1 and the output 2, respectively, and the stray capacitances existing at the output terminals 17 and 18 are charged to the input potential. ing.

At the time of amplification, first, the potential of the clock terminal 20 is changed to cut off the MOSFETs 4 and 5. Next, the potential of the clock terminal 19 is changed to make the MOSFET 3 conductive. This causes MOFSET1 and 2 to form a flip-flop circuit, and the positive feedback action causes the output terminals 17 and 1
Of the eight, the terminal closer to the potential VSS of the power source 21 immediately before the amplifying operation is discharged to the potential VSS, and the potential of the other output terminal hardly changes, and as a result, it is applied to the input terminals 15 and 16. Output terminal 1
You get 7 and 18.

[Problems of conventional technology]

In the amplification operation of the sense amplifier circuit described above, since the output terminals 17 and 18 are charged in the floating capacitance, the potential cannot change rapidly, and it takes a certain amount of time. Therefore, if the potential of the connection point 22 is suddenly changed, the MOSF
Since both ET1 and ET2 become conductive, correct amplification operation cannot be expected. In order to explain this in detail, the potential VS applied to the input terminal 15 is higher than the potential VS applied to the input terminal 16 than the potential VS of the power supply 21.
Suppose it is close to S. In this state, the MOSFETs 4 and 5 are cut off, the MOSFET 3 is made conductive, and the potential at the connection point 22 is gradually increased.
When it approaches VSS, first MOSFET 1 becomes conductive.
As a result, even if the potential of the output terminal 17 approaches VSS and the potential of the connection point 22 approaches VSS, the MOSFET 2 is kept in the cutoff state. In this way output terminal 1
Only the potential of 7 reaches VSS. However, connection point 2
If the potential of 2 is changed faster than the change of the potential of the output terminal 17, the gate-source voltage of the MOSFET 2 becomes higher than the threshold voltage of the MOSFET 2 and the MOSFET 2 becomes conductive. Then, the potential of the output terminal 18 also changes toward VSS. Therefore, correct amplification operation cannot be expected.

As described above, in order for the sense amplifier circuit shown in FIG. 2 to operate properly, the voltage waveform applied to the clock terminal 19 must be adjusted so that the potential at the connection point 22 changes sufficiently slowly. Further, the change in the potentials of the output terminals 17 and 18 is slower as the stray capacitance is larger, so that the potential of the connection point 22 must be changed slowly.

In general, it is desirable that the time required for amplification is short, and for that purpose it is necessary to reduce the stray capacitance of the output terminals 17 and 18. However, in the holding state after amplification, if the stray capacitances of the output terminals 17 and 18 are too small,
Even if a slight amount of current noise is added to this terminal, the potential of the terminal changes greatly. As a result, M that was in the conducting state
If the OSFET 1 is cut off, the stored contents will be destroyed.

As described above, in the conventional sense amplifier circuit, the stray capacitance of the output terminal must be reduced in order to speed up the amplification operation, but if it is too small, the resistance to noise in the holding state becomes weak. Therefore, there is a problem in that the size cannot be reduced so much, and thus a sufficient speedup cannot be achieved.

[Object of the Invention]

In view of this point, it is an object of the present invention to provide a sense amplifier circuit which does not reduce the resistance to noise in the holding state even when the amplification operation is speeded up.

[Structure of Invention]

In order to achieve the above object, the present invention provides a first output terminal connected to a first input terminal through a first MISFET having a gate electrode connected to a first clock terminal, and a gate electrode. The second MI connected to the first clock terminal
A second output terminal connected to a second input terminal via an SFET, a drain electrode connected to the first output terminal, a source electrode connected to a connection point, and a gate electrode connected to the second output terminal.
And a drain electrode connected to the second output terminal, a source electrode connected to the connection point, and a gate electrode connected to the first output terminal. In a sense amplifier circuit comprising a MISFET and a first power supply connected to the connection point via a fifth MISFET having a gate electrode connected to the second clock terminal, the first and second output terminals are provided. First and second two-terminal load elements respectively connected to a second power source, a drain electrode connected to the drain electrode of the third MISFET, and a source electrode connected to the third M
Sixth, in which the gate electrode is connected to the source electrode of the ISFET and is connected to the second output terminal via a first resistor
MISFET and the drain electrode are the fourth MISF
A seventh MISFET having a source electrode connected to the drain electrode of ET, a source electrode connected to the source electrode of the fourth MISFET, and a gate electrode connected to the first output terminal via a second resistor; and a drain The electrode is the sixth M
An eighth MISFET connected to the gate electrode of the ISFET, a source electrode connected to the first power source, and a gate electrode connected to a third clock terminal, and a drain electrode connected to the gate electrode of the seventh MISFET. A ninth MISFET having a connected source electrode connected to the first power supply and a gate electrode connected to the third clock terminal is provided.

〔Example〕

 An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, elements having the same functions as those of FIG. 2 are designated by the same reference numerals. The drain electrode of one MOSFET 1 forming the flip-flop circuit is connected to the output terminal 17, and the gate electrode thereof is the output terminal 18.
, And the source electrode is connected to the connection point 22. The other MOSFE forming the flip-flop circuit
The drain electrode of T2 is connected to the output terminal 18, the gate electrode is connected to the output terminal 17, and the source electrode is connected to the connection point 2
Connected to 2. The connection point 22 is connected to the drain electrode of the MOSFET 3, the gate electrode of the MOSFET 3 is connected to the clock terminal 19, and the source electrode is connected to the power supply 21. The output terminal 17 is connected to the source electrode of the MOSFET 4, the drain electrode of the MOSFET 4 is connected to the input terminal 15, and the gate electrode is the clock terminal 2
It is connected to 0. The output terminal 18 is the MOSFET 5
Of the MOSFET 5, the drain electrode of the MOSFET 5 is connected to the input terminal 16, and the gate electrode is connected to the clock terminal 20.

The above configuration is the same as the configuration of the sense amplifier circuit shown in FIG. The sense amplifier circuit of the present embodiment further includes the following circuits. Output terminals 17 and 1
8 acting as a two-terminal load element between the power source 25 and the power source 25
The OSFETs 11 and 12 are connected with the source electrode on the output terminal side and the drain electrode on the power source side.
The gate electrodes of the OSFETs are connected to the power supply 25, respectively. The drain electrode of the MOSFET 6 is the output terminal 17
, The source electrode is connected to the connection point 22, and the gate electrode is connected to the connection point 23. MOSFET 7
Is connected to the output terminal 18, the source electrode is connected to the connection point 22, and the gate electrode is connected to the connection point 24. Between the output terminal 18 and the connection point 23,
A resistor 13 that functions as a two-terminal load element is connected, and a resistor 14 that functions as a two-terminal load element is connected between the output terminal 17 and the connection point 24. Connection point 23 is MOSF
It is connected to the drain electrode of ET8, the source electrode of MOSFET8 is connected to the power supply 21, and the gate electrode is connected to the clock terminal 26. Connection point 24 is a MOSFET
9 is connected to the drain electrode, the source electrode of the MOSFET 9 is connected to the power supply 21, and the gate electrode is connected to the clock terminal 26.

Next, the operation of this embodiment will be described. Immediately before starting the amplification, M is set by the potentials of the clock 1 and the clock 2 applied to the clock terminals 19 and 20.
OSFET3 is cut off, and MOSFETs 4 and 5 are conductive. The potentials of the clock 3 applied to the clock terminal 26 make the MOSFETs 8 and 9 conductive, and as a result, the MOSFETs 6 and 7 are cut off. MOSFE
T6 and 7 are transistors having a large area, and the stray capacitances at the connection points 23 and 24 are considerably large due to their gate capacitances, and therefore these stray capacitances are charged to the potential VSS of the power supply 21. MOSFET 11 acting as a two-terminal load element,
The resistance values of 12 and resistors 13 and 14 are sufficiently high, and the potentials of output terminals 17 and 18 are substantially equal to the potentials of input terminals 15 and 16, respectively. When an input cannot be applied to the input terminals 15 and 16 with a sufficiently low DC resistance as in the case of a normal dynamic memory, the MOSFETs 4 and 5 are cut off during non-operation and immediately before the amplification operation.
It is possible to satisfy this condition by conducting.

During the amplifying operation, the potentials of the clock terminal 20 and the clock terminal 26 are changed to change the MOSFETs 4 and 5 and the MO.
Turn off SFETs 8 and 9. After that, clock terminal 1
The potential of 9 is changed to make MOSFET 3 conductive. As described above, the MOSFETs 6 and 7 are transistors having a large area, the stray capacitances at the connection points 23 and 24 are considerably large due to the gate capacitances thereof, and the resistance values of the resistors 13 and 14 are very large. Therefore, even if the potentials of the output terminals 17 and 18 change, the potential VSS of the connection points 23 and 24 is hardly affected in a short time. Therefore, during the amplifying operation, the MOSFETs 6 and 7 remain cut off and do not affect the amplifying operation. Also MOSFETs 11 and 12
Since the resistance values of the resistors 13 and 14 are sufficiently high, it takes a certain amount of time to change the potentials of the output terminals 17 and 18 through them, so that the amplification operation in a short time is hardly affected. Therefore, first output terminals 17 and 18
The existing potential difference is amplified in the same manner as in the case of the sense amplifier circuit of FIG. During the short-time amplification operation, the resistance values of the resistors 13 and 14 are large, so that the stray capacitances of the connection points 23 and 24 have no effect, and only the stray capacitances of the output terminals 17 and 18 are exerted during the amplification operation. Will be involved. Therefore, a high-speed amplification operation can be performed by reducing the stray capacitance. The potential of one output terminal after amplification is the potential VSS of the power supply 21, but the potential of the other output terminal becomes a constant potential determined by the load elements 11 and 12 in this embodiment. As shown in FIG. 1, these load elements have an enhancement type M.
When the OSFET is used, the potential of the other output terminal is VDD− if the threshold voltage of the MOSFETs 11 and 12 is VT.
It becomes VT. However, VDD is the potential of the power supply 25.

In the holding state, for the sake of explanation, it is assumed that MOSFET 1 is in a conducting state and MOSFET 2 is in a blocking state, and after amplification,
Assume that the potentials of the output terminals 17 and 18 are VSS and VDD-VT, respectively. As described above, since the potentials at the connection points 23 and 24 are held at VSS by the floating capacitance,
FET7 remains cut off, but MOSFET6
Current flows into the stray capacitance at the connection point 23 through the resistor 13, and after a sufficient time elapses, the potential at the connection point 23 becomes VDD-VT, which is the same as the output terminal 18, and the MOSFET 6 becomes conductive. When the potentials of the output terminals 17 and 18 are opposite to each other, on the contrary, the MOSFET 6 remains in the cutoff state.
Conducts. In this state, even if the potentials of the output terminals 17 and 18 change due to noise, the circuit states do not change due to the functions of the MOSFETs 6 and 7. For example, when MOSFET 1 is in the conductive state and MOSFET 2 is in the cutoff state,
If the potential of the output terminal 17 rises due to noise, M
The gate-source voltage of OSFET2 increases, the potential of output terminal 18 decreases, and the gate of MOSFET1
The voltage between sources becomes small. As mentioned above, MOSFE
Since T6 is in the conductive state, the gate-source voltage of MOSFET1 is prevented from falling below the threshold voltage of MOSFET1 and MOSFET1 is not cut off. Therefore, since the state of the circuit does not change, the stored contents are not destroyed. Further, since the potentials of the connection points 24 and 23 are respectively the potential VSS of the output terminal 17 and the potential VDD-VT of the output terminal 18, the connection points 23 and 2 are
The large stray capacitance of No. 4 becomes effective, and even if current noise is applied to the output terminals 17 and 18, the change in the potential is suppressed, so that the influence on the circuit state is reduced and the output terminals 17 and 18 are also affected. The changed potential also quickly returns to the original potential.

As described above, according to the sense amplifier circuit of the present embodiment, only the stray capacitances of the output terminals 17 and 18 are involved in the amplifying operation, and high speed operation can be obtained by reducing the stray capacitance. On the other hand, in the holding state, the large stray capacitances at the connection points 23 and 24 have an effect, and thus are strong against noise.

Although the source electrodes of the MOSFETs 8 and 9 are connected to the power supply 21 in this embodiment, they may be connected to the connection point 22. In this case, immediately before the start of the amplification operation, the MOSFETs 3, 8 and 9 are rendered conductive by the potential applied to the clock terminal 19 and the clock terminal 26, and the connection points 23 and 24 are charged to the potential VSS of the power supply 21. It will be. The subsequent operation is similar to that of the above-described embodiment, and the same effect can be obtained.

In the above embodiments, the case where the MOSFET is used as the MISFET has been described, but it goes without saying that other MISFETs can also be used.

〔The invention's effect〕

As described above, according to the present invention, it is possible to obtain a sense amplifier circuit that is suitable for use in a MIS integrated circuit such as a dynamic memory and that has both high-speed operation and noise resistance.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional sense amplifier circuit. 1,2,3,4,5,6,7,8,9,11,12 ...
MOSFET 13, 14 ... Resistor 15, 16 ... Input terminal 17, 18 ... Output terminal 19, 20, 26 ... Clock terminal 21, 25 ... Power supply

Claims (1)

[Claims] 1. A first output terminal connected to a first input terminal through a first MISFET having a gate electrode connected to a first clock terminal, and a gate electrode connected to the first clock terminal. A second output terminal connected to a second input terminal via the second MISFET, a drain electrode connected to the first output terminal, a source electrode connected to a connection point, and a gate electrode connected to the second electrode. And a drain electrode connected to the second output terminal, a source electrode connected to the connection point, and a gate electrode connected to the first output terminal. MISF
ET and a first MISFET connected to the connection point via a fifth MISFET having a gate electrode connected to the second clock terminal
The sense amplifier circuit including the power supply of
And first and second two-terminal load elements connected between the second output terminal and the second power source, respectively, and a drain electrode connected to the drain electrode of the third MISFET and a source electrode of the third MISFET. A gate electrode connected to the source electrode of a third MISFET and having a gate electrode connected to the second electrode via a first resistor.
A MISFET connected to the output terminal of the second MISFET, a drain electrode connected to the drain electrode of the fourth MISFET, a source electrode connected to the source electrode of the fourth MISFET, and a gate electrode connected to the second resistor. A seventh MISFET connected to the first output terminal via
An eighth MI having a drain electrode connected to the gate electrode of the sixth MISFET, a source electrode connected to the first power supply, and a gate electrode connected to a third clock terminal.
An SFET and a ninth MISFET having a drain electrode connected to the gate electrode of the seventh MISFET, a source electrode connected to the first power supply and a gate electrode connected to the third clock terminal are provided. A sense amplifier circuit characterized in that