JPH0646672B2 - Circuit board manufacturing method - Google Patents
Circuit board manufacturing methodInfo
- Publication number
- JPH0646672B2 JPH0646672B2 JP12055785A JP12055785A JPH0646672B2 JP H0646672 B2 JPH0646672 B2 JP H0646672B2 JP 12055785 A JP12055785 A JP 12055785A JP 12055785 A JP12055785 A JP 12055785A JP H0646672 B2 JPH0646672 B2 JP H0646672B2
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- Prior art keywords
- circuit
- circuit board
- plating
- nib
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は回路の高密化に伴って要求される高品質、か
つ作業能率に優れた回路基板の製造方法に関するもので
ある。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a circuit board which is required to have a high density circuit and has high quality and excellent work efficiency.
一般に、プリント回路基板を得るに際しCu箔を基板に
貼り合わせたクラツド板にレジスト印刷・エツチングを
施し所望の回路パターンを得て、必要に応じてこれらを
多層に積層する方法が知られている。しかし、この所謂
サブトラクテイブ法は多段な行程を要し、かつ多量のC
uをエツチングするためコスト高をまねくばかりでな
く、0.1〜0.25mm巾の微細回路を形成する際には
不向きな方法とされている。In general, there is known a method of obtaining a desired circuit pattern by performing resist printing / etching on a cladding plate obtained by bonding a Cu foil to a substrate when obtaining a printed circuit board, and laminating these in multiple layers as necessary. However, this so-called subtractive method requires many steps and a large amount of C
This is not suitable for forming a fine circuit having a width of 0.1 to 0.25 mm, as well as increasing the cost due to etching u.
これに対し、Pd触媒化された特殊基板を用い、レジス
ト処理後にCu化学メツキして、一挙に所望パターンを
形成できる所謂アデイテイブ法が普及しつつある。この
方法は工程が単純であると同時に、従来法でみられたサ
イドエツチング等の問題がなく、微細な回路パターンの
形成には特に有利とされている。On the other hand, a so-called additive method is becoming popular in which a Pd-catalyzed special substrate is used to chemically form Cu after resist treatment to form a desired pattern at once. This method has a simple process, and at the same time, has no problems such as side etching, which are observed in the conventional method, and is particularly advantageous for forming a fine circuit pattern.
電子部品の小型・高密化及び機器、回路の高密・高性能
化に伴って、回路基板の高密化、微細パターン化に対す
る要求は、近年益々強くなっている。In recent years, the demand for higher density and finer patterning of circuit boards has become stronger as electronic components become smaller and more dense and equipment and circuits have higher density and higher performance.
前記アデイテイブ法はこれらの要求に応えるものではあ
るが、特殊基板を用いるためコスト高となるばかりでな
く、電気的特性(絶縁性)にも問題点が指摘されてい
る。即ち該方法においては、部品を搭載したり、外部回
路との接続等に半田付工程を必要とし、かつ回路の修
理、特殊部品の搭載等では手半田作業が不可欠とされて
いる。このため、Cu回路の半田食われ現象が起こり、
Cuが半田に溶解消失し、はなはだしい場合は基板が露
出してしまう。このような現象を防止するため、電気的
特性からは明らかに過剰な厚いCu(例えば、35μ)
が化学メツキされる。かかるメツキ行程には20〜30
時間の長時間を要し、コスト高となるばかりでなく、基
板がメツキ液に長時間さらされる結果、溶出、吸収、膨
潤等が併発して基板の劣化をまねき易い。更には、メツ
キ行程中に細い回路間隙に異常析出するCuがシヨート
欠陥を生じ易く、回路の微細化要求には反することとな
る。Although the additive method meets these requirements, it is pointed out that not only the cost increases due to the use of a special substrate, but also the electrical characteristics (insulating property). That is, in this method, a soldering process is required for mounting components, connecting to an external circuit, and the like, and manual soldering work is indispensable for repairing circuits, mounting special components, and the like. As a result, the solder erosion phenomenon of the Cu circuit occurs,
Cu dissolves and disappears in the solder, and in the extreme case, the substrate is exposed. In order to prevent such a phenomenon, it is apparently thick Cu (eg, 35 μ) that is excessive from the electrical characteristics.
Is chemically damaged. 20 to 30 for such a mating process
Not only does it take a long time and the cost is high, but as a result of the substrate being exposed to the plating solution for a long period of time, elution, absorption, swelling, etc. occur at the same time and the substrate is likely to deteriorate. Further, Cu which is abnormally deposited in a narrow circuit gap during the plating process easily causes a short defect, which is against the demand for circuit miniaturization.
従って、予め触媒化された特殊基板を必要とせず、より
安価な普通基板に能率良く高密度な回路を直接形成する
ことが望まれる。又、回路基板で不可避的に問題となる
半田食われのないこと、及び長期間の熱的機械的ストレ
スに耐える強固な接着力も必要となる。特に半田食われ
は、電子部品の高密実装に理想的な面実装において、解
決すべき重要課題となっている。Therefore, it is desired to directly form an efficient and high-density circuit on a cheaper ordinary substrate without requiring a special substrate that has been catalyzed in advance. Further, it is necessary that the circuit board is free from solder erosion, which is inevitably a problem, and that the circuit board has a strong adhesive force to withstand a long-term thermal mechanical stress. In particular, solder erosion is an important issue to be solved in surface mounting, which is ideal for high-density mounting of electronic components.
本発明は、上記の現況に鑑みて為されたものである。即
ち、任意の絶縁性基板上にCuレジンペーストを印刷し
て所望の回路を形成してから、NiB化学メツキ、Cu
化学メツキを順次施して導電回路を形成することを特徴
とするものである。The present invention has been made in view of the above situation. That is, after printing a Cu resin paste on an arbitrary insulating substrate to form a desired circuit, NiB chemical plating, Cu
It is characterized in that a conductive circuit is formed by sequentially performing chemical plating.
本発明において、NiB化学メツキはジメチルアミンボ
ラン、水素化ホウ素酸ナトリウム等のボラン系還元剤を
用い、NiSO4等のNi2+演、錯化剤、pH調整剤、
安定化剤等が配合されたメツキ浴で、通常1〜5μの厚
さに施される。Cuメツキはホルマリン等を還元剤と
し、CuSO4等のCu2+塩、EDTA等のキレート
剤、pH調整剤、CN-化物或いはS化合物等の安定化剤
等が配合されたメツキ浴で、通常5〜15μの厚さに施
される。Cuレジンペーストは、Cu又はCu合金粉と
フエノール、エポキシ、ポリイミド、変性フエノキシ等
のレジンのほかにブチルカルビノール等の溶剤、粘度調
整剤、安定化剤等が配合され、Cu又はCu合金粉とレジ
ンの配合比は、Cu又はCu合金粉60〜95重量%が用
いられる。ペーストはスクリーン印刷された後、100
〜250℃の温度で硬化される。In the present invention, the NiB chemical plating uses a borane-based reducing agent such as dimethylamine borane and sodium borohydride, and Ni 2+ such as NiSO 4 , a complexing agent, a pH adjusting agent,
It is a plating bath containing a stabilizer and the like and is usually applied to a thickness of 1 to 5 μm. Cu plating is a plating bath usually containing formalin or the like as a reducing agent and a Cu 2+ salt such as CuSO 4 or the like, a chelating agent such as EDTA, a pH adjusting agent, a CN - compound or a stabilizer such as an S compound, and the like. It is applied to a thickness of 5 to 15 μ. The Cu resin paste contains Cu or Cu alloy powder and a resin such as phenol, epoxy, polyimide, modified phenoxy, etc., as well as a solvent such as butyl carbinol, a viscosity modifier, a stabilizer, etc. The compounding ratio of the resin is 60 to 95% by weight of Cu or Cu alloy powder. After the paste is screen printed, 100
Cured at a temperature of ~ 250 ° C.
本発明において、Cuレジンペーストはシート抵抗にし
て5〜100mΩ/□位の導電性を有すると共に、Ni
B化学メツキに対する触媒作用も発揮する。しかしCu
レジンペースト中のCu又はCu合金粉の比が60%に
満たないときは上記効果に乏しく、他方95%を越える
ときはペースト部の強度が低下し、いずれも実用的では
ない。In the present invention, the Cu resin paste has a sheet resistance of about 5 to 100 mΩ / □ and has a Ni content of about 5 to 100 mΩ / □.
It also exerts a catalytic action for B chemical plating. But Cu
When the ratio of Cu or Cu alloy powder in the resin paste is less than 60%, the above effect is poor, and when it exceeds 95%, the strength of the paste portion decreases, and neither is practical.
NiBは通常B分が0.1〜10%の合金メツキのとき、
Pd触媒を要せずCuペースト上に直接メツキできる。
従ってNiBメツキは、基板をPdCl2浴等で触媒化したと
き、絶縁部に吸着し易いPdが誘発するCuの異常析出
を未然に防ぐこととなる。更にNiBは密着力、機械的
強度に優れ、又耐食的であるため酸化し難く、後述の半
田性に優れ、かつ半田食われを起こさない。しかしNi
Bメツキの厚さが1μ未満では上記効果の乏しいので1
μ以上、実用上は1〜5μとすることが望ましい。NiB is usually alloyed with B content of 0.1-10%,
It can be directly plated on Cu paste without the need for Pd catalyst.
Therefore, the NiB plating prevents the abnormal deposition of Cu induced by Pd which is easily adsorbed to the insulating portion when the substrate is catalyzed by a PdCl 2 bath or the like. Further, NiB has excellent adhesion and mechanical strength, and is resistant to corrosion because it is resistant to oxidation, has excellent solderability described below, and does not cause solder erosion. But Ni
If the thickness of B plating is less than 1 μ, the above effect is poor.
It is desirable that the thickness be equal to or larger than μ, and practically 1 to 5 μ.
NiBメツキを併用するため、Cuメツキの厚さは導電
性を主条件に決定でき、実用上は5〜15μ程度が望まし
い。本発明方法ではCuメツキ厚を薄くしても、半田食
われによる絶縁層の露出は全く起こらない。この理由は
耐熱性の高いNiはCuと比べ半田への溶解速度が1/10
以下と低い故である。又メツキ作業時間も従来の半分以
下に短縮することが可能となるが、これはメツキ速度の
相違、即ちCuの1〜5μ/hrに対しNiBは5〜1
5μ/hrと速いことに基因する。更にCuメツキ厚が薄
いことから、前述のCu異常析出の危険度も加速的に減
少し、信頼性の高い微細回路の形成が可能となった。Since the NiB plating is used in combination, the thickness of the Cu plating can be determined mainly on the basis of the conductivity, and in practical use, it is preferably about 5 to 15 μm. In the method of the present invention, even if the thickness of the Cu plating is reduced, the insulating layer is not exposed due to solder erosion. The reason for this is that Ni, which has high heat resistance, has a dissolution rate of 1/10 in solder compared to Cu.
This is because it is low as below. Also, the plating work time can be shortened to less than half of the conventional one, but this is due to the difference in the plating speed, that is, 1 to 5 μ / hr for Cu and 5 to 1 for NiB.
This is due to the high speed of 5 μ / hr. Further, since the thickness of Cu plating is thin, the risk of abnormal Cu precipitation is reduced at an accelerating rate, and it becomes possible to form a highly reliable fine circuit.
本発明方法で得られる回路基板の一つの特徴は、部品、
特に半導体素子を直接搭載する際のワイヤーボンド性に
極めて優れている点である。即ち、従来のアデイテイブ
法で製造した基板ではCu層の下にゴム状接着層を置く
ため、超音波ボンドのエネルギーが吸収されて有効にボ
ンドに使われない。従ってCu層は可及的に厚くする必
要があった。これに対し本発明方法で得られるものは、
硬質なCuペーストとNiB層を有するため、Cu層が
薄くともボンデイングキヤピラリーを通して加えられる
超音波エネルギーは回路表面とボンデイングワイヤー間
に集中して効率的に使われ、高速度で確実なボンドが容
易に実現される。One feature of the circuit board obtained by the method of the present invention is a component,
In particular, it is extremely excellent in wire bondability when directly mounting a semiconductor element. That is, in the substrate manufactured by the conventional additive method, since the rubber-like adhesive layer is placed under the Cu layer, the energy of the ultrasonic bond is absorbed and it is not effectively used for bonding. Therefore, it was necessary to make the Cu layer as thick as possible. On the other hand, what is obtained by the method of the present invention is
Since it has a hard Cu paste and NiB layer, even if the Cu layer is thin, ultrasonic energy applied through the bonding capillary is concentrated between the circuit surface and the bonding wire and is used efficiently, facilitating reliable bonding at high speed. Will be realized.
以上、本発明は一層回路基板について説明したが、両面
回路基板或いはこれらを積層した多層回路基板の製造に
も応用可能である。この場合、スルーホールの代りにC
uレジンペーストでドリル穴を埋めることにより能率的
に導通を形成できる。又、一層回路上にCuレジンペー
ストを用いてスルースタツドを立て絶縁層を印刷してか
ら、全く同様にして第2層回路を形成できる。更に、従
来のサブトラクテイブ法により製造した回路基板上に本
発明方法を応用して多層化することもできる。Although the present invention has been described with reference to the single-layer circuit board, it can be applied to the production of a double-sided circuit board or a multilayer circuit board in which these are laminated. In this case, C instead of through hole
Conductivity can be efficiently formed by filling the drill holes with u resin paste. Further, the second layer circuit can be formed in exactly the same manner after forming a through-stud with a Cu resin paste on the one-layer circuit and printing an insulating layer. Further, the method of the present invention can be applied to form a multi-layer on a circuit board manufactured by a conventional subtractive method.
1)実施例1、比較例1〜5 Al板(厚さ1.5mm)の片面をポリイミド塗膜(厚さ
約50μ)で絶縁して基板とした。平均粒径9μの球状
Cu粉80重量%とフエノールレジン20重量%に少量
のブチルカルビノールアセテートを配合したCuレジン
ペーストを用いて回路をスクリーン印刷した。最小回路
巾を0.15mm、回路間隔を0.2mmとし、210℃、
15分間加熱して硬化した。この回路基板を10%HC
l中に10分間浸漬しその表面を洗浄後、ナイクラツド
741浴(奥野製薬社製)(65℃、pH7.1)に1
5分間浸漬して、約3.5μ厚のNiB(B分約0.9
%)メツキをした。次に、ELC−HS浴(上村工業社
製)(65℃)に2時間浸漬して、約8μ厚のCuメツ
キをした。これを実施例1とする。1) Example 1, Comparative Examples 1 to 5 One side of an Al plate (thickness: 1.5 mm) was insulated with a polyimide coating film (thickness: about 50 μm) to obtain a substrate. A circuit was screen-printed using a Cu resin paste prepared by mixing 80% by weight of spherical Cu powder having an average particle diameter of 9μ and 20% by weight of phenol resin with a small amount of butylcarbinol acetate. The minimum circuit width is 0.15 mm, the circuit interval is 0.2 mm, 210 ° C,
It was cured by heating for 15 minutes. This circuit board is 10% HC
After immersing in l for 10 minutes and washing the surface, it was immersed in a bath of Niclad 741 (Okuno Pharmaceutical Co., Ltd.) (65 ° C., pH 7.1).
Immerse for 5 minutes, and about 3.5μ thick NiB (B content about 0.9
%) I made a woodpecker. Next, it was immersed in an ELC-HS bath (manufactured by Uemura Kogyo Co., Ltd.) (65 ° C.) for 2 hours to make Cu plating having a thickness of about 8 μm. This is Example 1.
比較例1 実施例1において、NiBメツキを欠いてCuメツキし
た。Comparative Example 1 In Example 1, Cu plating was performed without NiB plating.
比較例2 比較例1において、Cuメツキを8時間行い約30μの
Cuメツキ厚とした。Comparative Example 2 In Comparative Example 1, Cu plating was performed for 8 hours to obtain a Cu plating thickness of about 30 μ.
比較例3 実施例1において、NiBメツキ浴の代りにNiPメツ
キ浴を用いたが、全くNiを析出しなかった。そこで、
PdCl20.1g/水溶液に30秒間浸漬してから水洗
し、その後NiPメツキ浴、Cuメツキ浴に浸漬し、実
施例1と同様にメツキをした。Comparative Example 3 In Example 1, a NiP plating bath was used instead of the NiB plating bath, but no Ni was deposited. Therefore,
It was dipped in 0.1 g of PdCl 2 / water solution for 30 seconds, washed with water, and then dipped in a NiP plating bath and a Cu plating bath, and plated as in Example 1.
比較例4 以下の特性比較を行うため、市販のサブトラクテイブ法
回路基板を用いた。該基板の最小回路巾は0.35mm、
回路間隔は0.40mmであり、Cu箔の厚さは35μで
あった。Comparative Example 4 In order to perform the following characteristic comparison, a commercially available subtractive method circuit board was used. The minimum circuit width of the board is 0.35 mm,
The circuit spacing was 0.40 mm and the Cu foil thickness was 35 μ.
比較例5 同様に、市販アデイテイブ法回路基板を用いた。該基板
の最小回路巾は0.2mm、回路間隔は0.25mmであ
り、Cuメツキ厚は35μであった。Comparative Example 5 Similarly, a commercially available additive circuit board was used. The minimum circuit width of the substrate was 0.2 mm, the circuit interval was 0.25 mm, and the Cu plating thickness was 35 μ.
以上で得た各々の回路基板につき、(A)100倍の実体
顕微鏡を用いて、回路間絶縁部上におけるCuの異常析
出の有無を調べた。(B)半田食われを試みるため、23
0℃の共晶浴に10秒間浸漬する操作を4回くり返した
後、半田付け面の濡れ面積を比較した。(C)Al−1%
Si線(35μφ)を用いてウエツジボンデイングを行
い、更に両自由端をボンドしてループを形成し引張強度
を測定した。20本のループについて測定し、平均強度
を求めた。表−1に結果ををまとめて示す。For each of the circuit boards thus obtained, (A) a stereoscopic microscope with a magnification of 100 was used to examine the presence or absence of abnormal precipitation of Cu on the inter-circuit insulating portion. (B) 23 to try to eat solder
The operation of immersing in a eutectic bath at 0 ° C. for 10 seconds was repeated 4 times, and then the wetted areas of the soldering surfaces were compared. (C) Al-1%
Wet bonding was performed using a Si wire (35 μφ), both free ends were further bonded to form a loop, and the tensile strength was measured. 20 loops were measured and the average strength was calculated. The results are summarized in Table-1.
上記表−1より、本発明による実施例1品は半田食われ
が無く、ボンド強度大の微細回路であることが明らかで
ある。従来法による比較例4〜5は、35μの厚いCu
層をもつため、半田食われにおいて実施例1と同等の結
果を示したが、ボンド強度に劣り、かつ回路はより粗に
とどまった。比較例1〜3は、Cuレジンペーストを用
いる点で本発明例と共通しているが、本発明条件を欠い
ているため、いずれも不都合な点を有している。 From Table 1 above, it is clear that the product of Example 1 according to the present invention is a fine circuit without solder erosion and having a high bond strength. Comparative Examples 4 to 5 by the conventional method have a thick Cu of 35 μm.
Since the layer had a layer, the same results as in Example 1 were shown in solder erosion, but the bond strength was poor and the circuit remained coarse. Comparative Examples 1 to 3 are common to the example of the present invention in that a Cu resin paste is used, but since they lack the conditions of the present invention, they all have disadvantages.
2)実施例2、及び比較例6〜7 上述の如く、本発明はNiBメツキの特性を活かしてC
uレジンペースト応用回路の高性能化を実現している。
この点をより明らかにするため、実施例1において、N
iBメツキ厚を1.5μ(実施例2)、0.5μ(比較
例6)0μ(比較例7)とした試料について(B),(C)
の測定をした。表−2に結果を示す。2) Example 2 and Comparative Examples 6 to 7 As described above, the present invention utilizes the characteristics of NiB plating to produce C
High performance of u resin paste application circuit is realized.
In order to make this point clearer, in Example 1, N
Samples having iB plating thicknesses of 1.5 μ (Example 2), 0.5 μ (Comparative Example 6) and 0 μ (Comparative Example 7) (B) and (C)
Was measured. The results are shown in Table-2.
〔発明の効果〕 本発明はエレクトロニクスの発展に伴って、今後益々大
量に、かつ工業的に強く要求される良性能の高密微細プ
リント回路基板の新規な製造方法であり、従来の如くエ
ツチングやレジスト等の多段多様な工程を要することな
く、より一層能率的経済的な製造を可能にするものであ
る。しかも得られる回路基板は半田食われのない微細回
路基板であり、今後の電子部品実装の主流となりつつあ
る面実装に好適なものであり、本発明の工業的意義は極
めて大きい。 [Advantages of the Invention] The present invention is a novel method for producing a high-density fine printed circuit board of good performance, which will be required more and more industrially in the future in accordance with the development of electronics. It enables more efficient and economical manufacturing without requiring multi-stage and various processes such as. In addition, the obtained circuit board is a fine circuit board without solder erosion and is suitable for surface mounting, which is becoming the mainstream of electronic component mounting in the future, and the industrial significance of the present invention is extremely great.
Claims (3)
所望の回路パターンを形成したのち、NiB化学メツキ
を施し、ついでCu化学メツキを施して導電回路を形成
することを特徴とする回路基板の製造方法。1. A Cu resin paste on an insulating substrate,
A method for manufacturing a circuit board, which comprises forming a desired circuit pattern, performing NiB chemical plating, and then performing Cu chemical plating to form a conductive circuit.
%のCu又はCu合金粉末を含有するCuレジンペース
トを用いることを特徴とする特許請求の範囲第1項記載
の回路基板の製造方法。2. The method for producing a circuit board according to claim 1, wherein a Cu resin paste containing 60 to 95% by weight of Cu or Cu alloy powder is used as the Cu resin paste.
化学メツキを少くとも5μ厚施すことを特徴とする特許
請求の範囲第1項記載の回路基板の製造方法。3. NiB chemical plating of at least 1 μm thick, Cu
The method for manufacturing a circuit board according to claim 1, wherein the chemical plating is applied to a thickness of at least 5 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12055785A JPH0646672B2 (en) | 1985-06-05 | 1985-06-05 | Circuit board manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12055785A JPH0646672B2 (en) | 1985-06-05 | 1985-06-05 | Circuit board manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61279195A JPS61279195A (en) | 1986-12-09 |
| JPH0646672B2 true JPH0646672B2 (en) | 1994-06-15 |
Family
ID=14789253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12055785A Expired - Lifetime JPH0646672B2 (en) | 1985-06-05 | 1985-06-05 | Circuit board manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0646672B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01140870U (en) * | 1988-03-22 | 1989-09-27 | ||
| CN111885832B (en) * | 2020-07-22 | 2021-12-21 | 广东天承科技股份有限公司 | Neutralizing and reducing solution for PCB (printed circuit board) glue removal post-treatment as well as preparation method and application thereof |
-
1985
- 1985-06-05 JP JP12055785A patent/JPH0646672B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61279195A (en) | 1986-12-09 |
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