JPH0646698B2 - Superconducting slave flip-flop - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a superconducting flip-flop circuit, and more particularly to a flip-flop circuit suitable for an AC power supply driven Josephson circuit.

[Conventional technology]

The AC power supply driven Josephson circuit requires a master-slave flip-flop circuit that transfers information during the cycle of the power supply current. The power supply current for driving the Josephson circuit consists of a transient part near the value of zero and a steady part in between. The logic progression of the combinational circuit takes place during the steady-state part, but its hold information is reset to the transient part. Therefore, a master-slave flip-flop holding data during the transient is needed. As a master-slave flip-flop circuit, A. Davidson "A Josephson Latch" I E E E, Journal of Solid State Circuits, Vol. 13, No. 5, October 1978, 583-590.
Page (A. Davidson, "A Josephson Latch" IEEE
Journal of Solid-State Circuits, Vol, SC-1
3, No. 5, October 1978, pp. 583-590)
As will be discussed in detail in Section 1, the master flip-flop that holds the value of the data input established in the steady-state part before the AC power supply until the end of the next transient part, and the master-flip-flop of the master flip-flop at the start part of the steady-state part. It is generally composed of a slave flip-flop that reads an output and holds an output value corresponding to the output value during a steady portion.

Here, in the slave flip-flop described in the document, a magnetic flux quantum interference type circuit (Josephson Interferometer;
Hereinafter referred to as JI. ) Two are used, the output current of the first JI is set as the drive current (power supply current) of the second JI, and the second when the control line input is applied to both the first and second JIs.
A wire-and-type gate structure that can obtain the JI output current is adopted.

The detailed structure and problems of this wire-and-type gate will be described with reference to FIG.

Here, as JI, when a control line input is given from the third terminal to the fourth terminal when a drive current (power supply current) is flowing from the first terminal to the second terminal, the first terminal and the second terminal are connected. Two
The one in which the superconducting state transitions between the terminals to the voltage state is used.

In FIG. 2, the first terminal of the first JI (hereinafter referred to as the input stage JI) 211 is connected to the resistors 204 and 205 from the power source bus 201.
AC power supply current is supplied via the. Second JI
An AC power supply current is supplied to the first terminal of 213 (hereinafter referred to as output stage JI) through resistors 204 and 206 as well.

[Problems to be Solved by the Invention]

The problem here is that in the wire-and-type gate of FIG. 2, even if the input stage JI211 or 213 is switched from the zero voltage state to the voltage state, the control line input to the output stage JI214 or 213 is not always sufficient. It is not cut off low. The equivalent resistance value of the input stage JI 211, 212 after switching is not infinitely larger than that of the resistor 206. In particular, after the input stage JI211 is switched, when the output stage JI213 is also switched, the load resistance seen from the input stage JI is the sum of the resistances 206 and 207, and a certain amount of power supply current flows through the input stage JI211 itself, and the output stage JI214. Comes to the control line.
Then, in this state, when the control line input is applied to the other input stage JI212 to switch and the power supply current is transferred to the output stage JI214, the output stage JI214 is likely to be erroneously switched.

The object of the present invention is to have the output stage J after the input stage JI is switched.
It is an object of the present invention to provide a slave flip-flop that can cut off the I control line current to a sufficiently small value.

[Means for Solving the Problems]

The above object is achieved by inserting a buffer stage JI between the input stage JI211 and the output stage JI213.

[Action]

The operation of the buffer stage JI in the slave flip-flop will be described with reference to FIG. An AC power supply current is supplied to the first terminal of the buffer stage JI301 from the power supply bus 201 via the resistors 304 and 305. The second terminal of the buffer stage JI301 is grounded. The output signal line 306 of the input stage JI211 is terminated by the load resistor 303 via the control line of the buffer stage JI301. From the connection point 310 of the resistors 304 and 305 to the output stage JI 213 via the resistor 206.
The AC power supply current is also supplied to.

When the set input is applied to the terminal 202 at the time of the rise of the AC power supply, the input stage JI211 switches from the zero voltage state to the voltage state, and the output current flows through the output signal line 306 and the buffer stage JI2.
I301 also switches from the zero voltage state to the voltage state. Then, the power supply current supplied to the buffer stage JI301 is transferred to the output stage JI213. At this time, if there is no reset input at the terminal 203 and the input stage JI212 is in the zero voltage state, a current is flowing through the control line of the output stage JI213. Therefore, the output stage JI213 also switches from the zero voltage state to the voltage state, and the output current flows through the load resistor 207.

Here, the load seen from the input stage JI211 is only the resistor 303, and even if the output stage JI213 is switched, its influence does not return to the input stage JI211. Therefore, the output stage JI214 after the input stage JI211 has switched
The control line current of is always kept low.

In order to increase the output current amplitude of the output stage JI213, it is necessary to raise the value of the resistor 305 to about 1/4 to 1/3 of the value of the resistor 206. Then, even after the buffer stage JI switch,
A considerable power supply current remains in the JI, but this does not affect others. Therefore, the output current amplitude of the output stage JI213 can be made sufficiently large.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. The input stage JI 211, 212, the buffer stage JI 301, 302 and the output stage JI 213, 214 are three-junction type JI whose structure is shown in FIG. The same JI has the first terminal 4
The control line current is applied between the third terminal 404 and the fourth terminal 405 while the power supply current is being supplied from 02 to the second terminal 403, whereby the fifth terminal 401 and the second terminal 403 are During the interval, the zero voltage state changes to the voltage state.
In order to keep the threshold current value (the maximum power supply current value that can be flowed while keeping the zero voltage state) when applying the JI control line current low, the device inductances 406 to 409 are selected to be as small as possible and compensate for this. To do this, in the buffer stages JI301, 302 and the output stages JI213, 214, the control line currents are combined in a double winding.

In the slave FF of FIG. 1, a damping resistor 121 is inserted between the second terminal 111 of the input stage JI211 and the ground point. This damping resistance prevents resonance between the control line inductance of the output stage JI 214 and the parasitic capacitance of the input stage JI 211 during switching, and prevents the output signal line 3
06 has a function of transmitting an output current without any disturbance.

FIG. 5 shows another embodiment of the present invention. In the figure, the Josephson junction 501, together with the resistors 121 and 502, has a function of bypassing a current equal to or less than the threshold current value of the Josephson junction 501 to the ground point and completely zeroing the control line current of the output stage JI214. After the input stage JI switch, most of the power source current is transferred to the load resistor 303, but some amount remains as it is and goes from the node 111 to the ground point. In the configuration shown in FIG. 1, this current flows through the control line of the output stage JI214 as it is. However, in the configuration of FIG. 5, this residual control line current can be suppressed to 0, and malfunction of the output stage JI 214 can be prevented.

FIG. 6 shows still another embodiment of the present invention. In the figure, output stages JI 213 and 214 having a large device inductance value are selected, and the elements can be switched even by a control current of a single winding. The current path 611 extending from the second terminal 111 of the input stage JI211 to the ground point 614 passes through the control lines of the output stages JI213 and 214, each having a single turn. Also input stage JI21
Current path 6 from the second terminal 112 of No. 2 to the ground point 613.
12 is the output stage JI21 in the opposite direction to the current path 611.
Each of the 3,214 control lines also goes through a single winding.

In the same figure, it is assumed that the input stage JI211 is switched when the AC power supply rises. Then, the power supply current flowing in the current path 611 is transferred to the output current path 306 of the input stage JI211.
Then, the output current flows through the control line of the buffer stage JI301, and the JI switches. Then, the power supply current is transferred to the output stage JI213. If the input stage JI212 is not switched yet, the power supply current continues to flow in the current path 612. This causes the output stage JI213 to switch. Then, if the other input stage JI212 is switched, the power supply current is transferred to the output stage JI214 in the same order, but the current paths 611 and 612 have already been transmitted.
The output stage JI 214 does not switch because both currents are blocked. Here, the current path 61 is actually
There is a small amount of current remaining in 1,612.
However, they are equal in size, and they work in the direction of canceling each other out within the control line of the output stage JI 214 to make them completely zero, so that malfunction of the output stage JI 214 can be completely prevented. The resistors 601 and 602 inserted in parallel to the control lines of the buffer stages JI301 and 302 are connected to the input stage JI21.
It has a function of delaying the propagation of switching from 1 and 212 to the buffer stages JI 301 and 302 and preventing the transfer of the power supply current earlier than the disappearance of the control line current of the output stage JI.

FIG. 7 shows a method of further amplifying the output current amplitude of the slave FF described above. The output of the output stage JI213 is inserted into the Josephson junction 703 via the resistor 701. On the other hand, a power supply current is supplied to the Josephson junction 703 also via the power feeding resistor 705, and an output current amplified by both is flowing to the load resistor 207.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide a slave flip-flop having a large output current amplitude without causing a malfunction, so that there is an effect of greatly improving the operation margin of the Josephson integrated circuit including the flip-flop.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a conventional technique, FIG. 3 is a diagram showing a principle configuration of the present invention, and FIG. 4 is used in FIG. Junction type JI circuit diagram, No. 5
FIG. 6 and FIG. 6 are circuit diagrams showing another embodiment of the present invention, and FIG. 7 is a diagram showing yet another embodiment of the present invention. 211, 212 ... Input stage JI, 213, 214 ... Output stage JI, 301, 302 ... Buffer stage JI, 204, 206, 304 ... Feeding resistance, 303, 207 ... Load resistance, 201 ... AC power supply Bus bar, 121, 122 ... Damping resistance.

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Hiroyuki Mori 1-280, Higashi Koigokubo, Kokubunji, Tokyo Metropolitan Research Laboratory, Hitachi, Ltd. Kenichi Ishii (56) Reference JP-A-59-183523 (JP, A) JP-A-59-210722 (JP, A) JP-A-61-261916 (JP, A)

Claims (1)

[Claims] Claim: What is claimed is: 1. A control current is supplied from a third terminal to a fourth terminal while a drive current is supplied from the first terminal to the second terminal. The first to the sixth magnetic flux quantum interference type circuits for switching between the zero voltage state and the voltage state are included in the first, second, third and
An AC power supply current is supplied to each first terminal of the fourth magnetic flux quantum interference type circuit, and a second terminal of the first magnetic flux quantum interference type circuit is connected to a third terminal of the sixth magnetic flux quantum interference type circuit. Connected,
The second terminal of the second magnetic flux quantum interference type circuit is connected to the third terminal of the fifth magnetic flux quantum interference type circuit, and the fifth terminal of the first magnetic flux quantum interference type circuit is connected to the third magnetic flux quantum The third magnetic flux quantum interference type circuit is connected to the third terminal of the interference type circuit, the fifth terminal of the second magnetic flux quantum interference type circuit is connected to the third terminal of the fourth magnetic flux quantum interference type circuit. The fourth terminal of the circuit is grounded via a resistor, the fourth terminal of the fourth flux quantum interference type circuit is grounded via a resistor, and the first terminal of the third flux quantum interference type circuit is a resistor. Is connected to the first terminal of the fifth magnetic flux quantum interference type circuit via a resistor, and the first terminal of the fourth magnetic flux quantum interference type circuit is connected via a resistor to the first terminal of the sixth magnetic flux quantum interference type circuit. A second terminal of the third magnetic flux quantum interference type circuit connected to the terminal, a second terminal of the fourth magnetic flux quantum interference type circuit,
Second and fourth terminals of the fifth magnetic flux quantum interference type circuit, second and fourth terminals of the sixth magnetic flux quantum interference type circuit are grounded, and third terminals of the first magnetic flux quantum interference type circuit are grounded. A set input is added to the current path from the terminal to the fourth terminal and a reset input is added to the current path from the third terminal to the fourth terminal of the second magnetic flux quantum interference type circuit, and a fifth magnetic flux quantum is added. Interference type circuit No. 5
A superconducting slave flip-flop, wherein a true value output is taken out from a terminal of and a complementary value output is taken out from a fifth terminal of the sixth magnetic flux quantum interference type circuit.