JPH0646873B2 - Digital phase controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase controller for controlling the rotational phase of a controlled object.

Configuration of Conventional Example and Its Problems FIG. 1 shows a conventional example of a digital type phase control device.
Is a controlled body (a motor or a rotating body driven by a motor), 2 is a frequency generator (hereinafter referred to as FG), 3 is a digital speed comparison means, 4 is a digital filter, 5 is drive means, and 6 is rotational position detection. (Hereinafter referred to as PG), 7 is a digital phase comparing means, and 8 is a digital filter.

The rotation speed of the controlled object 1, that is, the rotation speed is detected by the _{FG 2} as a signal (FG signal) S _FG having a frequency proportional to the speed, and the signal (PG signal) S _PG representing the rotation phase is detected as PG.
6 to detect. The FG signal S _FG is input to the speed comparison means 3, and its frequency is digitally discriminated (speed comparison) by the clock pulse CK1 to detect digital speed error information D _S1 . The speed error information D _S1 is digitally processed by the digital filter 4 and the digital output D _S2 is guided to the driving means 5 to control the rotation speed of the controlled body 1. On the other hand, PG signal S _PG external reference signal S
_It is input to the phase comparison means 7 together with _RF , and the clock pulse C
The phase difference between the two signals is digitally discriminated (phase comparison) by K2, and the digital phase error information D _P1 is detected.
The phase error information D _P1 is digitally processed by the digital filter 8 and the digital output D _P2 is guided to the speed comparison means 3 to control the rotational phase of the controlled body 1. As described above, the digital phase control device for synchronizing the rotation phase (signal S _PG ) of the controlled object 1 with the reference phase (signal S _RF ) is embodied.

First, the operation of the speed comparison means 3 and the phase comparison means 7
This will be described with reference to FIGS.

The speed comparison means 3 has an FG signal S _FG and a clock pulse C.
K1 is input to generate a latch pulse S _L1 that precedes the timing and a preset pulse S _P1 that follows the timing. Normally, the speed comparison means 3 is composed of a binary counter for M bits, and detects the speed error information D _S1 from the lower N bits of the binary counter, and digitally generates an equivalent trapezoidal wave S _Z1 by the preset pulse S _PR. It is created and latched by the latch pulse S _L1 to obtain the speed error information D _S1 . T _i is a reference period for speed comparison, and T _FG is a period of the FG signal S _FG . A is in a low speed state with T _FG > T _i , B
Is a constant speed state when T _FG = T _i , C is a high speed state when T _FG > T _i , and in state A, the minimum value of trapezoidal wave S _Z1 is set to state B.
In the state C, the central value is latched (sampled), and in the state C, the maximum value is latched (sampled).

The phase comparison means 7 has external reference signals S _RF and PG signals S
_PG and the clock pulse CK2 are input, a preset pulse S _P2 is created by the external reference signal S _RF , and a latch pulse S _L2 is created by the PG signal S _PG . The position comparing means 7, like the speed comparing means 3, is also composed of a K-bit binary counter, and the phase error information D _P1 from the lower L bits thereof.
Is detected, the equivalent trapezoidal wave S _Z2 is digitally generated by the preset pulse S _P2 , and the phase error information D _{P1 is} latched by the latch pulse S _L2.
Is getting The illustrated state is a steady state, and the central position of the inclined portion of the trapezoidal wave S _Z2 created by the external reference signal S _{RF is} latched by the latch pulse S _L2 created by the PG signal S _PG . In this advanced state, the phase error information D _P1 has the maximum value and the minimum value, respectively, in the advanced phase state in which the upper bottom portion of the trapezoidal wave S _Z2 is latched and in the delayed phase state in which the lower bottom portion is latched. A steady state (phase locked state) can be achieved by controlling the phase and advance. This can be realized by a configuration in which the digital output D _P2 obtained by digitally processing the phase error state D _P1 by the digital filter 8 is guided to the speed comparison means 3 and controlled. Digital output D
_As a control method of the speed comparison means 3 by _P2, there are a method of adding to the speed error information D _S1 and a method of modulating the reference period T _i . Needless to say, since the phase comparison means 7 has a binary counter configuration, it is possible to decode the predetermined count value to generate an internal reference signal and use it instead of the external reference signal S _{RF. The PG} may have a configuration in which the FG signal S _FG is divided and used.

Next, the construction, operation, and influence of the digital filters 4 and 8 on the system of FIG. 1 will be described with reference to the specific example shown in FIG.

4A shows an up-down counter type digital filter (U / D counter type DF), and FIG. 4B shows a cumulative addition type digital filter (cumulative addition type DF). The basic constituent elements of the digital filter are a U / D counter type frequency dividing means 9 and a U / D counter type 11, and a cumulative addition type adding means 1.
4 and the delay means (storage means) 15, by which the integral characteristic is obtained. Multipliers 12, 16 and adder 1
Reference numerals 3 and 17 are means for adding a proportional characteristic, respectively, whereby a proportional integral characteristic is obtained. In the operation of the U / D counter type DF, the frequency dividing means 9 divides the clock pulse CK3 into a frequency equal to the absolute value of the difference between the input digital signal D1 (corresponding to D _S1 and D _P1 ) and the reference digital signal D _0. , The frequency-divided output S ₁ of the U / D counter 1
Input as 1 clock. On the other hand, the magnitude discriminating means 10 discriminates the magnitude between D ₀ and D _1, and its output S ₂ is used as a U / D switching input. As a result, the U / D counter 11
Integral of _{D 1} which is a reference value _{D 0} from the output _D 2 _{(D S2,}
D _P2 is equivalent) is obtained. Here, the size discriminating means 10
Is not always necessary, and D _{0 is set} to 10 ... 0 (or 01
If a specific value such as 1) is set, the most significant bit of the input D ₁ can be used as the U / D switching input.
The operation of the cumulative addition type DF is performed by the storage means 15 and the addition means 14
The output D ₂ is stored and the output D ₅ and the input D ₁ are added by the adding means 14. As a result, the integrated output D ₂ of the input D ₁ (corresponding to D _S2 and D _P2 ) is obtained from the adding means 14. Normally, the storage operation of the storage means 15 is performed by latching pulses S _L1 . S _L2 is used respectively. The coefficients multiplied by the multiplying means 12 and 16 are real numbers including 1, and the proportional and integral outputs D ₄ (corresponding to D _S2 and D _P2 ) are obtained from the adding means 13 and 17.

These digital filters are applied to the means of 4 and 8 in FIG. 1 as an integral element or a proportional integral element as required. However, when the controlled object 1 is started or the speed is switched, the output D ₂ of the U / D counter 11 and the storage means 15,
D ₅ is not necessarily specified, and the phase lock-in of the phase controller is not performed smoothly and speedily. this is,
This is due to the initial states of the U / D counter 11 and the storage means 15. That is, for example, when it is not possible to output the maximum value (or a value in the vicinity) when decelerating the controlled object 1 and the minimum value (or a value in the vicinity) when accelerating, U
In the case of the / D counter type DF, it is necessary to wait for the counting operation of up or down, a lot of time is required for pulling in the phase synchronization, and the cumulative addition type DF is also the same. In the worst case, the storage means 15 There is a problem that the minimum value or the maximum value is held and the phase synchronization cannot be pulled in.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the conventional example, and to provide a digital phase control device in which the phase synchronization pull-in at the time of start-up or speed switching is shortened.

Configuration of the Invention The present invention can shorten the phase synchronization pull-in time at the time of start-up or speed switching by adopting a configuration in which control is performed according to the speed comparison state of the digital filter speed comparison means constituting the digital phase control device. It is a thing.

Description of Embodiments The configuration and operation of the present invention will be described below with reference to embodiments. Fifth
FIG. 1 is an electrical block diagram of a digital type phase control device showing an embodiment of the present invention.

In FIG. 5, reference numeral 18 denotes state detecting means for detecting the state of speed comparison of the speed comparing means 3.
The difference from the conventional example of FIG. 1 is that the state of the digital filters 4 and 8 is controlled by the detection output S ₃ of FIG. The points of the present invention will be described below.

Normally, the speed comparison means 3 operates as shown in FIG. 2 and the signals S _NH and S _NL shown in FIG. 6 are used to form the trapezoidal wave S _Z1 .
Is created and used. This is a signal necessary for taking out the lower N bit output from the M bit binary counter forming the speed comparing means 3 only for one cycle before the end of counting. S _NH is the “H” level period of the trapezoidal wave S _Z1 (the first
_SNL is a signal for setting the "L" level period C (third state), and the speed comparison period B (third state) in which a speed comparison error can be detected by these two signals. 2 state) is set. Here, the period c is a period in which the controlled object 1 should be accelerated, and the period a is a period in which it should be decelerated, and neither speed pull-in nor phase pull-in is possible. Therefore, during this period, the output S _{3 of the} state detection means 18
Therefore, in period c, the digital filter 4 gives an acceleration command,
The digital filter 8 outputs a phase advance command, and during the period a, the digital filter 4 outputs a deceleration command and the digital filter 8 outputs a phase delay command. Next, in period B, both velocity pull-in and phase pull-in are possible,
The control in the periods a and c is released, and the digital filters 4 and 8 are immediately set to the steady states of the velocity pull-in state and the phase pull-in state, and thereafter the control by the state detecting means 18 is released. By doing so, the phase synchronization pull-in of the phase control device, which is the object of the present invention, can be performed smoothly and speedily, and the pull-in time can be shortened.

FIG. 7 shows a concrete circuit example of the state detecting means 18, which produces a signal S ₃ for controlling the digital filters 4 and 8 from the speed comparing means S _NH and S _NL . FIG. 8 shows the operation waveforms of FIG. 7, where A shows the operation during acceleration (startup) and B shows the operation during deceleration.

In FIG. 7, 19 is a first shift register, 20 is a second shift register, and 19A, 19B, 20A, 2
0B is a D flip-flop (DFF), 19C is a 2-input NAND gate (2NAND), and 20C and 20D are 2-input NOR gates (2NOR). Signal S _NH , S
_NL is the DFF 19 of the first shift register 19, respectively.
It is used as the D input of A and 19B, and is latched by the latch pulse _SL1 . The Q output of the DFF 19A is output as the signal SE (H), and the Q output of the DFF 19B is NANDed with the signal S _NL by the 2NAND 19C and output as the signal RE (L). Next, the signals SE (H) and RE (L) are used as the D inputs of the DFFs 20A and 20B of the second shift register 20, respectively.
It is latched by the latch pulse S _L1 or the preset pulse S _P1 . 2NOR20C takes the NOR of the output of DFF20A and signal SE (H) and outputs signal RE (H), and 2NOR20D outputs the output of DFF20B and signal R
These 4 which take NOR with E (L) and output signal SE (L)
The kinds of signals SE (H), SE (L), RE (H), RE (L) are the detection output S ₃ of the state detecting means 18, and are used for controlling the digital filters 4 and 8 as necessary. The DFF 19B and the 2NAND 19C of the first shift register 19 are
This is a start command function included in the normal speed comparison unit 3, and it is not always necessary to newly install the state detection unit 18.

FIG. 9 shows an embodiment of a digital filter controlled by the output S ₁₃ of the state detecting means 18. In FIG.
A is the U / D counter 11 in the U / D counter type DF
And B is a configuration for controlling the storage means 15 in the cumulative addition formula DF.

FIG. 10 shows the U / D counter 11 and storage means 15 shown in FIG.
6 is a specific circuit example for explaining the control method of FIG.

In FIG. 10, flip-flops FF1 to FF8 correspond to the binary counter of the U / D counter 11 and the latch circuit of the storage means 15, respectively. A can handle only during acceleration, and during period C, FF1 to FF8 are all reset by the signal RE (L), and minimum values, that is, acceleration command and phase advance command are output. When the period B is entered, the reset operation by the signal RE (L) is released and only the FF8 of the MSB is instantaneously set by the signal SE (L) to set the center value.
Release the control of F8. As a result, pulling in from a low speed can be shortened. B is applicable for acceleration and deceleration, and FF
All of 1 to FF8 having a set input S and a reset input R are used. The control at the time of shifting from the period c to the period b is similar to that of A, and the control at the time of shifting from the period a to the period b is added by the newly installed 20R gates 21 and 22. That is, in the period a, FF1 to FF are generated by the signal SE (H).
8 are all set and the maximum value, that is, the deceleration command and the delay command are output. When the period B is entered, the lower bits FF1 to FF7 are instantaneously reset by the signal RE (H) to be set to the central value, and thereafter the control of FF1 to FF8 is released. This makes it possible to shorten the pull-in from the low speed and the high speed.

FIG. 11 shows another embodiment of the digital filter. 9 is different from the embodiment shown in FIG. 9 in that output gate means 23 and 24 are added and controlled by the output S ₃ of the state detecting means 18, the state detecting means 18 and the U / D counter 1
1. The storage means 15 can be simplified. The output gate means 23 may be configured to gate the output D ₄ of the adding means 13, and the output gate means 24 may output the output D ₅ of the storing means 15 or the output D _{4 of the} adding means 17.
May be output as a gate.

FIG. 12 shows the U / D counter 11 and storage means 1 of FIG.
5, a specific circuit example for explaining the control method of the output gate means 23, 24. Figures 12A and B are the tenth respectively
It is an example of a circuit corresponding to FIGS. A and B. In A, FF1 to FF7 are reset by signal RE (L) in period C, FF8 is set to set the center value, and output gate means 25 uses FF.
The output of 8 is output through the 2AND gate 25A, and the output D is controlled by the inverted output of the inverter 26.
₂ 'to the minimum value. Then, when the period B is entered, this control is released. Also, in addition to A in B, 20 in period a
FF1 to FF depending on the signal SE (H) through the R gate 27
8 is set to the central value, and the output gate means 25 outputs the lower bits FF1 to FF7 to the 20R gates 25B to 25H.
The output D ₂ ′ is maximized by controlling the signal SE (H). Then, when the period B is entered, this control is released. In addition, during period C, 20R gate 2
5B to 25H are open, and during the period a, the 2AND gate 25A is open. With the above configuration, the seventh
The second shift register 20 of the state detecting means shown in the figure can be omitted, and the flip-flops FF1 to FF8 can be performed by only one of the function of setting or resetting, and the configuration can be simplified.

The specific example of the digital filter described above can be commonly used for the digital filters 4 and 8 in FIG. 5, and the smooth and speedy phase synchronization pull-in which is the object of the present invention can be achieved.

Here, when the method of controlling the reference period Ti as the method of controlling the speed comparison means 3 is adopted, the digital filter 8 has a configuration in which the output gate means 25 and the inverter 26 of FIG. 12 are deleted, and FF1 to FF8 are used. All you have to do is set the center value of.

The above description is one embodiment of the present invention, and it goes without saying that various configurations are possible without departing from the concept of the present invention.

EFFECTS OF THE INVENTION As described above, according to the present invention, when the controlled object is started or the speed is switched, the digital filter is controlled according to the state of speed comparison. Retraction can be shortened and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional digital phase controller, FIGS. 2 and 3 are operation waveform diagrams of the conventional example, and FIG. 4 is a block diagram of a digital filter used in the conventional example.
FIG. 5 is a block diagram of a digital type phase control device according to one embodiment of the present invention, and FIG. 6 is an operation waveform diagram of the same embodiment.
FIG. 7 is a concrete circuit diagram of the state detecting means of the embodiment, FIG. 8 is an operation waveform diagram of the concrete circuit example, and FIG. 9 is a block diagram of a digital filter of an embodiment applicable to the embodiment of the present invention. FIG. 10 is a partial concrete circuit diagram of the embodiment, FIG. 11 is a block diagram of a digital filter of another embodiment applicable to the embodiment of the present invention, and FIG. 12 is a partial concrete circuit diagram of the embodiment. is there. 3 ... Speed comparison means, 4, 8 ... Digital filter,
5 ... Driving means, 7 ... Phase comparing means.

Claims (1)

[Claims] 1. A speed comparing means for detecting speed error information as a digital quantity by discriminating a rotation frequency signal detected from a controlled object, and a first digital filter for filtering an output of the speed comparing means. Driving means for controlling the rotation speed of the controlled object according to the output of the first digital filter, and phase error information as a digital quantity by comparing a rotational phase signal detected from the controlled object with a reference signal. A phase comparison means for detecting, a second digital filter for filtering the output of the phase comparison means to control the speed comparison means, and a rotation speed of the controlled object is high and outside the comparison area of the speed comparison means. A first state, a second state in which the rotational speed of the controlled object is within a comparison area of the speed comparison means, and the controlled object A third state in which the rotation speed is low and is outside the comparison area of the speed comparison means is detected, and in the first state, the output of the first and second digital filters is the maximum value (or the minimum value). In the third state, the first and second digital filters are controlled so that the output has the minimum value (or the maximum value), and the second state is entered. Immediately after that, a state detecting means for initializing the first and second digital filters so that the output becomes a center value, and a digital type phase control device.