JPH0648722B2 - Semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device, and more particularly to a pair of CMOSs.
The present invention relates to a 6-transistor type semiconductor memory device having a converter.

[Technical background of the invention and its problems]

A 6-transistor type semiconductor memory device (static memory) having a pair of CMOS inverters has a circuit configuration shown in FIG. That is, Qp ₁ and Qn ₁ in the figure
Is a p-channel M forming one CMOS inverter
An OS transistor and an n-channel MOS transistor. Qp ₂ and Qn ₂ in the figure are a p-channel MOS transistor and an n-channel MOS transistor forming the other CMOS inverter. The gate of one CMOS inverter is cross-connected to the common drain portion D ₂ of each transistor of the other CMOS inverter, and the gate of the other CMOS inverter is cross-connected to the common drain portion D ₁ of the one CMOS inverter to form a flip-flop circuit. Are configured. The sources of the p-channel MOS transistors Qp ₁ and Qn ₂ are connected to V _DD , and the n-channel MOS transistors Q
n ₁ and Qn ₂ are connected to V _SS , respectively. Said common drain portion _{D 2} of the common drain part _{D 1} and the transistor _Qp 2, Qn ₂ transistors _Qp 1, Qn ₁ of the flip-flop circuit is set each _{V DD potential,} the _{V SS} potential, holds the information There is. For example, when the common drain portion D ₁ is at V _DD potential, the transistor Qp ₂ is off and the transistor Qn ₂ is on, so that the common drain portion D ₂ is at _VSS potential, so that the transistor Qp ₁ is on and the transistor Qn is on. ₁ is off. In addition, Qn ₃ and Qn ₄ are n-channel MOS transistors each of which functions as a transfer gate.
The S transistor Qn ₃ is connected to the node of the flip-flop circuit, and the other MOS transistor Qn ₄ is connected to the node of the flip-flop. The bit lines B are provided on the drain side of the transistors Qn ₃ and Qn ₄ , respectively.
L ₁ , BL ₂ are connected, and each transistor Qn ₃ ,
The gate of Qn ₄ is connected to the word line WL.
The transistors Qn ₃ and Qn ₄ are turned on when a memory cell is selected and writing and reading are performed, and the bit lines BL ₁ and BL connected to the drain side of the transistors Qn ₃ and Qn ₄ are connected. Information is transmitted between ₂ and the flip-flop circuit.

When information is written in the memory cell described above, for example, the common drain portion D _{1 is set} to the _VSS potential and the common drain portion D _{2 is}
Is set to the V _DD potential, the bit line BL _1
Is set to V _SS level and the bit line BL ₂ is set to V _DD level, and the transistors Qn ₃ and Qn ₄ as transfer gates are turned on by the word line WL. On the other hand, in the case of reading, the bit line, B
Transistors Qn ₃ and Qn as transfer gates by connecting L ₁ and BL ₂ to a sense-up circuit (not shown)
Turn on ₄ .

As the memory cell of the 6-transistor type static memory described above, the one having the structure shown in FIGS. 2 to 4 is conventionally known. In the figure, Qp ₁ and Qn ₁ are one CMO
An n-channel MOS transistor forming an S inverter, an n-channel MOS transistor, Qp ₂ in the figure,
Qn ₂ is a p-channel MOS transistor or an n-channel MOS transistor forming the other CMOS inverter. These CMO itinverters form a flip-flop circuit by cross-connecting one gate to the common drain part of the other. ing. Also,
In the figure, Qn ₃ and Qn ₄ are n-channel MOS transistors as transfer gates connected to the drain sides of the n-channel MOS transistors Qn ₁ and Qn ₂ .

As shown in FIGS. 3 and 4, the p-channel MOS transistors Qp ₁ and Qp ₂ are island-shaped and are separated by the field oxide film 3 of the n-type silicon substrate 2 in which the p-well 1 is selectively formed. The n-type silicon substrate 2 is formed in each region. One of the transistors Qp ₁ includes a p ⁺ type source 4 ₁ and a drain region 5 ₁ which are electrically isolated from each other in the island-shaped substrate 2 region, and between the source and drain regions 4 ₁ , 5 _1. Substrate 2 including the channel region
A gate electrode 7 ₁ made of, for example, phosphorus-doped first layer n-type polycrystalline silicon, which is disposed above the gate oxide film 6 and is shared by the gate of the n-channel MOS transistor Qn _1. ing. On the other hand, the transistor Qp ₂ includes the p ⁺ type source 4 ₁ and the drain region 5 ₂ which are electrically isolated from each other in the island-shaped substrate 2 region, and these source and drain regions 4 ₁ , 5.
Gate oxide film 6 on the substrate 2 including the channel region between the _two.
It is disposed through the n-channel MOS transistor Qn gate electrode 7 made of a first layer n-type polycrystalline silicon, for example phosphorus is common doped with the gate of the _{2 2}
It consists of and. The p ⁺ type source region 4
₁ is shared by both the transistors Qp ₁ and Qp ₂ and functions as a V _DD line. The transistors Qn ₁ and Q ₂ are respectively formed in the island-shaped p-well 1 region separated by the field oxide film 3. One transistor Qn _1, the island-like p- wells 1 ^{n +} -type source formed electrically isolated from each other in the region _{4 2,} the drain region _{5 3,} these source and drain regions ₄ 2, 5 is arranged through a gate oxide film (not shown) on the well 1 includes a channel region between the _3, and a gate electrode 7 _{Tokyo and} composed of the first layer n-type polycrystalline silicon. The other transistor Qn ₂ is an n ⁺ type source 4 ₃ and a drain region 5 ₄ which are electrically isolated from each other in the island-shaped p-well 1 region, and these source and drain regions 4 ₃ and 5. is arranged through a gate oxide film (not shown) on the well 1 includes a channel region between _4, and a gate electrode 7 ₂ which made of the first layer n-type polycrystalline silicon. Further, as shown in FIG. 4, one of the transistors Qn _{3 serving} as the transfer gate has an n ⁺ -type source region common to the drain region 5 ₃ electrically isolated from each other in an island-shaped well 1 region, and a drain region 5 _5, these source and drain regions _(3), 5 to the well 1 region comprising a channel region between the ₅ disposed via a gate oxide film 6, for example, phosphorus which is common with the other transistor Qn ₄ First doped
And a gate electrode 7 ₃ which consists of a layer n-type polycrystalline silicon. The other transistor Qn ₄ is and the drain region 5 ₄ which are electrically separated from one another like islands of well 1 region common n ⁺ -type source and drain regions 5 _6, these source and drain regions (5 ₄ ), 5 ₆
Is arranged through a gate oxide film (not shown) in well 1 region comprising a channel region between, and a gate electrode 7 ₃ which consists of the first layer n-type polycrystalline silicon. Incidentally, the gate electrode _{7 3} functions as a word line WL.

In addition, on the substrate 2 including the gate electrodes 7 _{1 to} 7 ₃ ,
The first CVD-SiO ₂ film ₈₁ is coated as an interlayer insulating film of the first layer, and the CVD-SiO ₂ film _{8 1}
Is the second layer n-type polycrystalline made of silicon V _SS power line 9 _1, 9 ₂ disposed to the first layer n-type polycrystalline silicon the same conductivity type impurity (phosphorus) is doped in the upper There is.
These _VSS power supply wirings 9 ₁ and 9 ₂ are formed by the first CVD.
Contact holes 1 opened in -SiO ₂ film _{8 1}
0 _1, 10 ₂ via the transistor _Qn 1, Qn ₂
Are connected to the source regions 4 ₁ , 4 ₃ . In addition, V
_{Since the SS} power supply wirings 9 ₁ and 9 ₂ also serve as the wirings of the memory cells adjacent to each other, one is arranged in each memory cell. Then, the V _SS power supply wirings 9 ₁ and 9 ₂
On the first CVD-SiO ₂ film ₈₁ containing the second CVD-SiO ₂ film _{8 2} as an interlayer insulating film of the second layer is coated, and said 2 CVD-SiO ₂ A pair of intersecting Al wirings 11 ₁ and 11 ₂ are arranged on the film 8 ₂ so as to cross the island-shaped substrate 2 region and the island-shaped well 1 region, respectively. One crossed for Al wiring 11 _1, 3
As shown in FIGS. 4 and 5, first and second CVD-SiO 2
₂ Contact hole 1 opened across films 8 ₁ and 8 ₂
The transistors Qp ₁ through 0 ₃ , 10 ₄ , and 10 ₅
Is connected to the drain region 5 ₁ , the extended portion 7a of the gate electrode 7 ₂ extending on the field oxide film 3, and the drain region 5 ₃ of the transistor Qn ₁ . The other intersection for A wiring 11 ₂ first, second CVD-SiO
₂ Contact hole 1 opened across films 8 ₁ and 8 ₂
0 ₆ , 10 ₇ , 10 ₈ via the transistor Qp ₂
The drain region 5 _2, are respectively connected to the drain region 5 ₄ of the gate electrode 7 of _the fields extending portion 7b extending over the oxide film 3 and the transistor Qn _2. By providing the crossing Al wirings 11 ₁ and 11 ₂ , the gate electrodes 7 ₂ of the transistors Qp ₂ and Qn ₂ that form the other CMOS inverter are connected to one CMO.
Transistors Qp ₁ and Qn ₁ constituting the S inverter are cross-connected to the drain regions 5 ₁ and 5 ₃ of the crossing Al wiring 11 ₁ and the contact holes 10 ₃ to 10 ₅ and constitute one CMOS inverter. ₁ , the gate electrode 7 ₁ of Qn ₁ is the CMO of the other
Cross-connected through the S transistor _Qp 2, Qn drain region ₅ 2 _{2, 5} for the crossing to ₄ Al wiring 11 ₂ and the contact hole ₁₀ 6 to 10 ₈ constituting the inverter, thereby cross-connect the respective CMOS inverters are mutually Implemented flip-flop circuit. Also,
Wherein the second upper CVD-SiO ₂ film _{8 2,} Al wiring as bit line _{12 1, 12 2 (BL 1} , BL 2)
And the Al wirings 12 ₁ and 12 ₁ are provided through contact holes 10 ₉ and 10 ₁₀ opened over the first and second CVD-SiO ₂ films 8 ₁ and 8 _2. Transistors Qn ₃ and Q as the transfer gate
The drain regions 5 ₅ and 5 ₆ of n ₄ are respectively connected.
In the figure, 13 is the crossing Al wirings 11 ₁ and 11 _2.
And second CVD-Si including Al wirings 12 ₁ and 12 _2.
Coated on O ₂ film 8 ₂ a is a protective film.

Incidentally, CMOS is accompanied by a latch-up phenomenon as is well known. This will be described with reference to the schematic diagram showing the latch-up phenomenon of the CMOS structure shown in FIG. 5, that is, the thyristor effect and its equivalent circuit diagram shown in FIG.

Reference numeral 21 in FIG. 5 is an n-type silicon substrate, and a p-well 22 is selectively provided on the surface of the substrate 21. A field oxide film 23 for separating element regions is formed on the surface of the substrate 21 including the well 22. The substrate 2 separated by the field oxide film 23
In one region, p ⁺ type source and drain regions 24 ₁ and 25 ₁ are provided which are electrically isolated from each other. An n ⁺ type diffusion region 26 ₁ for biasing the substrate 21 is formed in a region of the substrate 21 adjacent to the source region 24 ₁ . The source / drain regions 24 ₁ and 25 ₁
A gate electrode 28 _{1 made of} polycrystalline silicon is formed on the substrate 21 including a channel region between them via a gate oxide film 27.
Is provided. Further, the field p ⁺ -type source which is electrically separated from each other in the island-like p- well 22 region isolated by an oxide film 23, the drain region 24 _2, 2
5 ₂ is provided. P ⁺ -type diffusion region 26 ₂ for biasing the well 22 is provided in the region of the well 22 adjacent to the source region 24 _2. A gate electrode 28 ₂ made of polycrystalline silicon is provided on the well 22 including the channel region between the source / drain regions 24 ₂ and 25 ₂ via a gate oxide film 27.
An interlayer insulating film 29 is coated on the entire surface of the substrate 21 including the gate electrodes 28 ₁ and 28 ₂ . On the interlayer insulating film 29, a source Al wiring 30 connected to both the p ⁺ type source region 24 ₁ and the n ⁺ type diffusion region 26 ₁ through a contact hole, a drain region 25 ₁ and a contact hole are formed. Drain Al wiring 3 connected via
1 and a gate Al wiring 32 connected to the gate electrode 28 ₁ through a contact hole, respectively. Further, the interlayer insulating over layer 29, the ^{n +} -type source region 24 ₂ and the ^{p +} -type diffusion region 26 ₂ and the source Al wiring 33 connected through a contact hole to both,
The drain region 25 _second drain Al wiring connected through a contact hole 34 and the gate electrode 28
A gate Al wiring 35 connected to each of the _two via contact holes is provided. The gate Al wirings 32 and 35 are on the Vin side, and the drain Al wiring 3
1 and 34 are Vout, the source Al wiring 30 of the p-channel MOS transistor is V _DD , and the source Al wiring 33 of the n-channel MOS transistor is V _DD.
Each is connected to _SS . In such a CMOS structure, the n ⁺ type source region 24 ₁ of the n-channel MOS transistor, the p-well 22, and the parasitic npn transistor Qn using the n-type silicon substrate 21 as the emitter, the base, and the collector, and the p ^{+ of the} p-channel MOS transistor are used ^. type source region 24 ₂ and the n-type silicon substrate 21 and the p
-A parasitic pnp transistor Qp having the well 22 as an emitter, a base, and a collector is formed, and a latch-up phenomenon occurs during the operation of the CMOS as described below.

Due to high integration of the CMOS inverter, the source / drain regions 24 ₁ , 24 ₂ , 25 ₁ , of each MOS transistor are
When 25 ₂ is fine, for example, when to turn on the n-channel MOS transistors, Hall by the drain region 25 ₂ near the impact eye demon internalized raises the potential of the generated p- well 22. When the potential of the p-well 22 rises, the parasitic npn transistor Qn based on the well 22 causes a bipolar action, and the collector current I _{RS of the} transistor Qn flows through the n-type substrate 21. Since this collector current I _RS flows through the resistance Rs of the n-type silicon substrate 21 on the V _DD side, the parasitic pnp transistor Q described above is used.
The base potential of p is lowered and the transistor Q
Make p a bipolar action. As a result, the collector current I _RW of the transistor Qp comes to flow.
The collector current I _RW flows through the p-well 22, and the resistance Rw increases the base potential of the parasitic npb transistor Qn described above. Even after the impact ionization does not occur, The rise of the base potential causes the transistor Qn to perform bipolar action. Due to the bipolar action of this transistor Qn, its collector current I _RW
Further lowers the base potential of the parasitic pnp transistor Qp to facilitate the flow of the collector current I _RW of the transistor Qp, thereby further raising the base potential of the parasitic npn transistor Qn and further increasing the collector current of the transistor Qn. The positive feedback causes a large current to flow from V _DD to V _SS . Due to the latch-up current, the CMOS does not operate and the integrated circuit (static memory) having the CMOS
Is thermally destroyed by a large current. like this,
An effective means for improving the latch-up resistance is to reduce Rs (resistance of n-type silicon substrate 21) and Rw (resistance of p-well 22) shown in FIGS. 5 and 6. Specifically, by providing a p ⁺ -type diffusion region for biasing the well formed in the p-well for each CMOS inverter and connecting a wiring for biasing each diffusion region, the well is formed. The resistance should be lowered.

Thus, the memory cells of static memory of Figure 2-Figure 4 illustrated previously described for the purpose of constituting a flip-flop circuit to each other cross-connected pair of CMOS inverters, a second CVD-SiO ₂ film 8 ₂ A pair of intersections on top
Since the 1-wirings 11 ₁ and 11 ₂ are provided, the second CV
A wiring density is lowered to determine the pitch of the memory cells on D-SiO ₂ film _{8 2.} Therefore, the first CVD-
The SiO ₂ film _{8 1} V _SS power line ₉ 1 on, _{9 2} formed by the second layer n-type polycrystalline silicon, a second CVD-S
It is compensated density decrease of the Al wiring of the on iO ₂ film _{8 2.}
The V _SS power supply wirings 9 ₁ and 9 ₂ made of n-type polycrystalline silicon are diffusion regions of the same conductivity type as the n-type impurities in the polycrystalline silicon, that is, n-channel as shown in FIGS. 2 to 4. Ohmic contact can be made to the n ⁺ type source regions 4 ₂ and 4 _{3 of the} MOS transistor Qn ₁ and the transistor Qn ₂ of the same channel. However, the V _SS power supply wirings 9 ₁ and 9 ₂ are commonly connected to the p ⁺ -type diffusion region for biasing the well 1 formed in the p-well 1 together with the source region, and the well 1 of the well 1 is connected. lowering the resistance, an attempt to improve the latch-up, take favorable ohmic contact pn junction is formed in the contact portion between the n-type polycrystalline made of silicon V _SS power line and the p ⁺ -type diffusion region Becomes difficult. As a result, in the static memories shown in FIGS. 2 to 4, the area for forming the Al wiring for the well bias is provided in a region different from the memory cell region, for example, every 8 cells. Therefore, in the conventional static memory, four Al wirings (two for cross connection and two for bit line) are used as the second CVD-SiO for each memory cell.
_Since it crosses over _two films, the pitch width of the memory cell is increased, and the area for forming the Al wiring for the well bias is provided in a region different from the memory cell region. As a result, the total integration degree of the memory decreases. Further, since the Al wiring for the well bias can be formed only for every 8 memory cells, the latch-up withstand capability cannot be sufficiently improved.

From this, as shown in FIG. 7 to FIG.
An attempt has been made to a static memory memory cell in which a pair of CMOS inverters are cross-connected to each other with a layer of polycrystalline silicon. That is, this memory cell is the first CVD-Si
O ₂ film 8 pair of cross wires 14 1 made of a second layer polycrystalline silicon on _1, 14 ₂ are arranged to cross each said island-like substrate 2 region and the island-shaped well 1 region .
One of the intersecting wirings 14 ₁ is connected to the p of the transistor Qp ₁ via a contact hole 15 ₁ opened in the first CVD-SiO ₂ film 8 ₁ as shown in FIGS. 8 and 9.
⁺ -Type drain region _{5 1} and the wiring part 16a of the connected p-type polycrystalline silicon in the contact holes ₁₅ 2 opened in the CVD-SiO ₂ film _{8 1,} 15 ₃ via the first
The n ⁺ -type drain region 5 ₃ of the extending portion 7a and the transistor Qn ₁ extending over the field oxide film 3 of the gate electrode 7 ₂ consisting of a layer n-type polycrystalline silicon each connected to n-type polycrystalline silicon It is composed of a wiring portion 17a. The other cross-wire 14 ₂ first CVD-SiO ₂
A wiring portion 16b of the p-type polycrystalline silicon connected to the ^{p +} -type drain region _{5 2} of the transistor Qp ₂ via a contact hole 15 ₄ opened in the film _81, the CVD
Contact holes 1 opened in -SiO ₂ film _{8 1}
The extension 7b of the gate electrode 7 _{1 made} of n-type polycrystalline silicon of the first layer and extending over the field oxide film 3 via 5 ₅ and 15 ₆ and the n ⁺ -type drain region 5 _{4 of the} transistor Qn _2. And an n-type polycrystalline silicon wiring portion 17b connected to each of the wirings. Further, the first CVD-SiO ₂ film 8 ₁ including the intersecting wirings 14 ₁ and 14 ₂ is formed.
The upper, ₂ a second CVD-SiO ₂ film ₈ is coated. P This second on CVD-SiO ₂ film _{8 2} constituting the p-type constituting the cross wiring 14 _1, n-type polycrystalline silicon wiring portion 16a, a 17a and between the cross wire 14 ₂ Type, n-type polycrystalline silicon wiring portion 16b,
A pair of Al layers 18 ₁ and 18 ₂ are provided for removing the adverse effects of the pn junctions formed between 17b and electrically. In other words, one Al layer 18 ₁ is the p
Type, the second CVD-SiO ₂ film containing n-type polycrystalline silicon wiring portion 16a, the pn junction between 17a _{8 2}
It is connected to the intersecting wiring 14 ₁ through an elongated contact hole 19 ₁ opened in the. Other Al layer 18 ₂ is the p-type, n-type polycrystalline silicon wiring portion 16
the second CVD-including a pn junction between b and 17b.
It is connected to the intersecting wiring 14 ₂ through an elongated contact hole 19 ₂ opened in the SiO ₂ film 8 ₂ .

However, in the static memory having the structure shown in FIG. 7 to FIG. 9, the density of Al wiring etc. in the cell is lower than that in the static memory of FIG. 2 to FIG. 4 described above. _Two Al wirings 12 ₁ and 12 _{2 and} a crossing wiring 1 made of second-layer polycrystalline silicon
Al layers 18 ₁ and 18 for ohmic connection of 4 ₁ and 14 _2
There is no change in that the total of _{two, that is} , two, is required, so that the pitch width of the memory cell determined by Al cannot be reduced. Therefore, even in the static memory having such a structure, the cell size cannot be reduced from the cell size of the conventional static memory, and since the second layer n-type polycrystalline silicon is used as the _VSS power supply wiring, the well Providing an area different from the cell area for forming the Al wiring for bias does not improve the degree of integration of the memory itself or the sufficient improvement of the latch-up resistance.

[Object of the Invention]

An object of the present invention is to provide a semiconductor memory device in which the pitch width of memory cells and the memory itself can be miniaturized and the latch-up withstand capability is remarkably improved.

[Outline of Invention]

The present invention has a pair of CMOS inverters, one of which has a C
A flip-flop circuit formed by cross-connecting the gate electrode of the MOS inverter to the drain region of each transistor of the other CMOS inverter via wiring;
In a semiconductor memory device in which memory cells composed of a pair of transfer MOS transistors connected to each node of the flip-flop circuit are integrated in a matrix on a semiconductor substrate, the gate electrode is of a first conductivity type. Of the first-layer polycrystalline silicon containing impurities, and the wiring is provided on the first-layer interlayer insulating film covering the gate electrode, and a contact hole is formed in the drain region of the first conductivity type and the gate electrode. A second-layer polycrystalline silicon wiring portion containing a first-conductivity-type impurity connected via a contact hole, and a second-conductivity-type drain region provided with a contact hole connected to the wiring portion. A second-layer polycrystalline silicon wiring portion containing an impurity of the second conductivity type and a metal layer attached to each wiring portion. It is intended. In the semiconductor memory device having such a structure, one metal wiring to be one power source is provided on the second-layer interlayer insulating film covering the intersecting wiring, and the metal wiring is
It is possible to connect via a contact hole to both the source region of one CMOS inverter and the diffusion region of the opposite conductivity type to the source region for biasing the substrate region in which this source region is formed. As described above, the pitch width of the memory cell can be reduced, the integration of the memory itself can be increased, and the latch-up resistance can be significantly improved.

Example of Invention

Hereinafter, an example in which the present invention is applied to a CMOS static memory will be described in detail with reference to FIGS.

Qp ₁ and Qn ₁ in the figure are p-channel MOS transistors and n-channel MOS transistors forming one CMOS inverter, and Qp ₂ and Qn ₂ in the figure are p-channel MOS transistors and n forming the other CMOS inverter. It is a channel MOS transistor,
These CMOS inverters form a flip-flop circuit by cross-connecting one gate to the other common drain portion. In addition, Qn ₃ and Q in the figure
n ₄ is each of the n-channel MOS transistors Qn ₁ ,
It is an n-channel MOS transistor as a transfer gate connected to the drain side of Qn ₂ .

As shown in FIGS. 11 and 12, the p-channel MOS transistors Qp ₁ and Qp ₂ are island-shaped and are separated by a field oxide film 53 of an n-type silicon substrate 52 in which a p-well 51 is selectively formed. Each is formed in the n-type silicon substrate 52 region. One transistor Qp
₁ is a p ⁺ -type source 54 ₁ and a drain region 55 which are electrically isolated from each other in the island-shaped substrate 52 region.
₁ and a channel region between the source / drain regions 54 ₁ and 55 ₁ on the substrate 52 via a gate oxide film 56, and, for example, phosphorus shared by the gate of the n-channel MOS transistor Qn ₁ is formed. Gate electrode 57 _{1 made of} doped first layer n-type polycrystalline silicon
It consists of and. The other transistor Qp ₂ is
The p ⁺ type source 54 and drain regions 55 ₂ are formed in the island-shaped substrate 52 region so as to be electrically isolated from each other.
And the n-channel MOS transistor Q is disposed on the substrate 52 including the channel region between the source / drain regions 54 ₁ and 55 ₂ via the gate oxide film 56.
for example, phosphorus is common with the gate of the n ₂ is constituted by a first layer n-type polycrystalline made of silicon gate electrode 57 ₂ which doped. The p ⁺ type source region 54
₁ is shared by both the transistors Qp ₁ and Qp ₂ and functions as a V _DD line. The transistors Qn ₁ and Qn ₂ are respectively formed in the island-shaped p-well 51 region separated by the field oxide film 53. One of the transistors Qn ₁ is an n ⁺ type source region 54 ₂ and a drain region 55 ₃ which are electrically isolated from each other in the island-shaped p-well 51 region, and these source and drain regions 54 ₂ , It is arranged through a gate oxide film (not shown) on a well 51 containing a channel region between 55 _3, and a gate electrode 57 ₁ Metropolitan composed of the first layer n-type polycrystalline silicon. The other transistor Qn
_2, the island-like p- well 51 regions electrically separated to form the ^{n +} -type source region ₅₄₃ to each other, a drain region 55 _4, these source and drain regions _543,
55 is arranged through a gate oxide film (not shown) on a well 51 containing a channel region between _4, the transfer gate and a gate electrode 57 ₂ which made of the first layer n-type polycrystalline silicon One of the transistors Qn ₃ has an island-shaped well 5 as shown in FIG.
The drain region 5 electrically isolated from each other in one region
5 ₃ and the source region of a common ^{n +} -type and a drain region 55
₅ and these source and drain regions (55 ₃ ), 55 ₅
It is arranged through the gate oxide film 56 in the well 51 region including a channel region between a gate electrode 57 ₃ formed of the first layer n-type polycrystalline silicon doped with phosphorus to be shared with other transistor Qn ₄ It consists of
The other transistor Qn ₄ has the drain region 55 ₄ electrically isolated from each other in the island-shaped well 51 region.
Common n ⁺ type source region and drain region 55
₆ and these source and drain regions (55 ₄ ), 55 ₆
It is arranged through a gate oxide film on the well 51 region including a channel region between, and a gate electrode 57 ₃ which consists of the first layer n-type polycrystalline silicon. In addition,
The gate electrode 57 ₃ functions as a word line WL. Wherein the ^{n +} -type source region _542, adjacent to the 54 ₃ p-well 51, ^{p +} -type diffusion region ₅₈ 1, 58 ₂ for the well bias is provided respectively.

Further, on the substrate 52 including the gate electrode ₅₇ 1-57 _3, first CVD-Si as an interlayer insulating film of the first layer
O ₂ film 59 ₁ is coated. And this CVD-
A pair of intersecting wirings 60 ₁ and 60 are formed on the SiO ₂ film 59 _1.
2 is the island-shaped substrate 52 region and the island-shaped well 51, respectively.
It is arranged so as to cross the region. One crossing wiring
60 _1, the first CV as shown in FIG. 10-FIG. 12
D-SiO ₂ film 59 contact hole 6 which is opened in ₁
1 ₁ of the transistor Qp ₁ through ^{p +} -type drain region 55 connected to p-type _one polycrystalline silicon wiring portion 62
and a, extending on the same CVD-SiO ₂ film 59 ₁ contact hole ₆₁ opened in the 2, 61 ₃ via said first layer n-type polycrystalline gate electrode 57 ₂ of the field oxide film 53 made of silicon N connected to the extension 57a and the n ⁺ -type drain region 55 ₃ of the transistor Qn ₁ respectively.
Type polycrystalline silicon wiring portion 63a and these wiring portions 62
a, 63a and a tungsten layer 64 attached to the surface
and a. P-type polycrystalline silicon connected to the transistor Qp ₂ of ^{p +} -type drain region 55 ₂ via a contact hole 61 ₄ is opened in a first CVD-SiO ₂ film 59 ₁ and the other cross-wire 60 ₂ a wiring portion 62b, extending on the same CVD-SiO ₂ film 59 ₁ apertured contact hole ₆₁ 5, 61 the ₆ through the first layer n-type multi-crystalline gate electrode 57 ₁ made of silicon field oxide film 53 out the extending portion 57b and the transistor Qn ₂ ^{n +} -type drain region 55 and the n-type polycrystalline silicon wiring portion 63b which are respectively connected to _4, the wiring unit 62b, a tungsten layer 64b which is provided stuck on 63b It consists of and. Such cross wiring 6
By providing 0 ₁ , 60 ₂ , the other CMO
The gate electrode 57 ₂ of the transistor _Qp 2, Qn ₂ constituting the S inverter, the drain region 5 of the transistor _Qp 1, Qn ₁ constituting one of the CMOS inverters
Transistor Qp, which is cross-connected to 5 ₁ and 55 ₃ through the cross wiring 60 ₁ and contact holes 61 ₁ , 61 ₂ and 61 ₃ and constitutes one of the CMOS inverters.
_1, Qn gate electrode 57 ₁ of _1, through transistor _Qp 2, Qn ₂ of the drain region ₅₅ 2, 55 ₄ the wiring for the crossing 60 _second contact holes _{61 4,} 61 5, 61 ₆ constituting the other CMOS inverter Cross connected,
This realizes a flip-flop circuit in which the CMOS inverters are cross-connected to each other.

Further, the a first CVD-SiO ₂ film 59 ₁ on the second CVD-SiO ₂ film 59 ₂ of the second interlayer insulating film is coated including the cross wiring 60 _1, 60 ₂ . The second of the CVD-SiO ₂ film 59 _{2 V SS} is on
Power source Al wirings 65 ₁ and 65 ₂ are provided. Each A
l wiring ₆₅ 1, 65 ₂ is the first, second CVD-Si
The transistor _Qn 1 via the O ₂ film ₅₉ 1, 59 contact hole ₆₁ 7 which is open over a _2, 61 _8,
It is connected to both of the n ⁺ type source regions 54 ₂ and 54 ₃ and the p ⁺ type diffusion regions 58 ₁ and 58 ₂ of Qn ₂ . Incidentally, the Al wiring 65 _1, 65 ₂ because it also serves as a wiring of each adjacent memory cell will be one located in each memory cell. In addition, the second CVD-SiO ₂
On film 58 _2, Al wiring as the bit line 6
6 ₁ , 66 ₂ (BL ₁ , BL ₂ ) are arranged, and these Al wirings 66 ₁ , 66 ₁ are formed by the first and second CVD processes.
-SiO ₂ film ₅₉ 1, 59 to the transistor _Qn 3, the drain region ₅₅ 5, 55 ₆ of Qn ₄ as the transfer gate via a contact hole ₆₁ 9, 61 _10, which is open over a ₂ are respectively connected There is. Incidentally, reference numeral 67 in the figure is a protective film covering the entire surface.

Thus, according to the present invention, as cross wiring 60 ₁ while mutually cross-connected pair of CMOS inverters,
As shown in FIGS. 10 to 12, the first CVD-SiO
Via said ₂ film 59 contact hole 61 ₁ is opened to _one of the transistors Qp ₁ ^{p +} -type drain region 55 ₁
The p-type polycrystalline silicon wiring portion 62a connected to
VD-SiO ₂ film 59 contact hole ₆₁ 2 opened in _1, 61 ₃ extending portion 57a extending over the field oxide film 53 of the gate electrode 57 ₂ formed of the first layer n-type polycrystalline silicon via And n of the transistor Qn ₁
An n-type polycrystalline silicon wiring portion 63a connected to each ⁺ type drain region 55 ₃ and a tungsten layer 64a attached to these wiring portions 62a and 63a are used. In addition, the other crossing wiring 60
₂ has a first CVD-SiO ₂ film 59 p-type polycrystalline silicon wiring portion 62b via a contact hole 61 ₄ is opened which is connected to the ^{p +} -type drain region 55 ₂ of the transistor Qp ₂ to _1, the CVD-SiO ₂ film 59 ₁ contact hole ₆₁ opened in the 5, 61 ₆ extending portion 57b which extends over the field oxide film 53 of the gate electrode 57 ₁ consisting of the first layer n-type polycrystalline silicon via and n-type polycrystalline silicon wiring portion 63b and which are respectively connected to the transistor Qn ₂ of ^{n +} -type drain region 55 _4, those which are composed of the wiring portion 62b, and the tungsten layer 64b which is provided affixed to 63b I am using. As a result, p ⁺ type and n ⁺ type drain regions 55 ₁ , 55 ₂ and 55 having different conductivity types from the intersecting wirings 60 ₁ and 60 ₂ are formed.
_3, 55 ₄ pn junction can take good contactors without being formed between, moreover p-type polycrystalline silicon wiring portion 62a, 62b and the n-type polycrystalline silicon wiring portion 6
A tungsten layer 6 is formed on each of 3a and 63b.
Since 4a and 64b are attached to each other, it is possible to eliminate the adverse electrical effect of the pn junction formed between the wiring portions of different conductivity types. Therefore, the first CVD-SiO ₂
Since the CMOS inverters can be cross-connected to each other only by the cross wirings 60 ₁ and 60 ₂ arranged on the film 59 ₁ , the second interlayer insulating film (like the conventional memory cell shown in FIGS. 2 to 4) can be formed. A pair of CMs on the second CVD-SiO ₂ film)
It is not necessary to provide an Al wiring for cross-connecting the OS inverters, and the margin of the Al wiring on the memory cell that determines the pitch width of the memory cell increases. As a result, the Al wirings 66 ₁ and 66 ₂ as bit lines are formed into
V _SS power supply Al wiring on CVD-SiO ₂ film 59 ₂ of 6
5 ₁ and 65 ₂ can be arranged. By this way the _{V SS} power line ₆₅ 1, 65 ₂ can be formed by Al, as shown in FIG. 10 n-channel MOS transistor Q
The contact hole 6 is formed over both the source regions 54 ₂ and 54 _{3 of} n ₁ and Qn ₂ and the p ⁺ -type diffusion regions 58 ₁ and 58 ₂ for well bias of the p-well 51 adjacent thereto.
It can be favorably connected via a 1 _7, 61 _8. That is, V
Because the _SS power for the Al wiring 65 _1, 65 ₂ can be also used as well bias wiring, can be added to well bias to each memory cell. Therefore, p-well 51
Since the bias point of the well 51 can be increased and the resistance of the well 51 can be effectively reduced, the latch-up resistance can be significantly improved.

Further, it is not necessary to dispose the Al wiring for the well bias as in the conventional structure shown in FIG. 2 to FIG. 4 in an area different from the memory cell, for example, every 8 cells, so that the area of the memory itself is reduced. it can.

Moreover, on the _two second CVD-SiO ₂ film _{59, V SS}
One and the power supply for the Al wiring 65 ₁ (or 65 _2), a two and a total of three of the Al wiring ₆₆ 1, 66 ₂ as bit lines, one reduces the Al wiring as compared with the conventional memory cell Therefore, the pitch width of the memory cell can be reduced. In fact, if the design rule is 1.5μm process,
The pitch width of the memory cell shown in the figure is 17.0 μm, whereas it is 1 in the memory cell shown in FIG. 10 of the present invention.
It can be remarkably reduced to 5.5 μm.

Although tungsten is used as the metal layer attached to both the p-type polycrystalline silicon wiring portion and the n-type polycrystalline silicon wiring portion in the above embodiment, it is selected from molybdenum, tantalum, platinum or the like instead of tungsten. A refractory metal may be used.

〔The invention's effect〕

As described in detail above, according to the present invention, the pitch width of the memory cell and the memory itself can be miniaturized, and a highly integrated semiconductor memory device such as a static memory having a highly improved latch-up resistance can be provided. it can.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a 6-transistor static memory having a pair of CMOS inverters, FIG. 2 is a plan view showing a memory cell of a conventional static memory, and FIG. 3 is a line XX of FIG. 4 is a sectional view taken along the line Y-Y of FIG. 2, FIG. 5 is a schematic view of a CMOS structure for explaining the latch-up phenomenon, and FIG. 6 is a thyristor effect of FIG. FIG. 7 is an equivalent circuit diagram, FIG. 7 is a plan view showing a memory cell of another conventional static memory, FIG. 8 is a sectional view taken along line XX of FIG. 7, and FIG. 9 is Y- of FIG.
FIG. 10 is a sectional view taken along line Y, FIG. 10 is a plan view of a memory cell of a static memory showing an embodiment of the present invention, FIG. 11 is a sectional view taken along line XX of FIG. 10, and FIG. It is sectional drawing which follows the YY line of FIG. Qp ₁ , Qp ₂ ... p-channel MOS transistor,
Qn ₁ , Qn ₂ , Qn ₃ , Qn ₄ ... n-channel MO
S transistor, 51 ... P-well, 52 ... N-type silicon substrate, 53 ... Field oxide film, 54 ₁ , 54
₂ , 54 ₃ ... Source region, 55 ₁ , 55 ₂ , 55 ₃ ,
55 ₄ , 55 ₅ , 55 ₆ ... Drain region, 57 ₁ , 5
7 ₂ , 57 ₃ ... Gate electrode made of first layer n-type polycrystalline silicon, 58 ₁ , 58 ₂ ... P ⁺ for well bias
Mold diffusion region, 59 ₁ ... First CVD-SiO ₂ film (first interlayer insulating film), 59 ₂ ... Second CVD-SiO ₂
Film (second interlayer insulating film), 60 ₁ , 60 ₂ ... Cross wiring, 61 _{1 to} 61 ₁₀ ... Contact hole, 62 a, 6
2b ... p-type polycrystalline silicon wiring portion, 63a, 63b ...
... n-type polycrystalline silicon wiring portion, 64a, 64b ...... tungsten _{layer, 65 1, 65 2 ...... V} SS power supply Al _wiring, 66 _1, 66 ₂ ...... Al wiring as the bit line.

Claims (3)

[Claims] 1. A flip-flop circuit having a pair of CMOS inverters, wherein the gate electrode of one CMOS inverter is cross-connected to the drain region of each transistor of the other CMOS inverter via wiring, and In a semiconductor memory device in which memory cells composed of a pair of transfer MOS transistors connected to respective nodes of a flip-flop circuit are integrated in a matrix on a semiconductor substrate, the gate electrode is of a first conductivity type. A first layer of polycrystalline silicon containing impurities,
The wiring is provided on the first-layer interlayer insulating film covering the gate electrode, and includes a first conductivity type drain region and a first conductivity type impurity connected to the gate electrode through a contact hole. A two-layer polycrystalline silicon wiring portion and a second conductive type impurity which is provided on the interlayer insulating film and connected to the wiring portion and which is connected to a drain region of the second conductive type through a contact hole; A semiconductor memory device comprising: a two-layer polycrystalline silicon wiring portion; and a metal layer attached on each wiring portion. 2. The semiconductor memory device according to claim 1, wherein the metal layer is made of a refractory metal selected from tungsten, molybdenum, tantalum and platinum. 3. A metal wiring to be one power source is provided on a second interlayer insulating film covering the wiring, and the metal wiring is used as a source region of one CMOS inverter and a substrate on which the source region is formed. 2. The semiconductor memory device according to claim 1, wherein both the source region for biasing the region and the diffusion region of opposite conductivity type are connected through a contact hole.