JPH0648724B2 - Master slice type semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a master slice type semiconductor integrated circuit device (LS).
In particular, the present invention relates to a master slice type semiconductor integrated circuit device having a macrocell structure suitable for a gate array LSI having a full surface spread type.

[Conventional technology]

In recent years, an all-overlaid gate array has been attracting attention in place of the conventional fixed channel gate array. For this, see the Proceedings of IEEE 1985 Custom.
Integrated Circuits Conference) (May 20, 1985-
23) Discussed on pages 15-17. The full-faced type is a type in which basic cells are arranged on the entire surface of the chip internal region, and the characteristics of the variable channel region are maximized to increase the number of mounted gates. This will be described with reference to the master chip configuration shown in FIG. In a peripheral area 51 on the chip 50, an external cell 52 including an input / output buffer and a bonding pad (not shown) are arranged. Basic cells 53 are spread over the entire surface in the internal region 54.
Therefore, the wiring channel is formed by the unit of the length (hereinafter referred to as height) of the basic cell in the Y-axis direction or by providing the basic cell with symmetry as described in the above-mentioned prior art document. Since the height can be selected in units of half the height of the basic cell, high-density mounting is possible.

In particular, a large macro cell can be mounted at a significantly higher density than the conventional fixed channel method, so that the effect is great. Second
In the figure, in addition to the macro cells of the ROM 55, the RAM 56, and the PLA 57, the ALU and the analog super macro are shown.
In the all-overlaid type, the macrocell has a versatility suitable for a gate array because the macrocell can be freely arranged and its capacity can be changed.

However, in order to realize them, the following problems still remain.

(1) A configuration that reduces automatic wiring by DA (design automation) and reduces the wiring area (miniaturization).

(2) Consistency of array pitch, shape, etc. between the logic blocks that make up the macro cell.

(3) A structure with a high program function for arbitrary capacity and specifications.

However, the above-mentioned publicly known examples do not refer to the configuration of the macro cell. FIG. 3 shows a ROM macrocell structure estimated from the conventional gate array structure. In FIG. 3, 11 is a 6-input-64-output address decoder, 10 is a ROM matrix, and the ROM matrix 10 is composed of a unit ROM cell 14 and an output buffer cell 60 of 1-word 1-bit configuration. The ROM matrix 10 is formed by expanding unit ROM cells in the X-axis direction and the Y-axis direction according to the number of words and the number of bits, respectively. The address decoder 11 has address signal lines 19 to 24.
In response to the above address signal, one of the word line group 125 is set to an active logic level and word data of an arbitrary address is output to the output data lines 500 to 563.

In this example, since 64 word line groups 125 are wired,
The wiring area 126 is required and becomes large. Further, the wiring needs to be performed by the automatic wiring by DA, and the number of steps is increased, and the variation of the speed is increased due to the wiring load.

[Problems to be solved by the invention]

The prior art described above has a problem that the ROM and PLA macrocells in the all-overlaid gate array are not considered in terms of configuration, the area efficiency of the macrocells is poor, and it is difficult to support DA. Furthermore, since the word line is automatically wired, the load is not reproducible and the speed varies.

An object of the present invention is to provide a macrocell having a high program function capable of easily dealing with a change in specifications while forming the macrocell in a small size.

[Means for solving problems]

In the case of the ROM macro cell, the above-mentioned purpose is to run the address line in the direction perpendicular to the basic cell row, and the address decoder cell for word selection in the unit ROM cell, which receives the address line, corresponds to the number of words of the ROM matrix. This is accomplished by juxtaposing the sides of the ROM matrix in a direction perpendicular to the rows. Further, if the address decoder has a ROM structure, the entire macro cell is made into a ROM, and it is possible to easily cope with word format and address changes by changing only the wiring mask. These are the address decoder and R
This depends on the interface between the OM matrices in the basic cell sequence.

In the case of the PLA macro cell, basically, the same structure can be achieved by replacing the address decoder with an AND matrix.

[Action]

FIG. 1 shows a basic configuration of the present invention, and the configuration and operation will be described. Hereafter, the same symbols as those mentioned above will be attached with the same symbols. ROM according to the present invention
The macro cell has an address decoder 1 as shown in FIG.
1, a ROM matrix 10 and an address input buffer group 37. The address decoder 11 comprises two logic blocks 18, 17 each consisting of two 3-input NAND gates, a logic block 16 including two 2-input NOR gates, and an output buffer block 15. The ROM matrix 10 has unit ROM cells 14 arranged in the Y-axis direction according to the number of words and in the X-axis direction according to the number of bits. Here, the unit ROM cell 14 is composed of 14a, 14b, 14c and 14d as shown by the block surrounded by the broken line in FIG. 14a to 14d correspond to 1-bit ROM subcells. For example, assume that the input / output terminal position of the unit ROM cell 14 is represented as shown in FIG. In FIG. 4, square marks represent terminal positions, and B ₀ , B ₁ (electrical equipotential terminal outputs are B ₀ ′, B ₁ ′, respectively) are bit outputs W ₀ , ₀ , W ₁ , ₁ (etc. The potential terminal signals W ₀ ′, ₀ ′, W ₁ ′, ₁ ′) are word line selection signals. One block divided into four holds one bit of data. When the word line signal W ₀ ( ₀ ) becomes '1'('0'), (14a, 14
b) and when W ₁ ( ₁ ) becomes '1'('0'), 2-bit data of (14c, 14d) are output to the bit lines B ₀ , B ₁ , respectively. The 1-word line signal is composed of true logic and its inverted logic signal. As described above, the unit ROM cell has a structure of 2 bits × 2 words. In order to match this configuration, the 3-input NAND blocks 18 and 17 are provided with the address buffer group 3 which receives the address signals 19 to 24 as input.
The outputs of 7 are commonly input to form a ROM matrix. In this way, unit address decoder cells for two words are formed on the same basic cell. When the number of address input bits is m (the number of words is 2 ^m ) and the number of bits of one word is n, the unit ROM cell is n / 2 in the X-axis direction.
2 ^m-1 are arranged in the Y-axis direction. Unit ROM
The structure and operation of the cell will be described in the embodiment shown in FIG.

As is apparent from the above description, according to the present invention, the unit address decoder cell corresponding to the configuration of the unit ROM cell is formed on the same substrate cell, and the address decoder and the ROM are formed.
The wiring between the matrices is done in the basic cell, so
No special wiring area is required. (Adjust the side terminal positions and array pitches in advance when designing the logic block). Further, in a basic cell, at least two series of PMOSs or NMOSs having a common drain or source electrode are usually arranged in the basic cell column direction, and gate electrodes are arranged in a direction perpendicular to the direction. Further, since the address signal line runs at AL2 on the address decoder / block, MOS transistors corresponding to the number of address signal lines are prepared on the unit decoder cell forming the AND gate, and the PMOS gate electrode and the NMOS gate electrode are provided. Can be connected by a modular pattern (wiring layer pattern) as appropriate to realize an arbitrary decoder specification, and thus has a feature of high versatility. That is, the decoder can also be programmed with a modi-eye pattern as with the ROM matrix (the base pattern does not need to be changed).

The details, including the modi-eye pattern, will be described in the embodiment of FIG.

As described above, the address decoder can also be structured into a ROM, and the address specification can be changed by changing the eyes.

The address buffer group 37 can be housed in the ROM macro cell.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.
FIG. 5 shows a plan view of a part of the master chip when a 4-input type basic cell pattern is adopted, and a wiring pattern of one unit ROM cell. Basic cell (base)
Is a series of four with drain or source electrodes commonly connected
It is composed of a P ⁺ diffusion layer 100 forming a PMOS transistor, a polysilicon gate electrode 102, and an N ⁺ diffusion layer 101 forming a four-row NMOS transistor in which source or drain electrodes are commonly connected, and a gate electrode 105. The N ⁺ diffusion layer 101 is formed on the P well layer (not shown). Reference numerals 103 and 104 are V _CC and GND lines formed of the first layer aluminum (AL1). Other wiring patterns are solid line W ₁ , formed of AL1,
₁ , W ₀ , ₀ word signal lines, and a thick solid line modi-eye pattern, and broken bit signal lines B ₀ , B ₁ formed by the second layer amyl (AL2). A contact hole for connecting AL1 indicated by X and the diffusion layer or the poly Si gate electrode, which is included in the wiring pattern, and a contact of an interlayer insulating film for connecting AL2 indicated by a triangle and AL2. There is a hole (hereinafter referred to as a through hole). That is, the wiring mask is a contact,
It consists of 4 pieces of AL1, through hole and AL2 mask.
In the ROM macrocell, except for the modified eye pattern, that is, the thick solid line AL1, it is a fixed layer, and only the modified eye pattern may be changed corresponding to the eyes of the ROM. This will be described below with reference to FIG. FIG. 6 shows an electrically equivalent circuit of the layout pattern of FIG. The respective constituent elements and the arrangement relationship are the same as those in FIG. The source electrodes at both ends of the two PMOSs of the four PMOSs are connected to the Vcc line through contact holes. Similarly, the source electrodes on both ends of the two NMOSs are connected to the GND line. The bit signal lines B ₀ and B ₁ of AL2 are connected to the drain electrodes of two pairs of PMOS and NMOS, respectively, via contact holes, AL1 and through holes. Therefore, two PMOS and two NMOS are connected in parallel to the bit signal line. Writing of data (eyes) of "1" and "0" is performed as follows. NM1 of NMOS and PM1 of PMOS are word signal lines To write the corresponding _{B 0} bit data, NM2 and PM2 is for writing _{B 0} bit data corresponding to the word signal line _{W 1 (1).} The '0' as the data word address '0' is written as the data '1' of the word address '1', the gate electrode 105 of the NM1 to W ₀ signal line, a gate electrode 102 of the PM2 W ₁
Just connect to the signal line. At this time, the unused gate electrode is connected to the power source potential diffusion layer through the contact hole, AL1, and the contact hole as shown in FIG. In this way, when writing "1", the inverted signal of the word line signal is
When writing "0" to the gate electrode, the word line signal is NMOS
It may be connected to the gate electrode. Data writing to the bit line B ₁ is also performed in the same manner as above using PM3, PM4, NM3 and NM4. This basic cell has a feature that a ROM can be mounted at a high density of 2 bits × 2 words.

FIG. 7 shows the structure of the wiring pattern of the address decoder 11. The symbols and their meanings are the same as the ones described above, so explanations are omitted.

However, in FIG. 7, a part of the 3-input NAND gate block group 17 (see FIG. 1) and a part of the 2-input NOR gate block group 16 in the case of 6 address inputs are shown for convenience. Also, only the unit address decoder cell for two words is shown. The block 17 comprises two 3-input NAND gate sections 17-1 and 17-2. Word signal W ₀ ~
W ₅ runs in the Y-axis direction AL2 with inversion signal generated by the address punishment Hua 202 to 207. The word signal line is connected to the logic gate electrode on the 3-input NAND block 17 by using a modifie pattern (contact hole, AL1, through hole), and at the same time, unnecessary gates of the series-connected NMOS are connected. The part is short-circuited with a mod eye pattern (contact hole, AL1). The unused PMOS gate electrode is shorted to the Vcc line. With the above procedure, it is easy to change the specifications of any address decoder. Wiring connections in the horizontal logic block as shown in FIG. 1 are connected to the signal lines 208, 209, 21.
It turns out that this is actually possible, as indicated by 0,211.

In this embodiment, the address decoder is prepared for each word, and the decoding logic is executed for each word, so that the programmable function of the address specification is high.

Another embodiment is shown in FIG. The structure of the ROM matrix section is the same as that described above, but the structure of the address decoder 11 is different. Address input is six address signals 25,
27, 29, 31, 33, 35 and their inverted address signals 26, 28, 30, 32, 34, 36 respectively.
Consists of. A pair of the upper 5 bits of the address signal and its inverted signal is commonly supplied to the 5-input NAND gate blocks 17 'and 18'. 2-input NOR of either the lower 1-bit address signal 25 or its inverted signal 26
One of the two word data of the unit ROM cell 14 is selected by inputting it to the input of the 2-input NOR gate in the gate block 16. That is, the word line signal is generated by decoding the 5 input-32 output decoder, the lower 1 bit and the decoder output.

In this embodiment, there is an advantage that the area of the address decoder section may be small. Instead, the freedom of addressing is lost. The present embodiment is not limited to the configuration shown in FIG. 8 and can be adapted to any unit ROM cell word or bit configuration. That is, the unit address decoder cell may be composed of a lower address decoder that decodes the lower few bits and an upper bit address decoder according to the word configuration, and the logic of both decoder outputs may be taken. Further, in FIG. 8, the 5-input NAND block 18 'is deleted, the output of the 5-input NAND block 17' is commonly input to the 2-input NOR block 13, and one of the 2NOR outputs is input by the address signals 25 and 26. It is possible to choose. In this case, it will be the smallest.

Before describing the embodiment of PLA, a principle diagram of PLA is shown in FIG. PLA is AND matrix 350
And OR matrix 351, and for the l-bit input signal a ₀ ... a _l-1 , m term signals T ₀ ... T _m-1 , n output signals b ₀ ... b _n-1 Logical operation of.

Since the logic of the combinational circuit is generally expressed by the above equation, the random logic can be realized by PLA. The main advantages of PLA are that many kinds of logic functions can be obtained only by changing the wiring mask during the manufacture of the circuit, and the design can be easily automated and debugged. For the specific configuration, see "MOS /
LSI design and application "(WN Car, Electronics Digest, 1977.11).

An embodiment applied to a PLA macro cell is shown in FIG. The same or the same items as those described above are designated by the same reference numerals. The PLA macrocell consists of a two-stage ROM matrix, that is, an AND matrix 11 and an OR matrix 300.
The ND matrix 11 can have the same configuration as the address decoder 11 described above. However, in this embodiment, two-input NO
In the address buffer 15 on the output side of the R block 16, an inverter for positive logic output is replaced with a 2-input NOR gate, and the precharge timing signal 301 is commonly input to the inputs of the 2-input NOR gate. There is. on the other hand,
The OR matrix 300 is formed by expanding the basic cells in the X-axis direction according to the number of output column signals and in the Y-axis direction according to the number of row signals. The output column signal numbers 305 and 306 formed by AL2 are connected to the drain electrode connection portions of the two NMOSs via the contact hole, AL1, and through hole. Both source electrodes of the two NMOSs are connected to the GND power supply line. In addition, in FIG. 9, the mark Δ is not particularly shown, but there are contact holes and AL1 in the vicinity,
It is assumed that the diffusion layer-AL2 is electrically connected.
Further, the drain electrodes of the precharge PMOS transistors 303 and 304 are connected to the output column signal lines 305 and 306, respectively.
An inverted signal of the precharge signal is input to the gate electrode of 04 through the inverter 302.

Next, the operation will be described. Precharge signal 301
Is "0" level, 2-input NOR gates 15-1 to 15-1
15-64 are all active, and the PMOS transistors 303 and 304 are turned off because both gate electrode signals are "1". Therefore, the column signal lines 305, 30
The signal of 6 receives the row signal and performs a NOR logic operation.
On the other hand, when the precharge signal 301 is at "1" level,
Since the outputs of the 2-input NOR gates 15-1 to 15-64 are all at the "0" level, the NMOS in the OR matrix is
All transistors are turned off and PMOS transistor 3
Since 03 and 304 are turned on, the column signal lines 305 and 30
6 is precharged up to the power line voltage Vcc. In this way, since the precharge and the logic operation cycle are repeated alternately,
It has the advantage of low power consumption. Further, since there is no need for a wiring region between the AND matrix and the OR matrix, there is a feature that it can be formed in a small size. In the present embodiment, the case of two column signal lines is shown, but it is obvious that it can be applied to a PLA macro having an arbitrary sum of products.

〔The invention's effect〕

According to the present invention, the wiring area for wiring between logic blocks can be reduced and the arrangement of logic blocks can be made regular, so that there is an effect that a compact ROM and PLA macrocell with high versatility can be realized. In addition, DA support becomes easy.

[Brief description of drawings]

FIG. 1 is a logic block diagram showing the basic configuration of the present invention, and FIG.
FIG. 4 is a plan view showing a master chip of an all-overlaid gate array, FIG. 3 is a logic block diagram showing a conventional macro cell, FIG. 4 is a symbol diagram of a unit ROM cell, and FIG.
6 and 7 are connection diagrams showing an embodiment of the present invention, FIG. 8 is a logic block diagram showing another embodiment of the present invention, and FIG.
FIG. 10 is a logic block / wiring diagram showing still another embodiment, and FIG. 10 is a block diagram showing the configuration of the PLA. 10 ... ROM matrix, 11 ... Address decoder, 13 ... Unit address decoder cell, 14 ... Unit ROM cell.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP 61-22649 (JP, A) JP 60-177651 (JP, A) JP 59-54255 (JP, A)

Claims (4)

[Claims] 1. A master slice type in which a basic cell consisting of at least one pair of a P-channel type MOS transistor and an N-channel type MOS transistor is arranged side by side in a lateral direction and a longitudinal direction in a chip on a main surface side of a semiconductor substrate. In a semiconductor integrated circuit device, a ROM macro cell is composed of an address decoder and a ROM matrix composed of unit ROM cells, and unit address decoder cells for word selection in a unit ROM cell of the above address decoder are formed in the basic cell column direction. A master slice type semiconductor integrated circuit device, characterized in that the unit address decoder cells are arranged in parallel to the side surfaces of the ROM matrix in a direction perpendicular to the basic cell row according to the number of words in the matrix. 2. A master slice type semiconductor integrated circuit device according to claim 1, wherein an address signal line is run in a direction perpendicular to a basic cell row on the unit address decoder cell, and the number of the address signal line is increased. A pair group of corresponding PMOS transistor and NMOS transistor is prepared, and it is possible to cope with arbitrary address specifications by connecting or not connecting the gate electrode of the MOS transistor group to the address signal line by a wiring pattern. A master slice type semiconductor integrated circuit device characterized by: 3. A master slice type semiconductor integrated circuit device according to claim 1, wherein a PLA macrocell is composed of a plurality of column planes having a common input of an input signal running in a direction perpendicular to a basic cell column, and an AND matrix. A master slice type semiconductor integrated circuit device comprising an OR matrix and the column planes arranged side by side in a direction perpendicular to the basic cell column according to the number of product terms on the side surface of the OR matrix. 4. A master slice type semiconductor integrated circuit device according to claim 3, wherein a pair of a PMOS transistor and an NMOS transistor corresponding to the column planes forming the AND matrix is prepared, and an arbitrary address specification is provided. A master slice type semiconductor integrated circuit characterized in that changes can be dealt with only by a wiring pattern.