JPH0650486B2 - Data chain processing method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data chain processing method, and more particularly to a data chain processing method for detecting and restoring a data over-line fault in an information processing system supporting a data chain function. .

[Conventional technology]

The data chain function (hereinafter abbreviated as DC function) is a function for effectively utilizing the resources of a main storage device (hereinafter abbreviated as MM).
If a byte data area is required, normally M
An empty area with a size of 100 bytes or more is required somewhere on M, but in such a case, the DC function, for example, has 50 bytes from address A, 20 bytes from address B, and 30 bytes from address C. As described above, the data area of the required size is secured by combining some empty areas. By doing so, it is possible to effectively utilize the finely divided empty areas on the MM.

Conventionally, such a DC function is provided by, for example, an MM 101 as shown in FIG. 2, a central processing unit (hereinafter abbreviated as CFU) 102, an MM 101 and a CPU 102, and a memory bus 121.
An I / O (input / output) processor (hereinafter abbreviated as IOP) 103 connected via an I / O processor 103 and a peripheral control unit (hereinafter abbreviated as PCU) 104 connected through an IPO 103 and an I / O interface 122. In the information processing system including the PCU 104 and the device 105 connected via the device interface 126, it was realized as one function of the IOP 103.

However, in recent years, VLSI (Very Large Scale Integrator)
The IOP 103 and the PCU 104 in FIG. 2 can be brought close to each other due to the miniaturization of the device such as the ted circuit), and as shown in FIG.
Tends to change to I / O bus 123. IOP1
As the bus structure between 03 and PCU104 has a PC,
The U104 can indirectly recognize the address of the MM101, and can share a part of the function conventionally performed by the IOP103. Under such circumstances, the DC function has come to be performed by the PCU 104.
In other words, the IOP 103 has come to focus on its role as a distributor from the MM 101 or the CPU 102 to each PCU 104.

Here, an outline of the DC function performed by the IOP 103 will be described. When the IOP 103 receives a command (command # 1) for instructing a data chain, the subsequent command (command # 2) is read from the MM 101 before the execution of the command # 1 is completed, and the data transfer instructed by the command # 1 is completed. Then, the next data transfer (instructed by the command # 2) is immediately prepared. This is because if the buffer in the IOP 103 runs out, it may immediately lead to a data overrun failure on the PCU 104 side, which is a lower-level device, so prompt response is required. In order to prevent the failure in the IOP 103 from being transmitted to the PCU 104, it is treated as an overrun failure (command overrun failure or data overrun failure) when the preparation of the command # 2 is not completed when the execution of the command # 1 is completed. Often.

Even if the PCU 104 comes to perform the DC function, the idea in the IOP 103 that the command # 2 is processed as an overrun failure when the command # 2 is not ready when the execution is completed is the same as the idea in the PCU 104. Was inherited as. However, from the PCU 104 side, it means that the function is added more than the conventional one, and in the conventional processor performance, the overrun failure that the preparation of the command # 2 is not in time when the execution of the command # 1 is completed as described above may occur frequently. There was sex.

[Problems to be Solved by the Invention]

In the conventional data chain processing method described above, the PCU10
Since the idea of IOP103 was inherited as it is as the definition of the overrun failure when performing the DC function in 4,
Frequent occurrence of overrun failure in CU104, that is, PCU104
However, there is a large possibility that the performance degradation of the above will be caused.

By the way, data transfer between the PCU 104 and the device 105 often depends on the performance and operation of the device 105, and the performance is generally inferior to the data transfer performance on the I / O bus 123 side. Therefore, the DC function is
In the case of 4, the PCU 104 can be aware of both the data transfer status on the I / O bus 123 side and the data transfer status on the device 105 side. Even in the case of an overrun failure in which the preparation of the command # 2 is not in time, by preparing the command # 2 before the data transfer on the device 105 side, it is possible to prevent the overrun failure from immediately becoming a data overrun failure.

In view of the above points, an object of the present invention is to detect the data overrun failure of the DC function by considering not only the data transfer status of the I / O bus side but also the data transfer status of the device side, so that the PCU can perform the DC function. An object of the present invention is to provide a data chain processing method capable of suppressing the frequent occurrence of a data overrun failure when performing.

[Means for Solving the Problems]

The data chain processing method of the present invention is an information processing system that supports a data chain function and is located between an I / O processor and a device, and the I / O processor is an I / O processor.
In the peripheral controller connected via the I / O bus and connected to the device via the device interface, the data transfer with the I / O bus is made aware of the address of the main memory via the I / O processor. From the I / O bus, a buffer for temporarily holding data from the I / O bus, a device transfer control unit for controlling data transfer with the device, and an I / O bus A buffer input side counter for counting data input to the buffer; a buffer input side next count register for storing a next count value to be continuously counted when the count of the buffer input side counter is exhausted; A buffer output counter that counts the output of data to the device, and a count of this buffer output counter A buffer output side next count register for storing the next count value to be continuously counted when exhausted, a count 0 notification of the buffer input side counter and the buffer output side counter, and the buffer input side next count register and the buffer output A data overrun detection unit that outputs a next count value setting request, a count over notification and a data overrun failure notification in response to the next count value valid signal of the side count register, and the next count value setting request from this data overrun detection unit , A processor for receiving the count-over notification and the data-overrun failure notification and performing a data chain processing and a data-overrun failure recovery processing.

[Action]

In the data chain processing method of the present invention, the I / O bus control unit controls data transfer with the I / O bus through the I / O processor in consideration of the address of the main storage device, and the buffer controls the I / O bus. Data is temporarily stored, the device transfer control unit controls data transfer with the device, the buffer input side counter counts the data input from the I / O bus to the buffer, and the buffer input side next count register Stores the next count value to be continuously counted when the buffer input side counter runs out, the buffer output side counter counts the output of data from the buffer to the device, and the buffer output side next count register outputs the buffer output. Stores the next count value that should be continuously counted when the side counter counts out, and the data overrun detection section stores the next count value. When receiving the count 0 notification of the input side counter and the buffer output side counter and the next count value valid signal of the buffer input side next count register and the buffer output side next count register, the next count value set request, count over notification and data overrun failure The processor outputs a notification and receives the next count value setting request, the count-over notification and the data-overrun failure notification from the data-overrun detection unit, and performs the data chain processing and the data-overrun failure recovery processing.

〔Example〕

 Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an information processing system to which a data chain processing method according to an embodiment of the present invention is applied. This information processing system includes an MM1 and a CPU2.
From IOP3 connected to MM1 and CPU2 via memory bus 21, PCU4 connected to IOP3 via I / O bus 22, and device 5 connected to PCU4 via device interface 26, Its main part is composed.

The PCU 4 includes an I / O bus control unit 6 connected to the I / O bus 22 and the data bus 23, a buffer 7 connected to the I / O bus control unit 6 and the data bus 24, and a buffer 7. And the device transfer control unit 8 connected to the device interface 26 via the data bus 25
And a buffer input side counter 9 which counts (subtracts) upon receiving the data input notification 31 from the buffer 7, and a buffer input which stores the next count value 41 to be continuously counted when the count of the buffer input side counter 9 is exhausted. Data output notification from side count register 10 and buffer 7 32
Buffer output counter that receives and counts (subtracts)
11 and the next count value from the buffer output side next count register 12 that stores the next count value 42 that should be continuously counted when the count value of the buffer output side counter 11 is exhausted, and the next count value from the buffer input side next count register 10 Traffic light 5
1, count 0 notification from the buffer input side counter 9 5
2, count 0 notification from the buffer output side counter 11 53
And the next count value setting request 6 in response to the next count value valid signal 54 from the next count register 12 on the buffer output side
1, countover notification 62, data overrun failure notification 6
3 and a data overrun detection unit 13 that outputs a next count value set request 64, a next count value set request 61, a count over notification 62, and a data overrun failure notification 63 that are output from the data overrun detection unit 13 controlled by the firmware. The processor 14 is configured to include a data chain process and a data overrun failure recovery process in response to a next count value set request 64.

The buffer 7 outputs a data input notification 31 each time data is transferred from the I / O bus controller 6 via the data bus 24, and transfers data to the device transfer controller 8 via the data bus 25. The data output notification 32 is output to.

The buffer input side counter 9 counts (subtracts) the next count value 41 set from the buffer input side next count register 10 each time the data input notification 31 is output from the buffer 7, and counts 0 when the count value becomes 0. Notice 52
Is output.

The buffer input side count register 10 is the processor 14
When the next count value valid signal 51 is activated while the valid next count value 41 is stored, the count value of the buffer input side counter 9 becomes 0, and the next count value 41 is set in the buffer input side counter 9. At the same time, the next count value valid signal 51 is made inactive.

The buffer output side counter 11 counts (subtracts) the next count value 42 set from the buffer output side next count register 12 each time the data output notification 32 is output from the buffer 7, and when the count value becomes 0. Count 0 notification
Outputs 53.

The buffer output side count register 12 is the processor 14
When the next count value valid signal 54 is activated while the valid next count value 42 is stored, the count value of the buffer output side counter 11 becomes 0, and the next count value 2 is set in the buffer output side counter 11. At the same time, the next count value valid signal 54 is made inactive.

Next, the operation of the data chain processing method of this embodiment configured as described above will be described.

Now, data is transferred from MM1 to memory bus 21, IPO3,
I / O bus 22, data bus 23, I / O bus controller 6,
It is assumed that data is transferred to the device 5 via the data bus 24, the buffer 7, the data bus 25, the device transfer control unit 8 and the device interface 26.

At the start of the data chain operation, the processor 14 operates the buffer input side counter 9 and the buffer output side counter 9 through the buffer input side next count register 10 and the buffer output side next count register 12 based on the first command instructing the data chain. Next count values 41 and 42 are set to 11, respectively, and the I / O bus controller 6 and the device transfer controller 8 are respectively operated.

When the data is transferred from the I / O bus controller 5 to the buffer 6 via the data bus 24, the buffer 6 outputs a data input notification 31 to the buffer input side counter 9, and the buffer input side counter 9 outputs the count value. Count (subtract) one.

Similarly, when data is transferred from the buffer 6 to the device transfer control unit 8 via the data bus 25, the data output notification 32 is output from the buffer 6 to the buffer output side counter 11, and the buffer output side counter 11 Count value 1
One counts (subtracts).

If the next count value valid signal 51 indicating that the valid next count value 41 is stored in the buffer input side next count register 10 is not active while the buffer input side counter 9 is operating, the data overrun detection unit 13 , And outputs a next count value setting request 61 to the buffer input side next count register 10 to notify the processor 14. Upon receiving the next count value setting request 61, the processor 14 stores the next count value 41 based on the next command in the buffer input side next count register 10. Therefore, the next count value valid signal 51 from the buffer input side next count register 10 becomes active, and the data overrun detection unit 13 stops the output of the next count value setting request 61.

Similarly, while the buffer output counter 11 is operating,
When the next count value valid signal 54 indicating that the valid next count value 42 is stored in the buffer output side next count register 12 is not activated, the data overrun detection unit 13 outputs the next count value 42 to the buffer output side next count register 12. The next count value set request 64 is output and notified to the processor 14.

Upon receiving the next count value setting request 64, the processor 14 stores the next count value 42 based on the next command in the buffer output side next count register 12. Therefore, the next count value valid signal from the buffer output side next count register 12
54 becomes active, and the data overrun detection unit 13 stops outputting the next count value setting request 64.

From such a state, for example, when the count value of the buffer input side counter 9 becomes 0, the buffer input side counter 9 activates the count 0 notification 52 and notifies the data overrun detection unit 13. At this point, the data transfer performance to the device 5 is usually inferior to the data transfer performance of the I / O bus 22, so the count value of the buffer output side counter 11 for counting the data transfer to the device 5 is still 0. Should not be. Therefore, in such a case, the data overrun detection unit 13 immediately outputs a countover notification 62 as a countover and notifies the processor 14 of it. Upon receiving this count-over notification 62, the processor 14 receives the count register on the buffer input side.
The next count value 41 is set from 10 to the buffer input side counter 9. If the next count value 41 is set before the count value of the buffer output side counter 11 becomes 0,
The count 0 notification 52 from the buffer input side counter 9 is immediately released, the data chain operation is continued as it is, and the data overrun failure is avoided.

However, the buffer input side counter 9 by the processor 14
When the count value of the buffer output side counter 11 becomes 0 because the next count value 41 is not set in time, the buffer output side counter 11 outputs the count 0 notification 53, and outputs the count 0 notifications 52 and 53. At the same time, the data overrun detection unit 13 outputs the data overrun failure notification 63 as a data overrun failure and notifies the processor 14 of it. Upon receiving the data overrun failure notification 63, the processor 14 performs the data overrun failure recovery process.

〔The invention's effect〕

As described above, the present invention performs the DC function in the PCU by adding not only the data transfer status on the I / O bus side but also the data transfer status on the device side to the detection of the data overrun failure of the DC function. This is effective in suppressing frequent occurrence of data overrun failure.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an information processing system to which a data chain processing method according to an embodiment of the present invention is applied, and FIG. 2 shows an example of an information processing system to which a conventional data chain processing method is applied. Block diagram, FIG. 3 is a block diagram showing another example of the information processing system to which the conventional data chain processing method is applied. In the figure, 1 ... MM, 2 ... CPU, 3 ... IOP, 4 ... PCU, 5 ... device, 6 ... I / O bus controller, 7 ... buffer, 8 ... device transfer controller , 9 ... Buffer input side counter, 10 ... Buffer input side next count register, 11 ... Buffer output side counter, 12 ... Buffer output side next count register, 13 ... Data overrun detector, 14 ... Processor, 21 …… Memory bus, 22 …… I / O bus, 23-25 …… Data bus, 26 …… Device interface, 31 …… Data input notification, 32 …… Data output notification, 41,42 …… Next count value , 51, 54 ... Next count value valid signal, 52, 53 ... Count 0 notification, 61, 64 ... Next count value set request, 62 ... Countover notification, 63 ... Data overrun failure notification.

Claims (1)

[Claims] 1. An information processing system supporting a data chain function, which is located between an I / O processor and a device, is connected to the I / O processor via an I / O bus, and has a device interface with the device. An I / O that controls data transfer with the I / O bus via the I / O processor in consideration of the address of the main storage device in the peripheral control device connected via the I / O bus.
An O bus control unit, a buffer that temporarily holds data from the I / O bus, a device transfer control unit that controls data transfer with the device, and data from the I / O bus to the buffer. A buffer input side counter that counts the input of, a buffer input side next count register that stores the next count value that should be continuously counted when the count of this buffer input side counter is exhausted, and data from the buffer to the device Output side count for counting the output of the buffer, a buffer output side next count register for storing the next count value to be continuously counted when the count of the buffer output side counter is exhausted, the buffer input side counter and the buffer Output side counter count 0 notification and buffer input side next count A data overrun detection unit that outputs a next count value setting request, a count over notification, and a data overrun failure notification in response to a next count value valid signal from the register and the next count value on the buffer output side, and the data overrun detection unit from the data overrun detection unit. A data chain processing method comprising: a processor for performing a data chain processing and a data overrun failure recovery processing in response to a next count value set request, the count over notification, and the data overrun failure notification.